ES8706987A1 - Un aparato de control del transporte de datos - Google Patents

Un aparato de control del transporte de datos

Info

Publication number
ES8706987A1
ES8706987A1 ES552383A ES552383A ES8706987A1 ES 8706987 A1 ES8706987 A1 ES 8706987A1 ES 552383 A ES552383 A ES 552383A ES 552383 A ES552383 A ES 552383A ES 8706987 A1 ES8706987 A1 ES 8706987A1
Authority
ES
Spain
Prior art keywords
storage medium
interconnecting
interface device
communication bus
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES552383A
Other languages
English (en)
Other versions
ES552383A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Espana SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Espana SA filed Critical Alcatel Espana SA
Publication of ES552383A0 publication Critical patent/ES552383A0/es
Publication of ES8706987A1 publication Critical patent/ES8706987A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bus Control (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

APARATO DE CONTROL DE TRANSPORTE DE DATOS. COMPRENDE: UN MICROORDENADOR (12), UN DISPOSITIVO CONTROLADOR DE INTERFAZ (14), UN MEDIO (16) PARA CONTROLAR UN INTERFAZ DE BUS DE COMUNICACION (18) Y UN MEDIO DE ALMACENAMIENTO (20); UN PRIMER CONTROLADOR DE ACCESO DE PUERTO DE MEMORIA (24); UN ACCESO DE PUERTO DE MEMORIA (26); MEDIOS PARA LA REGULACION DE LA COMUNICACION ENTRE LOS CONTROLADORES DE ACCESO (22, 24, 26) Y EL MEDIO DE ALMACENAMIENTO (20); Y UN BUS LOCAL (30) QUE INTERCONECTA UNA PARTE DEL MICROPROCESADOR (32), UNA MEMORIA RAM (34), UNA MEMORIA DE SOLO LECTURA ROM (36) Y UNA PARTE DE SERVICIO AUXILIAR (38). TIENE APLICACIONES EN EL CAMPO DE LA INFORMATICA.
ES552383A 1985-02-25 1986-02-25 Un aparato de control del transporte de datos Expired ES8706987A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/705,457 US4780813A (en) 1985-02-25 1985-02-25 Data transport control apparatus

Publications (2)

Publication Number Publication Date
ES552383A0 ES552383A0 (es) 1987-07-01
ES8706987A1 true ES8706987A1 (es) 1987-07-01

Family

ID=24833535

Family Applications (1)

Application Number Title Priority Date Filing Date
ES552383A Expired ES8706987A1 (es) 1985-02-25 1986-02-25 Un aparato de control del transporte de datos

Country Status (5)

Country Link
US (1) US4780813A (es)
EP (1) EP0193096A3 (es)
JP (1) JPS61195042A (es)
AU (1) AU580655B2 (es)
ES (1) ES8706987A1 (es)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2910303B2 (ja) * 1990-06-04 1999-06-23 株式会社日立製作所 情報処理装置
US6006302A (en) * 1990-06-04 1999-12-21 Hitachi, Ltd. Multiple bus system using a data transfer unit
CA2060820C (en) * 1991-04-11 1998-09-15 Mick R. Jacobs Direct memory access for data transfer within an i/o device
CN1183482C (zh) * 2000-05-31 2005-01-05 皇家菲利浦电子有限公司 消耗时间间隔与数据载体的功率消耗相适配的数据载体
US6795871B2 (en) * 2000-12-22 2004-09-21 General Electric Company Appliance sensor and man machine interface bus
US20080165717A1 (en) * 2007-01-04 2008-07-10 Ning Chen Novel MBMS user detection scheme for 3GPP LTE
US8290924B2 (en) * 2008-08-29 2012-10-16 Empire Technology Development Llc Providing answer to keyword based query from natural owner of information

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS564854A (en) * 1979-06-22 1981-01-19 Fanuc Ltd Control system for plural microprocessors
US4449183A (en) * 1979-07-09 1984-05-15 Digital Equipment Corporation Arbitration scheme for a multiported shared functional device for use in multiprocessing systems
US4371932A (en) * 1979-07-30 1983-02-01 International Business Machines Corp. I/O Controller for transferring data between a host processor and multiple I/O units
US4398246A (en) * 1980-08-12 1983-08-09 Pitney Bowes Inc. Word processing system employing a plurality of general purpose processor circuits
JPS593621A (ja) * 1982-06-30 1984-01-10 Fujitsu Ltd 高速回線制御方式
JPS59108134A (ja) * 1982-12-13 1984-06-22 Nec Corp 入出力制御方式
US4597078A (en) * 1983-10-19 1986-06-24 Digital Equipment Corporation Bridge circuit for interconnecting networks
US4604683A (en) * 1984-12-10 1986-08-05 Advanced Computer Communications Communication controller using multiported random access memory

Also Published As

Publication number Publication date
ES552383A0 (es) 1987-07-01
EP0193096A3 (de) 1990-03-21
JPS61195042A (ja) 1986-08-29
EP0193096A2 (de) 1986-09-03
AU580655B2 (en) 1989-01-27
AU5344886A (en) 1986-08-28
US4780813A (en) 1988-10-25

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Legal Events

Date Code Title Description
MM4A Patent lapsed

Effective date: 19960506