ES8106989A1 - Sistema de retencion de datos en circuitos digitales - Google Patents
Sistema de retencion de datos en circuitos digitalesInfo
- Publication number
- ES8106989A1 ES8106989A1 ES497910A ES497910A ES8106989A1 ES 8106989 A1 ES8106989 A1 ES 8106989A1 ES 497910 A ES497910 A ES 497910A ES 497910 A ES497910 A ES 497910A ES 8106989 A1 ES8106989 A1 ES 8106989A1
- Authority
- ES
- Spain
- Prior art keywords
- power
- circuit
- supply
- power failure
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/577—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices for plural loads
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2015—Redundant power supplies
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Electromagnetism (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Quality & Reliability (AREA)
- General Engineering & Computer Science (AREA)
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
PROCEDIMIENTO DE RETENCION DE DATOS EN CIRCUITOS DIGITALES DURANTE FALLOS PASAJEROS DE LA FUENTE DE SUMINISTRO DE ENERGIA. EN CONDICIONES ESTATICAS UNOS ELEMENTOS DE DIRECCIONADO Y/O ALMACENAMIENTO DEL TIPO LOGICO C-MOS O EQUIVALENTES PRESENTAN UN CONSUMO DE ENERGIA PEQUEÑO, DEBIDO A QUE LAS CORRIENTES DE FUGA SE ALIMENTAN, DURANTE LAS INTERRUPCIONES DE LA FUENTE DE SUMINISTRO PRINCIPAL, POR MEDIO DE LA CARGA ALMACENADA EN UN CONDENSADOR DE CAPACITANCIA ELEVADA (C1). EL RESTO DE LOS CIRCUITOS, INCLUYENDO LOS ELEMENTOS LOGICOS TTL QUE CONSUMEN ENERGIA, SE ALIMENTAN POR SEPARADO A TRAVES DE UN CIRCUITO QUE PRESENTA UNA CONSTANTE DE TIEMPO REDUCIDA, DE TAL MANERA QUE LA TENSION (V2) DISMINUYE CASI INMEDIATAMENTE CUANDO LA TENSION DE ALIMENTACION DE LA RED DESAPARECE. CUANDO SE RESTABLECE EL SUMINISTRO DE ENERGIA, LA INFORMACION HA SIDO CONSERVADA DEBIDO A LA PRESENCIA DE LA TENSION (V1).
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT51138/79A IT1120243B (it) | 1979-12-19 | 1979-12-19 | Perfezionamento nei sistemi di preservazione di dati in circuiti digitali in mancanza temporanea di energia elettrica di alimentazione |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| ES8106989A1 true ES8106989A1 (es) | 1981-09-16 |
| ES497910A0 ES497910A0 (es) | 1981-09-16 |
Family
ID=11274447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES497910A Granted ES497910A0 (es) | 1979-12-19 | 1980-12-18 | Sistema de retencion de datos en circuitos digitales |
Country Status (5)
| Country | Link |
|---|---|
| DE (1) | DE3047802A1 (es) |
| ES (1) | ES497910A0 (es) |
| FR (1) | FR2476348A1 (es) |
| GB (1) | GB2065942B (es) |
| IT (1) | IT1120243B (es) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3212024A1 (de) * | 1982-03-31 | 1983-10-06 | Siemens Ag | Schaltungsanordnung zur sicherung der auf einen zentralen datenuebertragungsleitungsbuendel anliegenden informationen |
| DE3332701A1 (de) * | 1983-09-10 | 1985-03-28 | kabelmetal electro GmbH, 3000 Hannover | Schaltungsanordnung fuer ein elektrisches geraet mit mikroprozessor |
| DE3723579C1 (de) * | 1987-07-16 | 1989-02-16 | Sgs Halbleiterbauelemente Gmbh | Laengsspannungsregler |
| EP0588469A1 (en) * | 1992-09-17 | 1994-03-23 | International Business Machines Corporation | Personal computer with SCSI bus power control |
| DE4404131C2 (de) * | 1994-02-09 | 1998-07-23 | Siemens Ag | Batteriefreie Datenpufferung |
| DE10116871A1 (de) * | 2001-04-04 | 2002-11-07 | Infineon Technologies Ag | Integrierte Schaltung mit geringem Energieverbrauch in einem Stromsparmodus |
-
1979
- 1979-12-19 IT IT51138/79A patent/IT1120243B/it active
-
1980
- 1980-12-17 GB GB8040359A patent/GB2065942B/en not_active Expired
- 1980-12-17 FR FR8026834A patent/FR2476348A1/fr not_active Withdrawn
- 1980-12-18 ES ES497910A patent/ES497910A0/es active Granted
- 1980-12-18 DE DE19803047802 patent/DE3047802A1/de not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| IT1120243B (it) | 1986-03-19 |
| FR2476348A1 (fr) | 1981-08-21 |
| GB2065942B (en) | 1984-07-11 |
| ES497910A0 (es) | 1981-09-16 |
| IT7951138A0 (it) | 1979-12-19 |
| GB2065942A (en) | 1981-07-01 |
| DE3047802A1 (de) | 1981-10-15 |
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