GB2065942A - Data Retention System - Google Patents
Data Retention System Download PDFInfo
- Publication number
- GB2065942A GB2065942A GB8040359A GB8040359A GB2065942A GB 2065942 A GB2065942 A GB 2065942A GB 8040359 A GB8040359 A GB 8040359A GB 8040359 A GB8040359 A GB 8040359A GB 2065942 A GB2065942 A GB 2065942A
- Authority
- GB
- United Kingdom
- Prior art keywords
- power supply
- branch
- digital circuit
- supply line
- failure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000014759 maintenance of location Effects 0.000 title claims description 28
- 239000003990 capacitor Substances 0.000 claims abstract description 21
- 230000015654 memory Effects 0.000 claims abstract description 10
- 238000001514 detection method Methods 0.000 claims abstract 2
- 238000010586 diagram Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/577—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices for plural loads
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2015—Redundant power supplies
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Electromagnetism (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Quality & Reliability (AREA)
- General Engineering & Computer Science (AREA)
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The power supply circuit for a digital circuit, e.g. a microprocessor, branches 2 to form two power supply lines V1, V2. One line V1 supplies volatile low-power consuming components of the circuit and is connected to a high valued earthed capacitor C1 which sustains the supply during a temporary power failure. The other line V2 supplies the remainder of the circuit including high power consuming components and is arranged to cease supplying power rapidly in response to power failure. A third branch may continue to supply power to a memory to which data is transferred on detection of a power failure. <IMAGE>
Description
SPECIFICATION
Data Retention System
This invention relates to a data retention
system for allowing retention of data stored in
volatile digital circuit components during
temporary mains power supply failure.
In digital electronic systems it is essential to
maintain the supply of power since even a
temporary power supply failure will destroy
information contained in volatile circuit
components such as memories, counters,
addressing systems, etc and as a result make it
necessary to reinitialize the system or to re-enter
the information lost because of the power supply
failure.
According to the invention, there is provided a
data retention system allowing retention of data
stored in volatile components of a digital circuit
means during a temporary mains power supply
failure, in which system: a power supply for the
digital circuit means has a branching power
supply line; a first branch of the line has
connected thereto a relatively high capacitance
earthed capacitor and is connected in use to the
relatively low power consuming volatile
components of the digital circuit means, the
capacitor serving to maintain a power supply to the volatile component during a temporary mains
power supply failure; and a second branch of the
line is connected in use to the rest of the digital circuit including relatively high power consuming
components of the digital circuit.
Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:
Figure 1 shows a first embodiment of a data
retention system in accordance with the invention;
Figure 2 shows a second embodiment of a data retention system in accordance with the invention;
Figure 3 shows a third embodiment of a data retention system in accordance with the invention;
Figure 4 shows the general arrangement of a first digital electronic circuit including a microprocessor to which power is supplied through a data retention system in accordance with the invention;
Figure 5 is a block diagram of a second digital electronic circuit including a micro-processor and incorporating a data retention system in accordance with the invention: and
Figure 6 illustrates graphically the variation with time of voltages at various points in the circuit of Figure 5.
Referring now to the drawings, Figure 1 shows a first embodiment of a data retention system in accordance with the invention. A general earthed power supply voltage regulator 1 receives a mains supply voltage and delivers on an output line a stabilized voltage Volt. The output line from the voltage regulator 1 is connected to ground via a resistor R 1 to allow rapid dissipation of any charge stored in smoothing capacitors arranged in the input to, or contained in, the voltage regulator.
The output line branches at a point 2 to form two separate power supply line branches providing, respectively, V1 and V2 volts.
The V1 volt power supply line branch is decoupled from the voltage regulator 1 through a diode D1 having a relatively low reverse current and an earthed capacitor C1 of relatively high capacitance whereas the V2 volt power supply line branch incorporates a compensating diode
D2, an earthed filter capacitor C2 and an earthed resistor R2 to dissipate any charge stored in the filter capacitor C2.
Thus, when the voltage on the output line from the voltage regulator 1 drops, the voltage V2 drops rapidly to zero disabling all power consuming components including transistortransistor logic elements which may be connected to the V2 volt branch. However, a voltage is retained on the V1 volt power supply line branch by the charge stored in the capacitor C1. The V1 volt power supply line branch serves to supply low power consuming memory, addressing and similar volatile circuit components and thus prevents any loss of information stored in those components during a temporary mains supply power failure.
The voltage provided on the V1 volt power supply line branch will maintain the components connected thereto in an operating state for a predetermined adjustable time. Thus, when the mains power supply is restored and hence the output voltage of the voltage regulator 1 and the voltage V2 are restored, the circuit connected to the data retention system can resume normal operation from the point at which such operation was stopped without the need for re-initialization or re-entry of data.
Figure 2 shows a second embodiment of a data retention system in accordance with the invention. A voltage regulator 1' similar to that shown in Figure 1 supplies a stabilized voltage Vout on an output line. The output line branches at point 2' forming two separate power supply line branches providing respectively V1 and V2 volts.
The V1 volt power supply line branch is identical to the corresponding V1 volt power supply line branch of the first embodiment. However, in the
V2 volt power supply line branch a resistor R3 of relatively low resistance is connected between the diode D2 and the filter capacitor C2 replacing the earthed resistor R2 of the first embodiment.
Further, contacts rl of a relay coil RL connected between earth and the input to the voltage regulator 1' bridge the capacitor C2. The contacts r1 of the relay are normally closed such that, when the mains supply voltage and of course the input voltage Vl to the voltage regulator 1' drops, the relay RL is de-energized causing the contacts rl to close, short-circuiting the V2 volt power supply line branch to earth so that the voltage provided on the V2 volt power supply line branch falls as rapidly as possible.
A third embodiment of a data retention system in accordance with the invention is shown in
Figure 3. A voltage regulator 1" similar to those of the first and second embodiments supplies on an output line a stabilized output voltage Vout.
The output line branches at a point 2" to form two supply power line branches providing respectively V1 and V2 volts, the V1 volt power supply line branch being identical to the corresponding V1 power supply line branches of the first and second embodiments.
As shown in Figure 3, the V2 volt power supply line branch is connected to the point 2" on the output line of the voltage regulator by the anode of a silicon controlled rectifier (SCR) SIR 1 which replaces the compensator diode D2.
The voltage output from the cathode of the
SCR SR1 provides the V2 voltage power supply to a circuit connected to the data retention system, the cathode being connected to ground via the filter capacitor C2. The gate of the SCRSR1is connected via a capacitor C3 to the output line of the voltage regulator 1", the capacitor C3 and the gate of the SCR SR1 being earthed via a resistor
R4.
The resistor R4 and capacitor C3 form a differentiating circuit having a low time constant which allows the SCR to be switched into a conducting mode when the voltage Vout is restored on the output line and after a mains power supply failure.
Of course, whenever the output voltage Vout of the voltage regulator 1" drops, the anode of the SCR SRI will be at a negative voltage with respect to the cathode thereof, switching the SCR SRi off. When the output voltage VOut of the voltage regulator 1" is restored, a pulse applied by the differentiating circuit R3, C4 to the gate of the
SCR causes the SCR SR1 to conduct so as to restore the voltage V2.
Figure 4 shows the general arrangement of a first digital electronic circuit including a microprocessor 12 to which power is supplied through a data retention system in accordance with the invention (not shown).
A A decoupling unit 10 formed by AND gates is driven by the voltage V2 provided Wy the V2 volt power supply line of a data retention system in accordance with the invention.
The output of the decoupling unit 10 is input to low power consuming C-MOS or other similar volatile control logic, the output of which is connected to a microprocessor 12 through a second decoupling unit 13 formed by an inverter or buffer driven by a voltage V2. The microprocessor 12 is in turn connected to a buffer 14 which drives several loads 1, 2 ... N. The V2 volt power supply line feeds all the circuit components except the low power consuming control logic 11 which is connected to the V1 volt power supply line of a data retention system in accordance with the invention.
Referring now to Figure 5, there is shown a block diagram of a second digital electronic circuit including a micro-processor,uP and incorporating a data retention system in accordance with the invention.
A power supply voltage regulator 50 connected to an input voltage V supplies on an output line an output voltage V.
The output line branches to form three power supply line branches decoupled from the output line by respective diodes D1,D2 and D3 and providing respectively V1, V2 and V3 volts.
The V1 volt power supply line branch is earthed via a relatively high capacitance capacitor C1 and provides the supply voltage for the micro processor yP and any other dissipative logic components connected thereto whereas the V2 volt power supply line branch is earthed via a resistor R2 and connected via a mains failure detector 51 to an input PA of the micro-processor yP.
The V3 volt power supply line branch is earthed via a capacitor C3 and coupled via clock protection logic to a reserve C-MOS memory register 52 connected via input and output data buses to the data input INPB and date output
OUT, respectively of the micro-processor uP.
The output from the mains failure detector 51 is input to the clock protection logic which is controlled by the strobe output OUTA from the micro-processor uP.
A resistance equivalent to that of resistor R1 (see above) is produced across the terminals of capacitor C1 in the V1 volt power supply line branch. Similarly a resistance equivalent to that of resistor R3 (see above) is produced across the terminals of the capacitor C3 on the V2 volt power supply line branch, while an input capacitance equivalent to that of capacitor C2 is to be found across the terminals of resistor R2 in the V2 volt power supply line branch.
Thus, the following time constants are associated with the V1, V2 and V3 volt power supply lines respectively: Tl=Ri.O1, T2=R2.C2 and T3=R3.C3.
The values of the various components are arranged such that: 22921 and T1 < T3.
The fact that T2 Ti allows the fall in the mains supply voltage to be detected in the shortest time possible by the mains failure detector 51 which then actuates the micro-processor IUP to start the transfer of information identifying processing steps into the saving C-MOS memory register 52.
Because Tl r3 during the time in which the micro-processor,uP is inactive, the voltage supplied in the V3 volt power supply line allows the retention of the information stored in the C
MOS memory register 52.
When the mains supply is restored a restart address from the memory register 52 causes the information stored in the memory register 52 to be returned to the micro-processor via the data input bus.
Figure 6 shows graphically the variation with time of the voltage output V1 of the power supply voltage regulator 50 and of the output voltages Vi,V2 and V3.
From the above, it follows that, in the event of a mains supply power failure, the operation of the circuit connected to a data retention system in accordance with the invention is not damaged and the circuit can resume operation from the point at which normal operation was interrupted by the power failure without any external interference.
Claims (9)
1. A data retention system for allowing retention of data stored in volatile components of a digital circuit means during a temporary mains power supply failure, in which system: a power supply for the digital circuit means has a branched power supply line; a first branch of the line has connected thereto a relatively high capacitance earthed capacitor and is connected in use to relatively low power consuming volatile components in the digital circuit means, the capacitor serving to maintain a power supply to the volatile component during a temporary mains power supply failure; and a second branch of the line is connected in use to the rest of the digital circuit including relatively high power consuming components of the digital circuit.
2. A system according to claim 1, wherein the first branch is decoupled from the power supply line by a diode having a relatively low reverse current.
3. A system according to claim 1 or 2, wherein means are provided for short-circuiting the second branch to ground.
4. A system according to claim 3, wherein the short-circuiting means comprise a relay driven circuit.
5. A system according to claim 1, 2, 3 or 4, wherein the second branch is decoupled from the power supply line.
6. A digital circuit incorporating a data retention system according to any preceding claim, wherein the first branch of the power supply line provides the supply voltage for a micro-processor, the second branch is connected via a mains failure detecting means to the microprocessor, and a third branch of the power supply line supplies power to a reserve memory means to which information stored in the microprocessor is transferred on detection of a mains failure by the mains failure detecting means, the third branch having means connected thereto to sustain the power supply to the reserve memory means after failure of the power supply to the micro-processor maintained by first branch.
7. A data retention system for allowing retention of data stored in volatile components of a a digital circuit substantially as hereinbefore described with reference to, and as illustrated in,
Figures 1, 2 or 3 of the accompanying drawings.
8. A digital circuit incorporating a data
retention system substantially as hereinbefore described with reference to Figure 4 or 5 of the
accompanying drawings.
9. Any novel feature or combination of features
herein disclosed.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT51138/79A IT1120243B (en) | 1979-12-19 | 1979-12-19 | IMPROVEMENT IN DATA PRESERVATION SYSTEMS IN DIGITAL CIRCUITS IN THE TEMPORARY LACK OF ELECTRIC POWER SUPPLY |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2065942A true GB2065942A (en) | 1981-07-01 |
| GB2065942B GB2065942B (en) | 1984-07-11 |
Family
ID=11274447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8040359A Expired GB2065942B (en) | 1979-12-19 | 1980-12-17 | Data retention system |
Country Status (5)
| Country | Link |
|---|---|
| DE (1) | DE3047802A1 (en) |
| ES (1) | ES497910A0 (en) |
| FR (1) | FR2476348A1 (en) |
| GB (1) | GB2065942B (en) |
| IT (1) | IT1120243B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0588469A1 (en) * | 1992-09-17 | 1994-03-23 | International Business Machines Corporation | Personal computer with SCSI bus power control |
| FR2716016A1 (en) * | 1994-02-09 | 1995-08-11 | Siemens Ag | Intermediate data storage method for use during power failure |
| WO2002082248A2 (en) * | 2001-04-04 | 2002-10-17 | Infineon Technologies Ag | Integrated circuit with low energy consumption in a power saving mode |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3212024A1 (en) * | 1982-03-31 | 1983-10-06 | Siemens Ag | Circuit arrangement for protecting the information present on a central data-transmission line harness |
| DE3332701A1 (en) * | 1983-09-10 | 1985-03-28 | kabelmetal electro GmbH, 3000 Hannover | Circuit arrangement for an electrical device with microprocessor |
| DE3723579C1 (en) * | 1987-07-16 | 1989-02-16 | Sgs Halbleiterbauelemente Gmbh | Longitudinal voltage regulator |
-
1979
- 1979-12-19 IT IT51138/79A patent/IT1120243B/en active
-
1980
- 1980-12-17 GB GB8040359A patent/GB2065942B/en not_active Expired
- 1980-12-17 FR FR8026834A patent/FR2476348A1/en not_active Withdrawn
- 1980-12-18 DE DE19803047802 patent/DE3047802A1/en not_active Withdrawn
- 1980-12-18 ES ES497910A patent/ES497910A0/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0588469A1 (en) * | 1992-09-17 | 1994-03-23 | International Business Machines Corporation | Personal computer with SCSI bus power control |
| FR2716016A1 (en) * | 1994-02-09 | 1995-08-11 | Siemens Ag | Intermediate data storage method for use during power failure |
| WO2002082248A2 (en) * | 2001-04-04 | 2002-10-17 | Infineon Technologies Ag | Integrated circuit with low energy consumption in a power saving mode |
| WO2002082248A3 (en) * | 2001-04-04 | 2003-07-31 | Infineon Technologies Ag | Integrated circuit with low energy consumption in a power saving mode |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2476348A1 (en) | 1981-08-21 |
| DE3047802A1 (en) | 1981-10-15 |
| IT1120243B (en) | 1986-03-19 |
| ES8106989A1 (en) | 1981-09-16 |
| IT7951138A0 (en) | 1979-12-19 |
| ES497910A0 (en) | 1981-09-16 |
| GB2065942B (en) | 1984-07-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |