ES422824A1 - Perfected procedure to make multiplications, divisions and roads square, through an analogue computer circuit. (Machine-translation by Google Translate, not legally binding) - Google Patents

Perfected procedure to make multiplications, divisions and roads square, through an analogue computer circuit. (Machine-translation by Google Translate, not legally binding)

Info

Publication number
ES422824A1
ES422824A1 ES422824A ES422824A ES422824A1 ES 422824 A1 ES422824 A1 ES 422824A1 ES 422824 A ES422824 A ES 422824A ES 422824 A ES422824 A ES 422824A ES 422824 A1 ES422824 A1 ES 422824A1
Authority
ES
Spain
Prior art keywords
multiplications
divisions
translation
signal
machine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES422824A
Other languages
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elsag Bailey Inc
Original Assignee
Bailey Meter Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bailey Meter Co filed Critical Bailey Meter Co
Priority to ES422824A priority Critical patent/ES422824A1/en
Publication of ES422824A1 publication Critical patent/ES422824A1/en
Expired legal-status Critical Current

Links

Landscapes

  • Ac-Ac Conversion (AREA)
  • Amplifiers (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

Improved procedure for making multiplications, divisions and square roots, by means of an analog computer circuit, characterized in that said circuit, with output current conditioned to the first, second and third input signals, comprises: (a) means of the first circuit responsive to the first input signal and to the second input signal for generating a frequency signal proportional to the amplitude ratio of the first input signal with the amplitude of the second input signal; y (b) means of the second circuit responsive to said signal frequency and to the third signal to generate a signal with an amplitude proportional to the product of said ratio by the amplitude of the third input signal. (Machine-translation by Google Translate, not legally binding)
ES422824A 1974-01-31 1974-01-31 Perfected procedure to make multiplications, divisions and roads square, through an analogue computer circuit. (Machine-translation by Google Translate, not legally binding) Expired ES422824A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ES422824A ES422824A1 (en) 1974-01-31 1974-01-31 Perfected procedure to make multiplications, divisions and roads square, through an analogue computer circuit. (Machine-translation by Google Translate, not legally binding)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES422824A ES422824A1 (en) 1974-01-31 1974-01-31 Perfected procedure to make multiplications, divisions and roads square, through an analogue computer circuit. (Machine-translation by Google Translate, not legally binding)

Publications (1)

Publication Number Publication Date
ES422824A1 true ES422824A1 (en) 1976-10-16

Family

ID=8465877

Family Applications (1)

Application Number Title Priority Date Filing Date
ES422824A Expired ES422824A1 (en) 1974-01-31 1974-01-31 Perfected procedure to make multiplications, divisions and roads square, through an analogue computer circuit. (Machine-translation by Google Translate, not legally binding)

Country Status (1)

Country Link
ES (1) ES422824A1 (en)

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