ES2685262T3 - Improved memory read stability using selective bit line section preload - Google Patents

Abstract

A memory device comprising: means for preloading a first section (33) of a first bit line of a first bit cell (34) of a first column to a first voltage; means for preloading a second section (31) of the first bit line of a first bit cell (34) of a first column to a second voltage, in which a second voltage is different from the first voltage; means for preloading a first section of a second bit line of a second bit cell of a second column to the first voltage; means for preloading a second section (61) of the second bit line of the second bit cell of the second column to the first voltage, wherein the first section of the second bit line is coupled to the first section of the first bit line; and means for sharing load between the first section of the first bit line, the second section of the first bit line, the first section of the second bit line and the second section of the second bit line, wherein the means to share the load they are additionally configured to couple the first section of the first bit line to the second section of the first bit line during a read or write operation when the first bit cell is selected for the read or write operation .

Description

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DESCRIPTION

Improved memory read stability using selective bit line section preload CROSSED REFERENCE ON RELATED REQUEST

[0001] This application claims the benefit of US application US20080334817.

TECHNICAL FIELD

[0002] This disclosure generally refers to integrated circuits (IC). More specifically, this disclosure refers to memory devices.

BACKGROUND

[0003] A memory device, or memory, can generally be described as hardware that can store data for later recovery. Some memory devices include a set of transistors used to store data (represented, for example, by an electrical load) and a set of transistors used to control access to the data store. Transistor sizes have shrunk to 45 nm and will soon reach 32 nm. As the sizes have decreased, the acceptable margin of errors during manufacturing has decreased. As a result, manufactured transistors exhibit greater variability during operation.

[0004] The large increase in the variability of transistor technologies has negatively affected memory devices and their reading stability. Read stability is the ability of the memory device to retain the correct data when accessed in the presence of noise. Commonly, read stability is measured using the static noise range (SNM). The large variations in the manufactured transistors cause a reduction in the static noise range of the memory device. This reduction in the static noise range decreases the robustness and tolerance of the bit cell against noise, and therefore reduces memory performance due to increased faults.

[0005] Slightly reducing the bit line voltage of a memory device compared to the supply voltage significantly improves the static noise range of the memory device. However, in memory designs, the bit line is generally preloaded to a supply voltage before accessing memory. There have been several attempts to reduce the bit line voltage to improve read stability. Previous attempts have shown great sensitivity to process, temperature and voltage variations during manufacturing, which may limit its effectiveness in improving reading stability. Some of these attempts include the pulsed bit line scheme, dual supply voltages and dynamic cell polarization.

[0006] In a pulsed bit line scheme, a reducing device is connected to the bit line. After preloading the bit line to the supply voltage, a narrow pulse is applied to the reducing device, which reduces the bit line voltage and improves read stability. This technique is very sensitive to the generation of this narrow pulse, especially since the pulse width will vary with process variations, voltage and temperature during the manufacture of transistors and environmental variations.

[0007] Another attempt uses two supply voltages, one for the bit cell, and one for the bit line, where the bit line voltage is less than the bit cell voltage. Adding additional supply voltages is a difficult task and complicates the physical design and verification of the chip.

[0008] Another attempt to reduce the bit line voltage includes the use of an NMOS device to preload the bit line, to reduce the bit line voltage in the threshold voltage of the NMOS device. In this case, a low threshold voltage NMOS device is used, which increases the complexity and cost of the process, for example, by requiring additional masks. In addition, the threshold voltage has a strong dependence on process, voltage and temperature variations.

[0009] These three attempts to improve memory read stability are sensitive to manufacturing variations and, as such, are difficult to implement and their implementation is costly. Such cost is further increased when multiple supply voltages or an NMOS device are implemented in the preload circuits. Therefore, there is a need for improved reading stability in memory designs that decrease sensitivity to manufacturing variations without incurring an additional cost. US 2004/0141362 discloses that an apparatus having a dummy bit line to decrease an apparent current gains capacity from an access transistor and increases the static noise range. Japanese patent JP03102698, published on, discloses an SRAM with load sharing between a bit line of a bit cell and a common data line, where the common data line is preloaded to ground potential and connected to the bit line of the bit cell in a read access operation.

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SHORT SUMMARY

[0010] According to the invention, a memory device according to claim 1 is provided; and a method for operating a memory according to claim 8. According to one aspect of this disclosure, a memory device includes a bit line having a first section and a second section. The memory device also includes a load sharing circuit selectively coupled to the first section and the second section, wherein the load sharing circuit is configured to couple and decouple the first section to the second section.

[0011] According to another aspect of this disclosure, a method of operating a memory device includes preloading a first section of a bit line to a first voltage and preloading a second section of the bit line to a second voltage. The second voltage is different from the first voltage. The procedure also includes load sharing between the first section of the bit line and the second section of the bit line.

[0012] According to another aspect of this disclosure, a memory device includes means for preloading a first section of a bit line to a first voltage. The memory device also includes means to preload a second section of the bit line up to a second voltage. The memory device further includes means for sharing load between the first section of the bit line and the second section of the bit line.

[0013] According to an additional aspect of the disclosure, a method for operating a memory device, which has a bit line that includes a first section and a second section, includes the step of preloading a first section of a line of bits up to a first voltage. The procedure further includes the step of preloading the second section of the bit line to a second voltage, which differs from the first voltage. The procedure also includes the stage of load sharing between the first section of the bit line and the second section of the bit line, to obtain a voltage level between the first voltage and the second voltage.

[0014] This has outlined, somewhat vaguely, the characteristics and technical advantages of the present disclosure so that the following detailed description can be better understood. Additional features and advantages of the disclosure will be described below. It should be appreciated by those skilled in the art that this disclosure can be used immediately as a basis for modifying or designing other structures to carry out the same purposes of the present disclosure. Those skilled in the art should also realize that such equivalent structures do not depart from the teachings of the disclosure, as set forth in the appended claims. The novel features, which are believed to be characteristic of the disclosure, both as regards its organization and the operating procedure, together with the additional objects and advantages, will be better understood from the following description when considered in relation to with the attached figures. However, it should be expressly understood that each of the figures is provided for purposes of illustration and description only, and is not intended to be a definition of the limits of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] For a more complete understanding of the disclosure in the present application, reference is now made to the following descriptions taken in conjunction with the accompanying drawings.

Figure 1 is an illustration of an exemplary wireless communication system in which an embodiment of the disclosure can be advantageously employed.

Figure 2A is a circuit diagram illustrating a conventional pulsed bit line scheme, for improved SRAM stability.

Figure 2B is a timing diagram illustrating a conventional pulsed bit line scheme, for improved SRAM stability.

Figure 3 is a circuit diagram illustrating the initial preload operation in the exemplary selective preload technique, according to an embodiment of the disclosure.

Figure 4 is a circuit diagram illustrating the load sharing operation in the exemplary selective preload technique, according to an embodiment of the disclosure.

Figure 5 is a circuit diagram illustrating the selection of a bit cell for a read or write operation, according to an embodiment of the disclosure.

Figure 6 is a circuit diagram illustrating the preload of bit lines up to different voltages, in the exemplary selective preload technique, according to an embodiment of the disclosure.

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Figure 7 is a timing diagram illustrating the exemplary selective preload operation, according

to an embodiment of the disclosure.

Figure 8 is a circuit diagram of a circuit for implementing the exemplary selective preload technique,

according to an embodiment of the disclosure.

Figure 9 is a block diagram illustrating a design workstation, used for the design of

circuits, layout and logic of the semiconductor integrated circuit disclosed.

DETAILED DESCRIPTION

[0016] Figure 1 shows an exemplary wireless communication system 100 in which an embodiment of the disclosure can be advantageously employed. For illustrative purposes, Figure 1 shows three remote units 120, 130 and 150 and two base stations 140. It will be recognized that typical wireless communication systems may have many more remote units and base stations. Remote units 120, 130 and 150 include memory devices 125A, 125B and 125C, created according to an embodiment of the disclosure. Figure 1 shows the direct link signals 180 from the base stations 140 and the remote units 120, 130 and 150, and the reverse link signals 190 from the remote units 120, 130 and 150 to the base stations 140.

[0017] In Figure 1, the remote unit 120 is shown as a mobile phone, the remote unit 130 is shown as a portable computer and the remote unit 150 is shown as a fixed location remote unit in a wireless local loop system . For example, the remote units may be cell phones, manual units of personal communication systems (PCS), portable data units, such as personal data assistants, or fixed location data units, such as meter reading equipment. Although Figure 1 illustrates remote units according to the teachings of the disclosure, the disclosure is not limited to these exemplary units illustrated. The disclosure may be properly employed in any device that includes memory devices manufactured in accordance with the teachings of the disclosure.

[0018] Figure 2A is a circuit scheme illustrating a conventional pulsed bit line scheme for improved memory stability. A circuit 20 includes a bit cell 21 configured to store data and is coupled to additional circuits to control the read and write behavior of circuit 20. Bit cell 21 can be a six transistor storage cell. A preload signal, PCH, is coupled to a preload circuit 22. The preload circuit 22 includes a transistor 221 coupled to a bit line, BL, a transistor 222 coupled to a reverse bit line, BLB, and a transistor 223 coupled to both the bit line, BL, and the reverse bit line, BLB. A pulse signal, PULSE, is coupled to a reducing circuit 23. The reducing circuit 23 includes a transistor 231 coupled to the bit line, BL, a transistor 232 coupled to the reverse bit line, BLB, and a transistor 233 coupled both the bit line, BL, and the reverse bit line, BLB.

[0019] For illustrative purposes, the operation of the conventional pulsed bit line scheme will now be described. Figure 2B is a timing diagram illustrating a conventional pulsed bit line scheme, to improve memory stability. Circuit 20 begins at a time 251 when the preload signal, PCH, is low and transistor 221 raises the bit line, BL, to a supply voltage, Vdd, and transistor 222 raises the reverse bit line, BLB , up to the supply voltage, VDD. At a time 252, the preload signal, PCH, is activated, turning off transistor 221, transistor 222 and transistor 223 to disconnect the bit line, BL, and the inverse bit line, BLB, from the supply voltage, VDD At time 252, a narrow positive pulse is generated in the pulse signal, PRESS. The pulse signal, PULSE, turns on transistor 231 and transistor 232 to couple the bit line, BL, and the reverse bit line, BLB, to a ground ground 206. Transistor 233 is turned off to disconnect the line from bits, BL, of the inverse bit line, BLB. A voltage reduction occurs in the bit line, BL, and in the inverse bit line, BLB. At one point 253, the pulse signal, PULSE, is again low, so the bit line, BL, and the inverse bit line, BLB, stop the voltage reduction. Although this technique reduces the bit line voltage to improve read stability, this technique is very sensitive to narrow pulse generation, especially since the pulse width will vary strongly with process, voltage and temperature variations during manufacturing. of the transistors.

[0020] With reference now to Figure 3, Figure 4 and Figure 5, an exemplary improved selective preload technique will now be described. The selective preload technique reduces the bit line voltage, to improve read stability, without being so sensitive to process, voltage and temperature variations. The bit line voltage is reduced by sharing the load between the sections of the bit line that are selectively coupled to allow sharing during read and write operations. Although SRAM memory devices will be described, the selective preload technique can be applied to any memory design, including, but not limited to, SRAM, DRAM or MRAM.

[0021] The different parts of the bit line are preloaded to different voltages (for example, Vdd and GND) and, through load sharing, the required final value of the bit line voltage is achieved. In one embodiment, the load sharing operation is divided into three parts. First, as illustrated in Figure 3, the top of the bit line is preloaded to VDD while the bottom of the bit line is preloaded to

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GND Next, as illustrated in Figure 4, load sharing switches are activated to allow load sharing between the upper or lower parts of the bit lines. Therefore, the final bit line voltage will be determined by the capacitance ratio between Cbl and C2. Finally, as illustrated by Figure 5, load sharing is disabled for all columns, while the switch remains on for a column selected for a read or write operation.

[0022] Figure 3 is a block diagram illustrating the initial preload operation in the exemplary selective preload technique. A block diagram 30 includes an upper bit line 31 together with the associated capacitance, illustrated by a capacitor 311, with a Cbl value. A lower bit line 33 has the capacitance illustrated by a capacitor 331 associated with the value of C2. The upper bit line 31 and the lower bit line 33 are coupled to a multiplex switch 32. In the block diagram 30, the multiplex switch 32 is open during initial preload to allow the upper bit line 31 to be preload to a supply voltage, VDD, and that the lower bit line 33 is preloaded to a grounding discharge, GND. Additionally, the bit cells 34 are coupled to the upper bit line 31. In another embodiment, the bit cells 34 can be coupled to the lower bit line 33.

[0023] Figure 4 is a block diagram illustrating the load sharing operation in the exemplary selective preload technique. A block diagram 40 includes the upper bit line 31, the capacitance represented by the capacitor 311, the lower bit line 33, the capacitance represented by the capacitor 331 and the multiplex switch 32. The load sharing operation occurs. closing the multiplex switch 32 to couple the upper bit line 31 to the lower bit line 33. A final voltage, Vbl, in the combination of the upper bit line 31 and the lower bit line 33, is a function of the initial voltage on the upper bit line 31, the initial voltage on the lower bit line 33, the capacitor 311 and the capacitor 331, as indicated,

and 7ZVDD * (N * CBL) _ Vdd

BL n * cbl + C2 \ + a * c2 / CBl ’

where N is the number of pairs of bit lines connected to the multiplex switch 32.

[0024] Figure 5 is a block diagram illustrating the deactivation of load sharing in the exemplary selective preload technique. A block diagram 50 includes the upper bit line 31, the capacitance represented by the capacitor 311, the lower bit line 33, the capacitance represented by the capacitor 331 and the multiplex switch 32. The multiplex switch 32 opens to disconnect the upper bit line 31 from the lower bit line 33 after the load sharing has been completed. This opening disables the load sharing operation so that the data can be read or written to bit cell 34. A multiplex switch 52 remains closed because a bit cell 54 has been selected for a read or write operation.

[0025] Figure 6 is a block diagram illustrating bit line preload to different voltages in the exemplary selective preload technique, according to another embodiment of the disclosure. In this embodiment, not all upper bit lines are loaded up to the supply voltage, Vdd. A block diagram 60 includes the upper bit line 31, the capacitance represented by the capacitor 311, the lower bit line 33, the capacitance represented by the capacitor 331 and the multiplex switch 32. The upper bit line 31 is preloaded. up to the supply voltage, VDD, and the lower bit line 33 is preloaded until grounding, GND. In this embodiment, each upper bit line can be preloaded to a different voltage. For example, a higher bit line 61 is preloaded until grounding, GND. Therefore, when load sharing occurs, the upper bit lines and the reverse upper bit lines will have a lower final voltage compared to when all the upper bit lines are preloaded to the supply voltage, Vdd. Additional bit lines can be charged to ground discharge, GND, supply voltage, Vdd, or other supply voltages (not shown) to obtain an adequate final voltage.

[0026] Figure 7 is a timing diagram illustrating the selective preload operation. The operation of the selective preload on a higher bit line, BLu, a reverse upper bit line, BLBu, a lower bit line, BLl and a lower reverse bit line, BLBl is controlled by a preload signal, PRECHG, a multiplexed signal, MUX_STATE, and a load sharing signal, CH_SH. A word line signal, WL, allows access to the upper bit line, BLu, the upper reverse bit line, BLBu, the lower bit line, BLl and the lower reverse bit line BLBl. An initial state of the circuit is at a time 711 when the preload signal, PRECHG, the multiplexing signal, MUX_STATE, the load sharing signal, CH_SH, and the word line, WL, are low. The lower bit line, BLl and the inverse lower bit line, BLBl are pre-discharged to ground, and the upper bit line, BLu, and the upper reverse bit line, BLBu, are preloaded to a supply voltage, Vdd. The supply voltage level is indicated by the dashed dashed line.

[0027] After the preload signal, PRECHG, became high (deactivating a preload circuit), the

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Load sharing is enabled when the multiplex signal, MUX_STATE, is low. As a result, at a time 712, the load sharing signal, CH_SH, remains high. The upper bit line, BLU, and the upper reverse bit line, BLBu, reduce the ground voltage, GND, in response to load sharing. In addition, the lower bit line, BLl, and the inverse lower bit line, BLBl, increase the voltage to the supply voltage, Vdd. The multiplexing signal, MUX_STATE, is high shortly before a time 713 that indicates the end of a load sharing operation. As a result, the load sharing signal, CH_SH, is low at time 713, completing the load sharing operation. The voltages of the upper bit line, BLu, the upper reverse bit line, BLBu, the lower bit line, BLl, and the lower reverse bit line, BLBl, stabilize at time 713 when the sharing operation is finished loading The reductions in the voltages of the upper bit line, BLu, and the upper reverse bit line, BLBU, increase memory read stability.

[0028] At a time 714, the word line, WL, is high, indicating that a read operation has been initiated. The voltage on the upper bit line, BLu, the upper reverse bit line, BLBu, the lower bit line, BLl, and the lower reverse bit line, BLBl, discharge to ground, GND. At a time 715 after the reading operation has been completed and the word line, WL, has been low, the preload signal, PRECHG, is low. As a result, the upper bit line, BLU, and the upper reverse bit line, BLBU, are preloaded to the supply voltage, VDD, and the lower bit line, BLL, and the lower reverse bit line, BLBl, They are preloaded to ground, GND. Shortly before a time 716, the multiplexing signal, MUX_STATE, was low, returning all signals to their initial state at time 716.

[0029] Figure 8 is a circuit diagram of a circuit for implementing the exemplary selective preload technique, according to an embodiment of the disclosure. A circuit 80 includes an upper bit line 85, BLu, and a reverse upper bit line 87, BLBu, configured to access bit cells 84. Additionally, circuit 80 includes a lower bit line 86, BLl, and an inverse lower bit line 88, BLBl. Although the bit cells 84 are shown connected to the upper bit lines 85, 87, the bit cells 84 could also be connected to the lower bit lines 86, 88. A load sharing enable circuit 81, configured to Activate load sharing, it is coupled to the multiplexing signal, MUX_STATE, and to the preload signal, PRECHRG, and emits a load sharing signal, CH_SH. The load sharing enablement circuit 81 includes an inverter 812 coupled to the multiplexing signal, MUX_STATE, a NAND gate 814 coupled to the output of the inverter 812 and the preload signal, PRECHRG, and an inverter 816 coupled to the output of the NAND gate 814. The load sharing enablement circuit 81 illustrated is only a possible combination of logic gates capable of activating load sharing. A preload circuit 891 is coupled to the upper bit lines 85, 87 and a reduction circuit 892 is coupled to the lower bit lines 86, 88. The preload circuit 891 and the reduction circuit 892 can be controlled by the signal of preload, PRECHRG.

[0030] The load sharing signal, CH_SH, and a selection signal, SELn, are inputs to a NOR gate 82, to control a load sharing circuit 83. The load sharing circuit 83 is active when the signal Load sharing, CH_SH, is high. When the load sharing circuit is active, the upper bit line 85 is coupled to the lower bit line 86 and the upper bit line 87 is coupled to the lower bit line 88. The selection signal, SELn, is use to select bit cells for read or write operations. Although only one selection signal is shown, SELn, a higher bit line, BLu, a reverse upper bit line, BLBu, a lower bit line, BLl and a lower reverse bit line, BLBl, many more can be incorporated in circuit 80. In addition, many more bit cells can be incorporated into circuit 80.

[0031] The operation of circuit 80 will now be described together with timing diagram 70. At the moment 711, the preload signal, PRECHG, is low and the multiplexing signal, MUX_STATE, is low. The output of the load sharing enable circuit 81, CH_SH, will be low. The upper bit lines 85, 87 are preloaded to the supply voltage, VDD, and the lower bit lines 86, 88 are preloaded to ground discharge. At the moment 712 after the preload signal, PRECHG, remains high (deactivating the preload circuits) while the multiplexing signal, MUX_STATE, remains low, the output of the load sharing enablement circuit 81, CH_SH, remains high. This causes the NOR gate 82 to control the load sharing circuits 83 to couple the upper bit lines 85, 87 to the lower bit lines 86, 88, which leads to a reduction in the voltage in the upper bit line, BLU, and in the upper reverse bit line, BLBU. At time 713, after the multiplexing signal, MUX_STATE, is high, the output of the load sharing enable circuit 81, CH_SH, is low. This change causes the load sharing circuits 83 to decouple the upper bit lines 85, 87 from the lower bit lines 86, 88, terminating the load sharing. At time 714, the bit cells 84 (in response to the write line signal, WL) are accessed and a read or write operation occurs.

[0032] The load sharing technique, as described by this disclosure, improves memory read stability by reducing the bit line voltage from the supply voltage. The bit line voltage is reduced by preloading a section of the bit line to a first voltage and a second section of the bit line to a second voltage. A load sharing circuit then selectively couples the two sections to

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reach a bit line voltage between the first and second voltages. The final voltage depends, in part, on the relative capacitance of the two sections of the bit line; therefore, any manufacturing variation in the devices does not affect the operation of the load sharing. In one embodiment, the first section is the upper bit line and the second section is the lower bit line.

[0033] An advantage of this disclosure is the improved read stability by reducing the bit line voltage. You can choose a precise voltage level for bit lines. As mentioned earlier, a reduction in bit line voltage improves the static noise margin (SNM) of the memory device. Both accessed bit cells and semi-selected bit cells improve, because all bit lines see a lower voltage compared to the bit cell supply voltage. Semi-selected bit cells are cells selected by an activated word line, but not selected by their bit lines.

[0034] A second advantage of this disclosure is the robustness of superior design. The disclosure does not depend on the threshold voltage of the transistor and the timing of a critical signal.

[0035] A third advantage of this disclosure is the tolerance to process variation. The proposed solution depends on the relative capacitance values that do not change with the variation of the process, voltage and temperature. The bit line voltage will be independent of the process conditions

[0036] A fourth advantage of this disclosure is the flexibility of the design. The bit line voltage value can be changed by selecting which bit line segments to preload up to Vdd and which bit line segments to preload to ground. For example, preloading a bit line, or more, to ground can allow higher delta values (changing the bit line from Vdd). For example, if the supply voltage is 1,125 volts and the upper sections are 1,125 volts and the lower sections are 1,125 volts, then the final voltage may be 1,125 volts if all bit lines are preloaded to Vdd. The delta would be 0 millivolts in this case. However, in the same case, if one of the bit lines is preloaded to ground, then the final voltage would be 1.00 volts. The delta would be 125 milliVolts in this case. Therefore, there is a high degree of flexibility with respect to the voltages to which the bit line sections can be preloaded.

[0037] A fifth advantage of this disclosure is that only one supply voltage is used. This simplifies the top-level physical design and memory verification.

[0038] The memory device, as disclosed, can be coupled to a microprocessor or other micro-electronic device. The memory device may be packaged with the microprocessor and also incorporated into a communications device. For example, the memory may be included in a mobile phone or a communications base station.

[0039] Figure 9 is a block diagram illustrating a design workstation, used for the circuit design, arrangement and logic of the disclosed semiconductor integrated circuit. A design workstation 900 includes a hard disk 901 containing operating system software, support files and design software, such as Cadence or OrCAD. The design workstation 900 also includes a screen to facilitate the design of a circuit design 910. The circuit design 910 may be the memory circuit as previously disclosed. A storage medium 904 is provided to tangibly store the circuit design 910. The circuit design 910 can be stored in the storage medium 904 in a file format such as GDSII or GERBER. The storage medium 904 may be a CD-ROM, DVD, hard disk, flash memory or other appropriate device. In addition, the design workstation 900 includes a drive apparatus 903 for accepting input from, or writing output to, the storage medium 904.

[0040] The data recorded on the storage medium 904 may specify logic circuit configurations, pattern data for photolithography masks or mask pattern data for serial writing tools, such as electron beam lithography. The data may also include logical verification data such as timing diagrams or network circuits associated with logical simulations. Providing data in storage medium 904 facilitates the design of circuit design 910 by decreasing the number of processes for designing semiconductor integrated circuits.

[0041] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the scope of the disclosure, as defined in the appended claims. For example, although SRAM memory devices have been described, the selective preload technique can be applied to any memory design, including, but not limited to, SRAM, DRAM or MRAM. In addition, the scope of the present application is not intended to be limited to the particular embodiments of the process, the machine, the manufacture, the composition of the material, the means, the procedures and the steps described in the specification. As someone moderately skilled in the art will immediately appreciate from the disclosure of the present disclosure, processes, machines, manufacturing, compositions of matter, means, procedures or stages, currently existing or subsequently developed, which perform essentially the same function can be used or achieve essentially the same result

that the corresponding embodiments described herein, in accordance with the present disclosure. Accordingly, the invention is limited only by the appended claims.

Claims (11)

one. 10 fifteen twenty 25 2. 30 35 3. Four. 40 5. Four. Five 6. fifty 7. 55 8. 60 A memory device comprising: means for preloading a first section (33) of a first bit line of a first bit cell (34) of a first column to a first voltage; means for preloading a second section (31) of the first bit line of a first bit cell (34) of a first column to a second voltage, in which a second voltage is different from the first voltage; means for preloading a first section of a second bit line of a second bit cell of a second column to the first voltage; means for preloading a second section (61) of the second bit line of the second bit cell of the second column to the first voltage, wherein the first section of the second bit line is coupled to the first section of the first bit line; Y means for sharing load between the first section of the first bit line, the second section of the first bit line, the first section of the second bit line and the second section of the second bit line, wherein the means for load sharing are additionally configured to couple the first section of the first bit line to the second section of the first bit line during a read or write operation when the first bit cell is selected for the read or write operation. The memory device of claim 1, wherein the means for sharing comprise: a load sharing circuit selectively coupled to the first section of the first bit line and the second section of the first bit line, wherein the load sharing circuit is configured to couple and uncouple the first section of the first line from bits to the second section of the first bit line. The memory device of claim 1, wherein the first section of the first bit line is preloaded to ground and the second section of the first bit line is preloaded to a supply voltage. The memory device of claim 1, further comprising a load sharing enable circuit, configured to activate the load sharing circuit when a preload circuit is idle and a multiplexed signal indicates the load sharing. The memory device of claim 1, wherein the first bit cell (34) is coupled to the second section of the first bit line. The memory device of claim 2, wherein the load sharing circuit is selectively coupled to the first section of the second bit line and the second section of the second bit line, and is configured to couple and decouple the First section of the second bit line to the second section of the second bit line. The memory device of claim 1, wherein the memory device is coupled to a microprocessor; and in which the memory device and the microprocessor are integrated into a communications device. A method for operating a memory device having a plurality of bit lines, including a first section and a second section comprising: preloading the first section (33) of a first bit line of a first bit cell (34) of a first column to a first voltage; preload the second section (31) of the first bit line of the first bit cell of the first column to a second voltage, the second voltage being different from the first voltage; preloading a first section of a second bit line of a second bit cell of a second column to the first voltage; preload a second section (61) of the second bit line of the second bit cell of the second column to the first voltage, where the first section of the second bit line is coupled to the first section of the first line of bits; load sharing between the first section of the first bit line, the second section of the first bit line, the first section of the second 5 bit line and the second section of the second bit line, to obtain a final voltage between the first voltage and the second voltage; Y couple the first section of the first bit line to the second section of the first bit line during a read or write operation when the first bit cell is selected for the read or write operation. 9. The method of claim 8, wherein the final voltage is determined, at least in part, by a capacitance of the first section of the first bit line and a capacitance of the second section of the first bit line. fifteen 10. The method of claim 8, wherein preloading the first section of the first bit line comprises preloading the first section of the first bit line to a ground voltage and preloading the second section of the first bit line comprises preload the second section of the first bit line to a supply voltage. twenty 11. The method of claim 8, further comprising: preloading a first section of a second bit line and a second section of a second bit line up to the first voltage. 12. The method of claim 8, wherein the load sharing occurs according to a 25 multiplexed status signal (MUX_STATE) when a preload circuit is inactive. 13. The method of claim 8, further comprising: storing data related to communications in the memory device.