ES2378865B1 - CONVERTER OF ELECTRICAL ENERGY OF INTERLOCKING FOUR OR MORE LEVELS AND CONTROL METHOD. - Google Patents

Abstract

Active interlock electric power converter of four or more levels and control method. # A static power converter topology of four or more levels is presented. The topology is formed by a pyramidal structure of elementary cells. Each elementary cell is formed by two elementary devices. Each elementary device consists of a controlled electronic switch and an antiparallel diode. # The switching states of the converter that allow the control of it are defined, as well as a transition strategy between switching states. # The proposed converter and control are applicable in drives of electric motors of alternating current, systems of use of renewable energies, equipment of electrical traction, systems of feeding, etc.

Description

Active interlocking electric power converter of four or more levels and control method.

Technical sector

Electronic hardware for electrical and electronic power systems.

State of the art

Multilevel conversion techniques have opened a door to advances in electric power conversion technology. For a specific semiconductor technology, these techniques allow greater power capacity per converter, greater efficiency and less harmonic distortion. Different multilevel topologies have been proposed:

-

Multilevel converters complete cascade bridge (“cascaded H-bridge”).

-

Multilevel interlocking diode converters ("clamped diode").

-

Multilevel interlocking converters by capacitors or floating capacitors (“clamped capacitor” or “fl ying capacitors”).

-

Hybrid combinations of the above.

In particular, a general topology has been proposed in:

F. Z. Peng, “A generalized multilevel inverter topology with self voltage balancing”, IEEE Transactions on Industry Applications, vol. 37, pp. 611-618, 2001.

This topology includes floating capacitors, controlled electronic switches and antiparallel diodes.

The topology contemplated in the present invention incorporates only controlled electronic switches and antiparallel diodes. Floating capacitors are not incorporated, which substantially modifies the control and the operating characteristics of the converter.

In the literature the particular case of three levels of the topology object of the present invention appears, but its extension has not been presented at more levels, and the control of the converter proposed in the literature differs from that described here.

Description of the invention

The topology of an active interlocking multilevel electric power converter, the switching states necessary for its control and a transition strategy between these switching states are defined.

Topology

Figure 1 presents the topology of a m-level converter. The circuit has m input terminals (ik, k ∈ {1, 2, ..., m}) and an output terminal (o). The number of converter levels corresponds to the number of input terminals. Between two consecutive input terminals (ik eik + 1) a capacitive element (capacitor) or a voltage source (power supply, battery, etc.) is typically connected, so that the voltage of the ik terminal is less than or equal to the terminal voltage ik + 1.

The circuit is formed by a pyramidal connection of m · (m-1) / 2 elementary cells. Each elementary cell consists of two elementary devices, as shown in Figure 1. Each elementary device consists of a controlled electronic switch (designated Spxy ySnxy; x, y ∈ {1, 2, ..., m-1 }) and an uncontrolled electronic switch (diode), connected as shown in Figure 1 (anti-parallel connection).

The controlled electronic switch can be unidirectional (iS can only be greater than or equal to zero) or bidirectional (iS can be greater than, equal to or less than zero) in current. The controlled switch can be unidirectional (vS can only be greater than or equal to zero) or bidirectional (vS can be greater than, equal to or less than zero) in voltage. The typical case is that the controlled switch be bidirectional in current and unidirectional in voltage.

The controlled electronic switch of the elementary device has two states, according to the two possible states of its control signal:

a) On: The voltage vS at the terminals of the switch is approximately zero.

b) Off: The iS current flowing through the switch is approximately zero.

The elementary device, defined by the set of controlled switch and uncontrolled switch, can be performed with a single transistor or can be performed with any combination of transistors and diodes (series, parallel, etc.) that effectively has the same functionality.

Switching states

The output terminal (o) can be galvanically connected with a low impedance to each of the input terminals (ik, k ∈ {1, 2, ..., m}) by properly controlling the status of all controlled electronic switches . M-1 control variables (cj, j ∈ {1, 2, ..., m-1}) are defined to represent the status of the control signals of the controlled electronic switches. Each controlled switch is assigned a control variable (cj) or its complementary value (cj), as indicated in Figure 2. These control variables have two possible values:

a) cj = 0, in which case all switches controlled with this associated control variable are off and those with the associated complementary value cj = 1 are on.

b) cj = 1, in which case all switches controlled with this associated control variable are on and those with the associated complementary value cj = 0 are off.

To connect the output terminal (o) to the input terminal ik, the following values are assigned to the control signals:

In this way, the m switching states that allow the output terminal to be connected to the m input terminals are defined. The following table presents a summary of these switching states:

In the switching state k, all those controlled switches that allow galvanically connecting the input terminal ik with the output terminal (o) via m-1 elementary devices are switched on with a low impedance. Additionally, other controlled switches are switched on which allow to guarantee a voltage vs blocking in the controlled switches turned off equal to the voltage difference between consecutive input terminals.

Transition between switching states

To make a transition between two adjacent switching states (transition from a switching state k to the immediately higher (k + 1) or lower (k-1)), it is necessary to change the state of m controlled switches. The switches to be turned off are turned off first and then the switches to be turned on. Let ki be the initial switching state and kf the final switching state of the transition between adjacent states.

If (kf-ki) · io> 0 (where io is the output terminal current (Figure 1)), the energy losses of the transition are concentrated in the first device that is turned on. If (kf-ki) · io <0, the energy losses of the transition are concentrated in the last device that shuts down. Therefore, a transition strategy between adjacent switching states is defined, in which in successive transitions the first switch that turns on between the switches to be switched on and the last switch that switches off between the switches to turn off is alternated. In this way, the energy losses of the successive transitions are distributed among all the switches.

Brief explanation of the drawings

Figure 1: Topology of an active interlock converter of m levels.

Figure 2: Topology of an m-level active interlock converter, with indication of the control variable assigned to each controlled switch.

Figure 3: Topology of a five-level active interlocking converter (a branch), in which Metal Oxide Semiconductor Field Effect Transistor (MOSFET) transistors of channel and enrichment type are used.

Figure 4: Topology of a five-level active interlocking converter (one branch), in which MOSFET transistors of channel n and enrichment are used, with indication of the control variable assigned to each transistor.

Figure 5: DC-DC converter (DC-DC) or single-phase DC-AC (five-phase DC) with four voltage sources and one branch.

Figure 6: Five-level cc-cc converter, with intermediate DC bus consisting of four series capacitors and two branches.

Figure 7: Five-level cc-cc or cc-ca converter with five levels, with a voltage source connected to four capacitors in series and two branches.

Figure 8: Five-phase three-phase DC-AC converter, with a voltage source connected to four capacitors in series and three branches.

Embodiments of the invention

The present invention is further illustrated by the following example, which is not intended to limit its scope.

Example 1

Five-level active interlocking converter with MOSFETs

Figure 3 shows a branch of a five-level converter in which Metal Oxide Semiconductor Field Effect Transistor (MOSFET) type n and enrichment transistors are used. The diodes shown in Figure 3 can correspond with the parasitic diode of this type of transistors or with external diodes connected in antiparallel with the MOSFET transistors, as indicated in Figure 3.

The assignment of control variables to each transistor is indicated in Figure 4. The branch has the following five switching states to allow the output terminal to be connected to each of the five input terminals:

The transition between adjacent switching states is done by first turning off the transistors to turn off and then turning on the transistors to turn on. Additionally, in successive transitions from one switching state to another, the transistor is switched off last and the transistor switched on first. For example, in the transition from switching state 2 to switching state 3, transistors Sn21 and Sn22 must be turned off and transistors Sp21, Sp22 and Sp23 must be switched on. It would proceed as follows:

a) Sequence of transistors to be turned off last in successive transitions from switching state 2 to switching state 3:

a.1)

In the first transition, the transistor that turns off last is Sn21.

a.2)

In the second transition, the transistor that turns off last is Sn22.

a.3)

In subsequent transitions the cycle defined by a.1 and a.2 is repeated.

b) Sequence of transistors to be switched on first in successive transitions from switching state 2 to switching state 3:

b.1) In the first transition, the transistor that turns on first is Sp21.

b.2) In the second transition, the transistor that turns on first is Sp22.

b.3) In the third transition, the transistor that turns on first is Sp23.

b.4) In subsequent transitions the cycle defined by b.1, b.2, and b.3 is repeated.

Figure 5, Figure 6, Figure 7 and Figure 8 show examples of converters that can be made using the branch presented in Figure 3.

Figure 5 shows a DC-DC converter (DC-DC) or single-phase DC-AC converter, in which voltage sources are connected between each pair of adjacent input terminals of the branch . These voltage sources represent systems that maintain an approximately constant voltage between their terminals such as power supplies, batteries or photovoltaic panels with a capacitor connected between their positive and negative terminals. In the output terminal a fi lter and a load are represented, represented by an inductance (LF), capacity (CF) and resistance (RL).

Figure 6 shows a cc-cc converter with two branches, in which capacitive elements are connected between each pair of adjacent input terminals of each branch. The voltage source Vcc is connected through an inductance (LFa) to the output terminal of the first branch. The output terminal of the second branch is connected to a fi lter and a load represented by a set inductance (LFb), capacity (CF) and resistance (RL).

A single-phase cc-cc or cc-ca converter with two branches is shown in Figure 7, in which capacitive elements are connected between each pair of adjacent input terminals of each branch. A voltage source of value Vcc is connected between the input terminals i1 and i5. The output terminals of the branches are connected to a fi lter and a load represented by a set inductance (LF), capacity (CF) and resistance (RL).

A three-phase dc-ac converter with three branches is shown in Figure 8, in which capacitive elements are connected between each pair of adjacent input terminals of each branch. A voltage source of value Vcc is connected between the input terminals i1 and i5. The output terminals of the branches are connected to a three-phase filter and load represented by a series inductance (LF) and resistance (RL) set per phase.

Claims (5)

one.

An active interlocking electric energy converter of four or more levels, characterized by being constituted by a pyramidal structure of m · (m-1) / 2 elementary cells, with an output terminal and m input terminals, m being the number of levels; each elementary cell is constituted by two elementary devices; each elementary device is constituted by means to interrupt the current in a controlled manner and means to interrupt the current in an uncontrolled manner.

2.

A control method of the four-level or more active interlocked electrical energy converter of claim 1, characterized in that m-1 control variables are defined (cj, j ∈ {1, 2, ..., m-1 }) to represent the status of the control signals of the controlled electronic switches, with two possible values, zero and one, indicating that the corresponding switch is off or on, respectively; the control variable cj is assigned to the diagonal of switches Snjy, and ∈ {1, 2, ..., j}, and its complementary value (cj) to the diagonal of switches Spjy, and ∈ {1, 2,. .., mj}; to electrically connect the output terminal (o) to the input terminal ik (k ∈ {1, 2, ..., m}) set cj = 0 for all j <k and set cj = 1 for all j≥k .

3.

A control method of an active interlocking electric power converter of four or more levels according to claim 2, characterized in that the successive transitions between two adjacent switching states are made by alternating the last switch to be switched off between the switches to be turned off.

Four.

A control method of an active interlocking electric power converter of four or more levels according to claim 2, characterized in that the successive transitions between two adjacent switching states are made by alternating the first switch to be switched on between the switches to be switched on.

SPANISH OFFICE OF THE PATENTS AND BRAND Application no .: 200902246 SPAIN Date of submission of the application: 23.11.2009 Priority Date: REPORT ON THE STATE OF THE TECHNIQUE 51 Int. Cl.: H02M7 / 483 (2007.01) H02M5 / 22 (2006.01) RELEVANT DOCUMENTS

Category

56 Documents cited Claims Affected

Y

F.Z.PENG A generalized multilevel inverter topology with self voltage balancing. Industry Applications Conference, 2000. Conference Record of the 2000 IEEE 8-12 October 2000, Vol. 3, pages 2024-2031, ISBN 978-0-7803-6401-1, the entire document. one

TO

2-4

Y

EP 1443648 A1 (ABB RESEARCH LTD) 04.08.2004, figures 1,2a; summary. one

TO

2-4

Category of the documents cited X: of particular relevance Y: of particular relevance combined with other / s of the same category A: reflects the state of the art O: refers to unwritten disclosure P: published between the priority date and the date of priority submission of the application E: previous document, but published after the date of submission of the application

This report has been prepared • for all claims • for claims no:

Date of realization of the report 02.04.2012

Examiner M. Argüeso Montero Page 1/4

REPORT OF THE STATE OF THE TECHNIQUE Application number: 200902246 Minimum documentation searched (classification system followed by classification symbols) H02M Electronic databases consulted during the search (name of the database and, if possible, terms of search used) INVENES, EPODOC State of the Art Report Page 2/4  WRITTEN OPINION Application number: 200902246 Date of Completion of Written Opinion: 02.04.2012 Statement

Novelty (Art. 6.1 LP 11/1986)

Claims Claims 1-4 IF NOT

Inventive activity (Art. 8.1 LP11 / 1986)

Claims Claims 2-4 1 IF NOT

The application is considered to comply with the industrial application requirement. This requirement was evaluated during the formal and technical examination phase of the application (Article 31.2 Law 11/1986).  Opinion Base.- This opinion has been made on the basis of the patent application as published. State of the Art Report Page 3/4  WRITTEN OPINION Application number: 200902246 1. Documents considered.- The documents belonging to the state of the art taken into consideration for the realization of this opinion are listed below.

Document

Publication or Identification Number publication date

D01

F.Z.PENG A generalized multilevel inverter topology with self voltage balancing. Industry Applications Conference, 2000. Conference Record of the 2000 IEEE 8-12 October 2000, Vol. 3, pages 2024-2031, ISBN 978-0-7803-6401-1, the entire document.

D02

EP 1443648 A1 (ABB RESEARCH LTD) 04.08.2004

2. Statement motivated according to articles 29.6 and 29.7 of the Regulations for the execution of Law 11/1986, of March 20, on Patents on novelty and inventive activity; quotes and explanations in support of this statement

-

Claim 1 Document D01 is the state of the art document closest to the claimed invention. It describes an active interlocking electric energy converter of four or more levels, characterized by being constituted by a pyramidal structure of m (m-1) / 2 elementary cells with an output terminal and m input terminals, where m is the number of levels Each elementary cell comprises two elementary devices and each of them comprises means for interrupting the current in a controlled manner and means for interrupting the current in an uncontrolled manner. However, the converter of document D01 includes floating capacitors that are not incorporated in the claimed device. This difference modifies the control and the operating characteristics of the converter. On the other hand, document D02 refers to a three-level inverter consisting of a pyramidal structure of elementary cells with an output terminal and m input terminals, m being the number of levels. Each elementary cell is constituted by two elementary devices and, each of them, by means to interrupt the current in a controlled way and means to interrupt the current in an uncontrolled way. In view of the device of document D02, the person skilled in the art can apply it to the device of document D01, arriving at the claimed invention. Therefore, the combination of documents D01 and D02 affects the inventive activity of claim 1 (art. 8 LP). - Claims 2-4 Document D01 is the state of the art document closest to the claimed invention. The electric power converter described in this document is controlled by a method characterized by defining control variables, which have two possible values, zero and one, which indicate that the corresponding switch is off or on, respectively. Each of the switches corresponding to a cell (Snjy and Spjy) is assigned complementary values of the control variable, indicating that one of them will be open and another closed. The difference with the claimed invention is that in document D01 it is not explicitly stated that cj = 0 for all j <k and cj = 1 for all j> = k. Although document D01 does indicate that there are different alternatives for electrically connecting the output terminal to the input terminal ik, the choice of the claimed method is not specified. Nor does document D02 describe a method as claimed. That is, none of the recovered documents or a relevant combination thereof affects the novelty or inventive activity of claims 2-4.

State of the Art Report Page 4/4