ES2215838T3 - EEPROM AND PROCEDURE FOR THE ACTIVATION OF THE SAME. - Google Patents

Abstract

The EEPROM has several memory cells arranged in a memory cell region. The memory cells are accessed via word, bit and source lines for writing, reading out and erasing of data. The memory is divided into groups by memory cells accessed via individual word lines. A separate source line is provided for each group. The EEPROM is operated by group writing, readout, and/or erasing of data via individual word lines. The word lines are composed of a selection line and a control line. The memory cells are composed of a selection transistor and a storage transistor with their drains connected to each other.

Description

EEPROM and procedure for the activation of the same.

The present invention relates to an EEPROM according to the preamble of claim 1 of the patent and to a procedure for activation according to the preamble of the patent claim 14. It is known from EP 0 637 035 A1 an EEPROM with the characteristics of the preamble of the patent claim 1.

EEPROMs and procedures for activation of the same for the registration, reading and deletion of data have been known for a long time and are used every time in greater extent.

A practical example of the structure and activation of a conventional EEPROM with reference to figures 2 and 3.

The conventional EEPROM described has a plurality of memory cells arranged in a cell field of memory, which can be addressed by means of lines of words, bits and respective sources.

An exemplary structure of a single cell of memory (for memorizing a single bit of data) is represented in figure 2.

The memory cell shown in Figure 2 features a T1 selection transistor and a memory transistor T2

The selection transistor T1 is a transistor of "normal" field effect, whose mode of operation and whose function They are known, and do not require an additional explanation.

The T2 memory transistor is a door floating (no connection) with a field effect transistor that presents tunnel windows, whose mode of operation and function they are equally known by virtue of widespread employment in EEPROM memory cells and, therefore, do not require a Additional explanation.

From the selection transistor T1, the section source is connected to a BL bit line, the section of door is connected to a selection line SG and the section of drain is connected to the drain section of the transistor of T2 memory.

From the memory transistor T2, the section of source is connected to a source line SL, the section of control gate is connected to a CG control line and the drain section is connected to the drain section of the T1 selection transistor.

The SG selection line and the CG control line together they form a so-called WL word line.

The mentioned signal lines lead, to reading, erasing and writing, the following signals, being U_ {pp} a high voltage, for example, approximately 15 V to 20 V:

BL SG CG Reading \ approx 4 V 5 V approx 1.2 V Erased 0 V U_ {pp} U_ {pp} Writing U_ {pp} / 0 V U_ {pp} 0 V

The memory cell shown in Figure 2 is can group, in the case of pressure of a corresponding number of the same, to form a field of memory cells.

The structure of a memory cell field of this type is represented in figure 3.

Figure 3 shows a representation schematic of a memory cell field of an RRPROM conventional.

The memory cell field shown shows a plurality of individual memory cells, identified in each case with an "O" according to figure 2, which are arranged in several (m) rows and several (n) columns.

The n elements of each of the rows of the memory cell field are connected, respectively, with a common word line WL_ {0}, WL_ {1} ... WL_ {m} (which is consisting, respectively, of a selection line SG and a CG control line). The m elements of each of the columns of the memory cell field are connected respectively with a common bit line BL_ {0}, BL_ {1} ... BL_ {n}. The SL source lines of all memory cells in the field of memory cells are grouped to form a source line common.

The connection of memory cells to form a field of memory cells constituted as a matrix, shown in figure 3, allows the addressing of the memory cells through the corresponding activation of the word, bit and font lines individually (during registration and reading of data) or line by line (during data deletion).

The EEPROMs constituted in this way are increasingly used in chip cards, whose Memory content must be updated, sometimes determined, according to intermediate modifications (for example, the rate card of a phone card). Such updates require deletion and next overwrite of EEPROM memory areas.

The expense that must be made for this is disproportionately high, especially in the very frequent case of that only small amounts of data should be updated and, if not additional security measures are taken, cannot be excluded totally that the desired update is not performed correctly in certain circumstances, in the case of unfortunate coincidence of rare states of exception.

Therefore, the present invention has the committed to develop an EEPROM according to the preamble of the patent claim 1 and a method for activation thereof according to the preamble of claim 14 of the patent, so that the update of memorized data in an always simple, adequate, fast way and largely not prone to interference.

This task is solved, according to the invention, by means of the characteristics claimed in the part of characterization of claim 1 of the patent and of the characteristics claimed in the characterization part of the patent claim 14, respectively.

Accordingly, it is planned to divide the memory cells, which can be addressed through a individual word line, in a plurality of groups of different size, to each of which a line is associated from a separate common source (patent claim 1) or carry out a description, reading and / or deletion by groups of the memory cells that can be addressed through a Individual word line (patent claim 14).

These measures make it possible to limit a registration, reading and above all also a deletion of data from a selective way to fully determined data, which was not possible so far by virtue of the forecast only of a single common source line for all memory cells in the field of memory cells at least during deletion (deletion it could only be done line by line).

Data update, which is carried out through a deletion of the data to be updated and a next overwrite by means of the updated data, it can therefore perform, under exclusive access to the data to to update.

That is, through the forecast of measures according to the invention, as opposed to the steps that must be done so far for the data update, namely

(one)

 memory change full of the contents of memory cells that can be addressed through a word line (field row of memory cells).

(two)

 deletion of data memorized in the row of the memory cell field, Y

(3)

 deed of non-updatable data return and new data writing upgradeable in the row of the memory cell field erased,

it is possible to dispense with a change of memory, erasure and write-back of the non-updated data.
bles.

The omission of these additional processes prevents, for example, in a reliable way that, in the case of a power supply interruption, stay in the EEPROM data temporarily deleted (data placed at a value of deleted as "0000 ..." or "1111 ...") instead of data not upgradeable

The data update can be done, also, more quickly and with reduced energy use in by virtue of the reduced number of read, write and erased.

The reduced number of writing processes also increases the life span of memory cells that only perform a small number of writing processes (resistance).

Advantageous developments of the invention are Subject of the dependent claims.

The invention will be explained in detail below. with the help of an exemplary embodiment with reference to drawings. In this case:

Figure 1 shows a representation schematic of an example of realization of field writing of memory cells of an EEPROM configured according to the invention.

Figure 2 shows a representation schematic of the structure of an EEPROM memory cell, and

Figure 3 shows a schematic representation of the structure of a field of memory cells
Conventional EEPROM

The memory cell field shown in the Figure 1 is constituted, as the field of memory cells conventional shown in figure 3, by a plurality of cells of conventional memory, identified in each case, by the "O" symbol (for example, memory cells of type shown in figure 2), which are arranged in a plurality (m) of rows and in a plurality (n) of columns.

The n elements of each row of the field memory cells are connected, respectively, with a line common word WL_ {0}, WL_ {1} ... WL_ {m} (which is consisting, respectively, of a selection line SG and a CG control line). The m elements of each of the columns of the memory cell field are connected respectively with a common bit line BL_ {0}, BL_ {1} ... BL_ {n}.

However, as opposed to the cell field of conventional memory shown in figure 3, the source lines of memory cells are no longer grouped to form a common source line for all memory cells in the field of memory cells.

Instead, a plurality of separate SL source lines (in figure 1 are shown as a example SL_ {0}, SL_ {1} and SL_ {n}), each of which is associated with a certain group of memory cells within a row in the field of memory cells. Expressed from another way, memory cells of a row of cell field of memory are divided into several groups, each of the which presents a separate, but common source line for memory cells of a respective group.

In general, a group of memory cells it will contain in practice as many memory cells as bits present a data word (for example, one byte) and it will be provided for each row of the memory cell field a plurality of identical memory cell groups of this type, placed adjacent (juxtaposed).

However, in general terms, each row of the memory cell field may present, according to the needs, a discretionary plurality of groups (at least two), which may be the same or different size, may comprise a discretionary number of memory cells (at least one), and whose individual elements or memory cells may be Discretionary distributed over the field row of memory cells

One of the possibilities that derive from it, which differ, in general, from those mentioned, is that memory cells of every x word of data within a row of memory cell field meet in a group (by example, to be able to modify in common the attributes of representation associated with each sign of a text to represent.

In the representation of figure 1 are shown Three groups of memory cells. The first group (left according to Figure 1) consists of three adjacent memory cells each other, whose source lines are grouped to form a separate common SL_ {0} source line. The next second group (central according to figure 1) is constituted by four cells of memory adjacent to each other, whose source lines are grouped to form a separate common SL_ {1} source line. The third group (right according to figure 1) consists of two cells of memory adjacent to each other, whose source lines are grouped to form a common SL_ {2} source line separated.

The division into groups is the same for all rows of the memory cell field in the embodiment example represented. The respective common source lines of the groups corresponding to each other in different rows of the cell field of memory are connected to each other. Such a structure it limits, in effect, the necessary expense for the realization of the field of memory cells, but it is obviously not necessarily necessary. Instead, each row of the memory cell field it can be divided in a totally independent discretionary way of the other rows, and the source lines of the groups respective can be tended and activated in a totally independent of each other.

The described configuration of the cell field of EEPROM memory enables (using a control device corresponding) a description read and / or deleted by groups of memory cells that can be addressed through a individual word line, a group may be constituted, as already indicated above, in the extreme case also just for a single memory cell.

The individual memory cells of the EEPROM memory cells can therefore be addressed in a selective manner, in a discretionary number and distribution, for the registration, reading and deletion of
data.

This has an advantageous effect. especially during data erasure and during update (deleted + new registration) of data, since in the fields of conventional memory cells, as already mentioned at In principle, only deletion in units was possible (in certain very large circumstances) of rows of the field of memory cells

Deletion of an individual group is carried out within a row of memory cell field driving the BL bit line (s) of memory cells of the group to be deleted with 0 V, and driving the selection line SG and the control line CG of the corresponding group, respectively, with a high voltage, for example, from +15 to +20 V.

The remaining group within the row of the respective memory cell field driving, otherwise maintaining identical conditions, the (s) BL bit line (s) of the memory cells of the group (s) that should not be deleted equally with a voltage high, for example from +15 to +20 V.

The respective source lines of the groups of memory cells are in this case selectively maintained in floating state (not actively activated) (when a high voltage actively activated on the associated bit lines in the same way as when left unchecked) or connected with mass (in all other cases).

The processes during the registration and reading of data do not require any adaptation to the structure of the
EEPROM according to the invention. In the same way, the new structure opens possibilities to also modify these processes in an advantageous way.

To reliably prevent it through the drive of the different signal lines with high voltage, an accumulation of charge occurs, possibly leading to a modification of the data, in memory cells, is you can expect not to apply high voltage immediately throughout its height, but apply it only little by little (staggered and / or on ramp) upwards until the theoretical value is reached.

Claims (20)

1. EEPROM with a plurality of memory cells arranged in a field of memory cells that can be addressed by means of word, bit and source lines (WL, BL, SL) for description, writing and deletion , the cells of the memory being divided, which can be addressed through an individual word line (WL), in a plurality of groups, to each of which a separate common source line (SL) is associated, characterized because the memory cell groups of a row in the memory cell field have different sizes. 2. EEPROM according to claim 1, characterized in that the word lines (WL) are composed, respectively, of a selection line (SG) and a control line (CG). 3. EEPROM according to claim 1 or 2, characterized in that the memory cells are connected, respectively, by a selection transistor (T1) and by a memory transistor (T2), whose drain sections are connected to each other. 4. EEPROM according to claim 3, characterized in that the door sections of the selection transistors (T1) are connected, respectively, with one of the selection lines (SG). 5. EEPROM according to claim 3 or 4, characterized in that the source sections of the selection transistors (T1) are connected, respectively, with one of the bit lines (BL). 6. EEPROM according to one of claims 3 to 5, characterized in that the control gate sections of the memory transistors (T2) are connected, respectively, with one of the control lines (CG). 7. EEPROM according to one of claims 3 to 6, characterized in that the source sections of the memory transistors (T2) are connected, respectively, with one of the source lines (SL). 8. EEPROM according to one of claims 2 to 7, characterized in that the memory cells provided in the same row of the memory cell field are connected, respectively, with the same selection and control lines (SG, CG). 9. EEPROM according to one of the preceding claims, characterized in that the memory cells provided in the same column of the memory cell field are connected, respectively, to the same bit line (BL). 10. EEPROM according to one of the preceding claims, characterized in that the memory cells provided in the same column of the memory cell field are connected, respectively, to the same source line (SL). 11. EEPROM according to one of the preceding claims, characterized in that a memory cell is designed for memorizing a data bit. 12. EEPROM according to one of the preceding claims, characterized in that a group of memory cells is designed for the memorization of a data word, which is constituted by a discretionally large number of data bits. 13. EEPROM according to claim 12, characterized in that the data word is a data byte. 14. Method for activating an EEPROM according to one of claims 1 to 13, wherein the memory cells, which can be addressed through a single word line (WL), are described, read and / or deleted. by groups, characterized in that several groups of memory cells are treated as a common group. 15. Method according to claim 14, characterized in that for deleting the data of a group of memory cells essentially 0 V is applied to the respective bit lines (BL) of the group of memory cells to be deleted, as well as a voltage high (U_ {pp}) to the respective selection line (SG) and control line (CG). 16. Method according to claim 15, characterized in that the source line (SL) of a group of memory cells to be erased is essentially placed in bulk. 17. Method according to claim 15 or 16, characterized in that in order not to erase data from groups of memory cells that should not be deleted, a high voltage (U_ {pp}) is applied to the bit lines (BL) of the cell group of memory that should not be deleted. 18. Method according to claim 17, characterized in that the source line (SL) of a group of memory cells that should not be deleted is kept floating. 19. Method according to one of claims 14 to 18, characterized in that high voltage (U_ {pp}), to be applied, if necessary, to respective signal lines of a group of memory cells, especially during selective erasure, is it increases after application only gradually to its theoretical value. 20. Method according to claim 19, characterized in that the ascent is carried out in a staggered and / or ramp way.