ES2172430A1 - Flicker reduction for interlaced displays - Google Patents

Flicker reduction for interlaced displays

Info

Publication number
ES2172430A1
ES2172430A1 ES200002473A ES200002473A ES2172430A1 ES 2172430 A1 ES2172430 A1 ES 2172430A1 ES 200002473 A ES200002473 A ES 200002473A ES 200002473 A ES200002473 A ES 200002473A ES 2172430 A1 ES2172430 A1 ES 2172430A1
Authority
ES
Spain
Prior art keywords
line
data
synthetic
colour data
colour
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
ES200002473A
Other languages
Spanish (es)
Inventor
Yoshihito Iwanaga
Shizuka Matsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Namco Ltd
Original Assignee
Namco Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Namco Ltd filed Critical Namco Ltd
Publication of ES2172430A1 publication Critical patent/ES2172430A1/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Processing (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Information Transfer Between Computers (AREA)
  • Picture Signal Circuits (AREA)
  • Television Systems (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

An image generation method to reduce flicker on an interlaced display including the step of synthesising colour data of an objective line B and colour data of an adjacent line on a frame image at a predetermined ration to make a synthetic colour data, to generate a field image on the basis of the synthetic colour data. This reduces flicker by reducing the lightness difference between adjacent line. Synthesising of colour data may be achieved using pixel interpolation. Preferably first synthetic data B<SB>U</SB> is found using the line above the objective line A and second synthetic data B<SB>L</SB> is found using the line below the objective line C, a second processing step may then be included to synthesize the first and second synthesised data by executing a translucent synthesis process to generate a field image.
ES200002473A 2000-07-19 2000-10-16 Flicker reduction for interlaced displays Pending ES2172430A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000219810A JP2002044486A (en) 2000-07-19 2000-07-19 Information storage medium, picture generation device, picture generation system, picture generation method and picture generation program

Publications (1)

Publication Number Publication Date
ES2172430A1 true ES2172430A1 (en) 2002-09-16

Family

ID=18714524

Family Applications (1)

Application Number Title Priority Date Filing Date
ES200002473A Pending ES2172430A1 (en) 2000-07-19 2000-10-16 Flicker reduction for interlaced displays

Country Status (7)

Country Link
JP (1) JP2002044486A (en)
CA (1) CA2322250A1 (en)
DE (1) DE10052481C2 (en)
ES (1) ES2172430A1 (en)
FR (1) FR2812159B1 (en)
GB (1) GB2365298B (en)
IT (1) ITMI20002389A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111738902A (en) * 2020-03-12 2020-10-02 超威半导体(上海)有限公司 Large convolution kernel real-time approximate fitting method based on bilinear filtering image hierarchy

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07296146A (en) * 1994-04-25 1995-11-10 Nippon Telegr & Teleph Corp <Ntt> Image display method
WO1996010887A1 (en) * 1994-09-30 1996-04-11 Cirrus Logic, Inc. Flicker reduction and size adjustment for video controller with interlaced video output
EP0710018A2 (en) * 1994-10-31 1996-05-01 Victor Company Of Japan, Ltd. Scanning line interpolating apparatus with a motion vector detector
US5663772A (en) * 1994-03-29 1997-09-02 Matsushita Electric Industrial Co., Ltd. Gray-level image processing with weighting factors to reduce flicker
WO1999000785A1 (en) * 1997-06-27 1999-01-07 Cirrus Logic, Inc. System and method for conversion of progressive scanned images to television input formats
US6028589A (en) * 1995-10-13 2000-02-22 Apple Computer, Inc. Method and apparatus for video scaling and convolution for displaying computer graphics on a conventional television monitor
JP2002014667A (en) * 2000-06-29 2002-01-18 Mitsubishi Electric Corp Image compositing and processing device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3953668A (en) * 1975-05-27 1976-04-27 Bell Telephone Laboratories, Incorporated Method and arrangement for eliminating flicker in interlaced ordered dither images
NL7900324A (en) * 1979-01-16 1980-07-18 Philips Nv GRID INTERPOLATION CIRCUIT.
US4454506A (en) * 1981-09-04 1984-06-12 Bell Telephone Laboratories, Incorporated Method and circuitry for reducing flicker in symbol displays
US5742349A (en) * 1996-05-07 1998-04-21 Chrontel, Inc. Memory efficient video graphics subsystem with vertical filtering and scan rate conversion
WO1999000758A1 (en) * 1997-06-26 1999-01-07 Charles Schwab & Co., Inc. System and method for automatically providing financial services to a user using speech signals
US6130723A (en) * 1998-01-15 2000-10-10 Innovision Corporation Method and system for improving image quality on an interlaced video display

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5663772A (en) * 1994-03-29 1997-09-02 Matsushita Electric Industrial Co., Ltd. Gray-level image processing with weighting factors to reduce flicker
JPH07296146A (en) * 1994-04-25 1995-11-10 Nippon Telegr & Teleph Corp <Ntt> Image display method
WO1996010887A1 (en) * 1994-09-30 1996-04-11 Cirrus Logic, Inc. Flicker reduction and size adjustment for video controller with interlaced video output
EP0710018A2 (en) * 1994-10-31 1996-05-01 Victor Company Of Japan, Ltd. Scanning line interpolating apparatus with a motion vector detector
US6028589A (en) * 1995-10-13 2000-02-22 Apple Computer, Inc. Method and apparatus for video scaling and convolution for displaying computer graphics on a conventional television monitor
WO1999000785A1 (en) * 1997-06-27 1999-01-07 Cirrus Logic, Inc. System and method for conversion of progressive scanned images to television input formats
JP2002014667A (en) * 2000-06-29 2002-01-18 Mitsubishi Electric Corp Image compositing and processing device

Also Published As

Publication number Publication date
GB2365298B (en) 2002-06-26
DE10052481A1 (en) 2002-01-31
GB2365298A (en) 2002-02-13
ITMI20002389A1 (en) 2002-05-06
GB0024469D0 (en) 2000-11-22
DE10052481C2 (en) 2003-06-05
CA2322250A1 (en) 2002-01-19
FR2812159A1 (en) 2002-01-25
FR2812159B1 (en) 2008-09-26
JP2002044486A (en) 2002-02-08

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