ES2159245B1 - Linea de retardo multiple y ajustable para sistemas electronicos. - Google Patents
Linea de retardo multiple y ajustable para sistemas electronicos.Info
- Publication number
- ES2159245B1 ES2159245B1 ES9901787A ES9901787A ES2159245B1 ES 2159245 B1 ES2159245 B1 ES 2159245B1 ES 9901787 A ES9901787 A ES 9901787A ES 9901787 A ES9901787 A ES 9901787A ES 2159245 B1 ES2159245 B1 ES 2159245B1
- Authority
- ES
- Spain
- Prior art keywords
- delay line
- adjustable delay
- memorization
- electronic systems
- electronic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Networks Using Active Elements (AREA)
- Analogue/Digital Conversion (AREA)
- Pulse Circuits (AREA)
Abstract
Línea de retardo múltiple y ajustable para sistemas electrónicos La línea de retardo múltiple y ajustable es un circuito electrónico digital que retarda varias señales eléctricas un intervalo de tiempo variable. Una de sus posibles aplicaciones es para el control TDAS, el cual, utilizando señales retardadas, suprime el régimen caótico de los sistemas dinámicos no autónomos en general, y de los convertidores electrónicos no autónomos DC-DC en particular. Consta de una etapa de conversión AD, una etapa de procesado digital y una etapa de conversión DA. La etapa de procesado digital consta de un subsistema de memorización y uno de control. El subsistema de memorización esta implementado por memorias RAM tipo FIFO, y el de control por un reloj de muestreo, un registro de desplazamiento y una red combinacional.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| ES9901787A ES2159245B1 (es) | 1999-07-23 | 1999-07-23 | Linea de retardo multiple y ajustable para sistemas electronicos. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| ES9901787A ES2159245B1 (es) | 1999-07-23 | 1999-07-23 | Linea de retardo multiple y ajustable para sistemas electronicos. |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| ES2159245A1 ES2159245A1 (es) | 2001-09-16 |
| ES2159245B1 true ES2159245B1 (es) | 2002-04-01 |
Family
ID=8309533
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES9901787A Expired - Fee Related ES2159245B1 (es) | 1999-07-23 | 1999-07-23 | Linea de retardo multiple y ajustable para sistemas electronicos. |
Country Status (1)
| Country | Link |
|---|---|
| ES (1) | ES2159245B1 (es) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1117361A (en) * | 1965-04-05 | 1968-06-19 | Ferranti Ltd | Improvements relating to information storage devices |
| US4105978A (en) * | 1976-08-02 | 1978-08-08 | Honeywell Information Systems Inc. | Stretch and stall clock |
| US4241418A (en) * | 1977-11-23 | 1980-12-23 | Honeywell Information Systems Inc. | Clock system having a dynamically selectable clock period |
| DE3437006A1 (de) * | 1984-10-09 | 1986-04-10 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Anordnung zur variablen verzoegerung von nf-signalen |
| US5870445A (en) * | 1995-12-27 | 1999-02-09 | Raytheon Company | Frequency independent clock synchronizer |
-
1999
- 1999-07-23 ES ES9901787A patent/ES2159245B1/es not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| ES2159245A1 (es) | 2001-09-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EC2A | Search report published |
Date of ref document: 20160120 Kind code of ref document: A1 Effective date: 20160120 |
|
| FD2A | Announcement of lapse in spain |
Effective date: 20191030 |