ES2110948T3 - Contacto de alimentacion de energia a un circuito integrado. - Google Patents

Contacto de alimentacion de energia a un circuito integrado.

Info

Publication number
ES2110948T3
ES2110948T3 ES89309221T ES89309221T ES2110948T3 ES 2110948 T3 ES2110948 T3 ES 2110948T3 ES 89309221 T ES89309221 T ES 89309221T ES 89309221 T ES89309221 T ES 89309221T ES 2110948 T3 ES2110948 T3 ES 2110948T3
Authority
ES
Spain
Prior art keywords
power supply
integrated circuit
substrate
supply contact
epitaxial layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES89309221T
Other languages
English (en)
Inventor
Thaddeus J Gabara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of ES2110948T3 publication Critical patent/ES2110948T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Bipolar Transistors (AREA)

Abstract

UN CIRCUITO INTEGRADO FORMADO EN UN SUSTRATO TIENE TRANSISTORES DE EFECTO DE CAMPO CONFORMADOS EN UNA CAPA EPITAXIAL RELATIVAMENTE IMPURIFICADA (ES DECIR, CON ALTA RESISTIVIDAD), TIPICAMENTE EN UN "TUBO" FORMADO EN LA MISMA. LA CORRIENTE DE FUNCIONAMIENTO PARA LOS TRANSISTORES DE PROPORCIONA AL MENOS EN PARTE A TRAVES DE UNA CAPA METALICA SITUADA EN LA PARTE TRASERA DEL SUSTRATO. SORPRENDENTEMENTE, LA CONDUCTIVIDAD ES SUFICIENTEMENTE ALTA A TRAVES DE LA CAPA EPITAXIAL Y EL SUSTRATO QUE EL NUMERO DE ZONAS DE UNION EN LA PARTE FRONTAL PUEDE REDUCIRSE, O ELIMINARSE COMPLETAMENTE EN ALGUNOS CASOS. ADEMAS SE OBTIENE UNA REDUCCION EN LA INDUCTANCIA DE CONDUCCION DE LA FUENTE DE ALIMENTACION, REDUCIENDO LOS PROBLEMAS DEL SALTO A TIERRA Y DE OSCILACION
ES89309221T 1988-09-20 1989-09-12 Contacto de alimentacion de energia a un circuito integrado. Expired - Lifetime ES2110948T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/246,713 US4947228A (en) 1988-09-20 1988-09-20 Integrated circuit power supply contact

Publications (1)

Publication Number Publication Date
ES2110948T3 true ES2110948T3 (es) 1998-03-01

Family

ID=22931887

Family Applications (1)

Application Number Title Priority Date Filing Date
ES89309221T Expired - Lifetime ES2110948T3 (es) 1988-09-20 1989-09-12 Contacto de alimentacion de energia a un circuito integrado.

Country Status (6)

Country Link
US (1) US4947228A (es)
EP (1) EP0360477B1 (es)
JP (1) JP2738416B2 (es)
DE (1) DE68928483T2 (es)
ES (1) ES2110948T3 (es)
HK (1) HK1002542A1 (es)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5181094A (en) * 1988-09-29 1993-01-19 Mitsubishi Denki Kabushiki Kaisha Complementary semiconductor device having improved device isolating region
US5574633A (en) * 1994-02-23 1996-11-12 At&T Global Information Solubions Company Multi-phase charge sharing method and apparatus
US5985724A (en) * 1996-10-01 1999-11-16 Advanced Micro Devices, Inc. Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer
US5877930A (en) * 1997-03-27 1999-03-02 Digital Equipment Corporation Input and output noise reduction circuit
US5970347A (en) * 1997-07-18 1999-10-19 Advanced Micro Devices, Inc. High performance mosfet transistor fabrication technique
US6794978B2 (en) * 2002-05-15 2004-09-21 John C. Tung Accurate multi-ground inductors for high-speed integrated circuits
US7400047B2 (en) * 2004-12-13 2008-07-15 Agere Systems Inc. Integrated circuit with stacked-die configuration utilizing substrate conduction
US8159809B2 (en) * 2007-12-07 2012-04-17 METAMEMS Corp. Reconfigurable system that exchanges substrates using coulomb forces to optimize a parameter
US8018009B2 (en) * 2007-12-07 2011-09-13 METAMEMS Corp. Forming large planar structures from substrates using edge Coulomb forces
US7812336B2 (en) * 2007-12-07 2010-10-12 METAMEMS Corp. Levitating substrate being charged by a non-volatile device and powered by a charged capacitor or bonding wire
US7965489B2 (en) * 2007-12-07 2011-06-21 METAMEMS Corp. Using coulomb forces to form 3-D reconfigurable antenna structures
US8008070B2 (en) * 2007-12-07 2011-08-30 METAMEMS Corp. Using coulomb forces to study charateristics of fluids and biological samples
US8531848B2 (en) * 2007-12-07 2013-09-10 METAMEMS Corp. Coulomb island and Faraday shield used to create adjustable Coulomb forces
US7728427B2 (en) * 2007-12-07 2010-06-01 Lctank Llc Assembling stacked substrates that can form cylindrical inductors and adjustable transformers
US7946174B2 (en) * 2007-12-07 2011-05-24 METAMEMS Corp. Decelerometer formed by levitating a substrate into equilibrium
US7863651B2 (en) 2007-12-07 2011-01-04 METAMEMS Corp. Using multiple coulomb islands to reduce voltage stress
US20090149038A1 (en) * 2007-12-07 2009-06-11 Metamems Llc Forming edge metallic contacts and using coulomb forces to improve ohmic contact

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57162360A (en) * 1981-03-31 1982-10-06 Nec Corp Complementary insulated gate field effect semiconductor device
JPS58157151A (ja) * 1982-03-15 1983-09-19 Mitsubishi Electric Corp 半導体集積回路装置
EP0117867A4 (en) * 1982-08-26 1985-04-23 Mitsubishi Electric Corp SEMICONDUCTOR ARRANGEMENT.
US4572972A (en) * 1983-01-18 1986-02-25 At&T Laboratories CMOS Logic circuits with all pull-up transistors integrated in separate chip from all pull-down transistors
JPS60152055A (ja) * 1984-01-20 1985-08-10 Matsushita Electric Ind Co Ltd 相補型ｍｏｓ半導体装置
US4631570A (en) * 1984-07-03 1986-12-23 Motorola, Inc. Integrated circuit having buried oxide isolation and low resistivity substrate for power supply interconnection
US4675717A (en) * 1984-10-09 1987-06-23 American Telephone And Telegraph Company, At&T Bell Laboratories Water-scale-integrated assembly
JPS62286268A (ja) * 1986-06-04 1987-12-12 Sharp Corp 半導体集積回路装置

Also Published As

Publication number Publication date
EP0360477A2 (en) 1990-03-28
EP0360477B1 (en) 1997-12-10
EP0360477A3 (en) 1991-11-21
DE68928483T2 (de) 1998-04-02
US4947228A (en) 1990-08-07
DE68928483D1 (de) 1998-01-22
HK1002542A1 (en) 1998-08-28
JPH02114661A (ja) 1990-04-26
JP2738416B2 (ja) 1998-04-08

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