ES2110354A1 - Circuito de diezmado y procedimiento para el filtraje de señales cuantificadas, proporcionando al mismo tiempo una magnitud substancialmente uniforme y una respuesta de fase substancialmente lineal. - Google Patents

Circuito de diezmado y procedimiento para el filtraje de señales cuantificadas, proporcionando al mismo tiempo una magnitud substancialmente uniforme y una respuesta de fase substancialmente lineal.

Info

Publication number
ES2110354A1
ES2110354A1 ES09500540A ES9500540A ES2110354A1 ES 2110354 A1 ES2110354 A1 ES 2110354A1 ES 09500540 A ES09500540 A ES 09500540A ES 9500540 A ES9500540 A ES 9500540A ES 2110354 A1 ES2110354 A1 ES 2110354A1
Authority
ES
Spain
Prior art keywords
decimation
magnitude
linear phase
phase response
substantially uniform
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES09500540A
Other languages
English (en)
Other versions
ES2110354B1 (es
Inventor
Daniel Arthur Staver
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of ES2110354A1 publication Critical patent/ES2110354A1/es
Application granted granted Critical
Publication of ES2110354B1 publication Critical patent/ES2110354B1/es
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0283—Filters characterised by the filter structure
    • H03H17/0286—Combinations of filter structures
    • H03H17/0288—Recursive, non-recursive, ladder, lattice structures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/04—Recursive filters
    • H03H17/0416—Recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
    • H03H17/0427—Recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
    • H03H17/0438—Recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer
    • H03H17/045—Recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Networks Using Active Elements (AREA)

Abstract

CIRCUITO DE DIEZMADO Y PROCEDIMIENTO PARA EL FILTRAJE DE SEÑALES CUANTIFICADAS, PROPORCIONANDO AL MISMO TIEMPO UNA MAGNITUD SUBSTANCIALMENTE UNIFORME Y UNA RESPUESTA DE FASE SUBSTANCIALMENTE LINEAL. CIRCUITO DE DIEZMADO PARA FILTRADO DE UN FLUJO DE SEÑALES ELECTRICAS CUANTIFICADAS, PROPORCIONANDO UNA MAGNITUD UNIFORME Y RESPUESTA DE FASE LINEAL SOBRE GAMA DE BANDA DE PASO FB. EL FLUJO DE SEÑALES ELECTRICAS LLEGA A UN REGIMEN FN PREDETERMINADO DESDE UN MODULADOR DELTA-SIGMA DE SOBREMUESTREO. EL CIRCUITO COMPRENDE UN FILTRO DE DIEZMADO PARA FILTRAR EL FLUJO DE SEÑALES ELECTRICAS, PARA PROPORCIONAR UNA SEÑAL DE SALIDA FILTRADA A UN REGIMEN DE SALIDA F''S. EL FILTRO TIENE UNA RESPUESTA EN FRECUENCIA: FORMULA DONDE K, T Y R SE EXPLICAN DETALLADAMENTE EN LA DESCRIPCION. EXISTE UN CORRECTOR DE MAGNITUD PARA CORREGIR LA MAGNITUD DE LA SEÑAL DE SALIDA FILTRADA. LA TASA DE DIEZMADO SE SELECCIONA DE FORMA QUE EL REGIMEN DE SALIDA F''S ESTE SUFICIENTEMENTE POR ENCIMA DE LA GAMA DE LA BANDA DE PASO FB, PARA QUE EL CORRECTOR DE MAGNITUD PROPORCIONE UNA MAGNITUD UNIFORME Y RESPUESTA DE FASE LINEAL EN LA GAMA DE BANDA DE PASO FB.
ES09500540A 1994-04-05 1995-03-16 Circuito de diezmado y procedimiento para el filtraje de señales cuantificadas, proporcionando al mismo tiempo una magnitud substancialmente uniforme y una respuesta de fase substancialmente lineal. Expired - Fee Related ES2110354B1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/223,196 US5410498A (en) 1994-04-05 1994-04-05 Decimation circuit and method for filtering quantized signals while providing a substantially uniform magnitude and a substantially linear phase response

Publications (2)

Publication Number Publication Date
ES2110354A1 true ES2110354A1 (es) 1998-02-01
ES2110354B1 ES2110354B1 (es) 1998-08-01

Family

ID=22835479

Family Applications (1)

Application Number Title Priority Date Filing Date
ES09500540A Expired - Fee Related ES2110354B1 (es) 1994-04-05 1995-03-16 Circuito de diezmado y procedimiento para el filtraje de señales cuantificadas, proporcionando al mismo tiempo una magnitud substancialmente uniforme y una respuesta de fase substancialmente lineal.

Country Status (5)

Country Link
US (1) US5410498A (es)
KR (1) KR100360631B1 (es)
DE (1) DE19510655B4 (es)
ES (1) ES2110354B1 (es)
TW (1) TW255996B (es)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5650951A (en) * 1995-06-02 1997-07-22 General Electric Compay Programmable data acquisition system with a microprocessor for correcting magnitude and phase of quantized signals while providing a substantially linear phase response
EP0935851B1 (en) * 1997-08-12 2004-10-06 Koninklijke Philips Electronics N.V. A digital communication device and a mixer
US6041339A (en) * 1998-03-27 2000-03-21 Ess Technology, Inc. Efficient decimation filtering
US7602940B2 (en) 1998-04-16 2009-10-13 Digimarc Corporation Steganographic data hiding using a device clock
US6816100B1 (en) 1999-03-12 2004-11-09 The Regents Of The University Of California Analog-to-digital converters with common-mode rejection dynamic element matching, including as used in delta-sigma modulators
US6470365B1 (en) * 1999-08-23 2002-10-22 Motorola, Inc. Method and architecture for complex datapath decimation and channel filtering
KR100799406B1 (ko) 2004-06-22 2008-01-30 삼성탈레스 주식회사 대역 내 신호의 감쇠를 보상하기 위한 디지털 샘플링레이트 변환기
KR101949580B1 (ko) 2017-03-02 2019-02-18 서울대학교산학협력단 주파수 특성을 보정하는 아날로그 디지털 변환기 및 이를 포함하는 반도체 장치
US10862505B1 (en) 2020-02-27 2020-12-08 Nxp Usa, Inc. Arbitrary rate decimator and timing error corrector for an FSK receiver

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4783660A (en) * 1986-09-29 1988-11-08 Signatron, Inc. Signal source distortion compensator
US4833474A (en) * 1986-08-25 1989-05-23 Hitachi Ltd. A/D converter
US4951052A (en) * 1989-07-10 1990-08-21 General Electric Company Correction of systematic error in an oversampled analog-to-digital converter
US5181033A (en) * 1992-03-02 1993-01-19 General Electric Company Digital filter for filtering and decimating delta sigma modulator output signals
WO1993007679A1 (en) * 1991-10-07 1993-04-15 Elbit-Ati, Ltd. Nmr receiver with sigma-delta a/d converter

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4896156A (en) * 1988-10-03 1990-01-23 General Electric Company Switched-capacitance coupling networks for differential-input amplifiers, not requiring balanced input signals
US5349676A (en) * 1991-02-11 1994-09-20 General Electric Company Data acquisition systems with programmable bit-serial digital signal processors
US5126961A (en) * 1991-03-06 1992-06-30 General Electric Company Plural-channel decimation filter, as for sigma-delta analog-to-digital converters
DE69118372T2 (de) * 1991-07-17 1996-11-14 Ibm Dezimationsfilter für Sigma Delta Konverter und Datenendeinrichtung mit einem solchen Filter
JP3089104B2 (ja) * 1992-06-19 2000-09-18 株式会社日立製作所 移動平均フィルタ、及びこれを用いたａ／ｄ変換器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4833474A (en) * 1986-08-25 1989-05-23 Hitachi Ltd. A/D converter
US4783660A (en) * 1986-09-29 1988-11-08 Signatron, Inc. Signal source distortion compensator
US4951052A (en) * 1989-07-10 1990-08-21 General Electric Company Correction of systematic error in an oversampled analog-to-digital converter
WO1993007679A1 (en) * 1991-10-07 1993-04-15 Elbit-Ati, Ltd. Nmr receiver with sigma-delta a/d converter
US5181033A (en) * 1992-03-02 1993-01-19 General Electric Company Digital filter for filtering and decimating delta sigma modulator output signals

Also Published As

Publication number Publication date
KR100360631B1 (ko) 2003-01-24
ES2110354B1 (es) 1998-08-01
DE19510655A1 (de) 1995-10-12
DE19510655B4 (de) 2006-04-27
KR950035063A (ko) 1995-12-30
TW255996B (en) 1995-09-01
US5410498A (en) 1995-04-25

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