ES2046106A2 - Metodo de realizacion de circuitos alineadores inmunes a los deslizamientos ocurridos en la memoria elastica de recepcion. - Google Patents
Metodo de realizacion de circuitos alineadores inmunes a los deslizamientos ocurridos en la memoria elastica de recepcion.Info
- Publication number
- ES2046106A2 ES2046106A2 ES9200352A ES9200352A ES2046106A2 ES 2046106 A2 ES2046106 A2 ES 2046106A2 ES 9200352 A ES9200352 A ES 9200352A ES 9200352 A ES9200352 A ES 9200352A ES 2046106 A2 ES2046106 A2 ES 2046106A2
- Authority
- ES
- Spain
- Prior art keywords
- frame
- alignment
- stage
- immune
- per
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
METODO DE REALIZACION DE CIRCUITOS ALINEADORES INMUNES A LOS DESLIZAMIENTOS OCURRIDOS EN LA MEMORIA ELASTICA DE RECEPCION. APLICABLE A SISTEMAS DIGITALES DE TRANSMISION DE DATOS. BASADO EN GENERAR SEÑALES DE CONTROL EN LA MEMORIA ELASTICA (1) QUE INDIQUEN CUANDO SE REPITE O SE PIERDE INFORMACION, HACIENDO POSIBLE EL CONTROL DE CIRCUITOS ALINEADORES DE MANERA QUE UN DESLIZAMIENTO EN LA MEMORIA ELASTICA (1), DEBIDO A DIFERENCIAS DE FRECUENCIA ENTRE EL RELOJ DE RECEPCION Y DEL SISTEMA DE EMISION, NO IMPLIQUE FORZOSAMENTE EL DESALINEAMIENTO CUANDO SE ALCANZA EL ESTADO DE ALINEAMIENTO. PARA ELLO SE HA PREVISTO UNA ETAPA DE GENERACION DE SEÑALES TRAMA CONSTITUIDA POR LA MEMORIA ELASTICA (1), UN CONTADOR DE LECTURA (2), UN CONTADOR DE ESCRITURA (3), UN BLOQUE COMPARADOR Y DE CONTROL (4) QUE GENERA DICHAS SEÑALES TRAMA, Y UN CIRCUITO PIPO (5); CONECTANDOSE A ESA ETAPA UN CIRCUITO ALINEADOR DE MULTITRAMA DE SEÑALIZACION ASOCIADA AL CANAL PARA UNA TRAMA G.704 A 2.048 KBIT/S O UN CIRCUITO ALINEADOR SEGUN LA RECOMENDACION X.50 PARA LOS INTERVALOS DE CANAL A 64 KBIT/S CONTENIDOS EN UNA TRAMA G.704 A 2.048 KBIT/S, TODO ELLO DISEÑADO SEGUN EL METODO DE LA INVENCION.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ES9200352A ES2046106B1 (es) | 1992-02-18 | 1992-02-18 | Metodo de realizacion de circuitos alineadores inmunes a los deslizamientos ocurridos en la memoria elastica de recepcion. |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ES9200352A ES2046106B1 (es) | 1992-02-18 | 1992-02-18 | Metodo de realizacion de circuitos alineadores inmunes a los deslizamientos ocurridos en la memoria elastica de recepcion. |
Publications (3)
Publication Number | Publication Date |
---|---|
ES2046106A2 true ES2046106A2 (es) | 1994-01-16 |
ES2046106R ES2046106R (es) | 1996-04-16 |
ES2046106B1 ES2046106B1 (es) | 1996-11-16 |
Family
ID=8276106
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES9200352A Expired - Fee Related ES2046106B1 (es) | 1992-02-18 | 1992-02-18 | Metodo de realizacion de circuitos alineadores inmunes a los deslizamientos ocurridos en la memoria elastica de recepcion. |
Country Status (1)
Country | Link |
---|---|
ES (1) | ES2046106B1 (es) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4327411A (en) * | 1980-03-04 | 1982-04-27 | Bell Telephone Laboratories, Incorporated | High capacity elastic store having continuously variable delay |
US4368531A (en) * | 1979-08-10 | 1983-01-11 | The Plessey Company Limited | Frame aligner for digital telecommunications exchange system |
EP0435130A1 (fr) * | 1989-12-27 | 1991-07-03 | Alcatel Cit | Dispositif d'insertion d'éléments binaires d'information dans une structure de trame déterminée |
EP0459686A2 (en) * | 1990-05-30 | 1991-12-04 | AT&T Corp. | Digital signal synchronization employing single elastic store |
-
1992
- 1992-02-18 ES ES9200352A patent/ES2046106B1/es not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4368531A (en) * | 1979-08-10 | 1983-01-11 | The Plessey Company Limited | Frame aligner for digital telecommunications exchange system |
US4327411A (en) * | 1980-03-04 | 1982-04-27 | Bell Telephone Laboratories, Incorporated | High capacity elastic store having continuously variable delay |
EP0435130A1 (fr) * | 1989-12-27 | 1991-07-03 | Alcatel Cit | Dispositif d'insertion d'éléments binaires d'information dans une structure de trame déterminée |
EP0459686A2 (en) * | 1990-05-30 | 1991-12-04 | AT&T Corp. | Digital signal synchronization employing single elastic store |
Also Published As
Publication number | Publication date |
---|---|
ES2046106R (es) | 1996-04-16 |
ES2046106B1 (es) | 1996-11-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EC2A | Search report published |
Date of ref document: 19920218 Kind code of ref document: B1 Effective date: 19920218 |
|
FD1A | Patent lapsed |
Effective date: 20041004 |