EP4736080A2 - Adjusting tunnel junction characteristics of atomic layer deposition films through underlayer modification - Google Patents

Abstract

A system and method for tuning a high-resistivity layer of TaN deposited by atomic layer deposition (ALD) over a superconducting metal underlayer that has undergone one of a set of treatments. The underlayer can be chosen or modified in such a way to yield an ALD TaN thin film with predictably high- or low-resistivity. A low-resistivity layer of ALD TaN is deposited on exposed metal layers, whether they are superconducting metals or non-superconducting metals, while a high-resistivity layer of ALD TaN is deposited on exposed dielectrics, as well as modified surfaces of exposed metals. This modification may be achieved through the use of a physical vapor deposited (PVD) metal nitride intervening layer, such as PVD TaN and PVD NbN, deposited between the high-resistivity layer and the metal layer.

Description

ADJUSTING TUNNEL JUNCTION CHARACTERISTICS OF ATOMIC LAYER DEPOSITION FILMS THROUGH UNDERLAYER MODIFICATION

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of US Provisional Patent Application Nos. 63/523,410, filed on June 27, 2023, and 63/640,576, filed on April 30, 2024, the entireties of which are hereby incorporated herein by this reference.

BACKGROUND OF THE INVENTION

[0002] 1 . Field of the Invention

[0003] The present invention generally relates to atomic layer deposition of films on engineered surfaces or on multiple surfaces with specific characteristics. More particularly, the present invention relates to a system and method for tuning a high- resistivity layer of TaN deposited by atomic layer deposition (ALD) over a superconducting metal layer that has undergone one of a set of treatments.

[0004] 2. Description of the Related Art

[0005] Insulator-based tunnel junctions (either metal-insulator-metal or superconductor-insulator-superconductor) are fundamental components for sensing and information processing devices, including magnetic tunnel junctions for spintronics and fast-access nonvolatile magnetic memory, Josephson Junctions for particle detectors, magnetic field sensors, and superconducting qubits for quantum computation. Josephson junctions consist of two superconductors coupled by a weak link. The weak link can be a thin insulating barrier (known as a superconductor- insulator-superconductor junction, or S-l-S), a short section of non-superconducting metal (S-N-S), or a physical constriction that weakens the superconductivity at the point of contact (S-c-S). A current, known as a supercurrent, can flow continuously across the junction without any voltage applied, so long as it is less than a certain value (known as the critical current of the junction). Josephson Junctions have important applications in quantum-mechanical circuits, such as SQUIDs, superconducting qubits, and single-flux-quantum (SFQ) digital logic families (Rapid Single Flux Quantum (RSFQ), Adiabatic Quantum Flux Parametron (AQFP), Reciprocal Quantum Logic (RQL), and others).

[0006] The performance of S-l-S tunnel junctions depends critically on the quality of the insulating tunnel barrier-a uniform, pinhole-free film of nanometer-scale thickness is desired. The performance of S-l-S junctions also depends on the quality of the various interfaces that the supercurrent has to traverse - such as the interface that the tunnel barrier has with superconductors on each side. Native oxides (of variable characteristics) naturally form on the surface of most metals when exposed to air, which represents a challenge for the controlled fabrication of S-l-S tunnel junctions, and affects their performance, when used in superconducting quantum computing, in particular.

[0007] For example, in Nb/AI/AIOx/AI/Nb and Nb/AI/AIOx/Nb Josephson Junctions, an ultrathin (< approximately 1 nm) tunnel barrier of AIOx is required since the critical current (/_c) through the Josephson Junction exponentially decays with the barrier thickness. Room temperature oxidation has been an industry standard to produce AIOx tunnel barriers for Josephson Junctions through in situ oxygen reaction of an Al layer in a controlled, pure oxygen environment. However, such tunnel barriers formed by room temperature oxidation are prone to ‘aging’ (when the tunnel barrier is exposed to atmospheric oxygen at room temperature) and to change when subjected to increased temperatures during downstream processing of the Josephson junction. Despite successful commercial applications of these extant Josephson Junctions in devices such as superconducting quantum interference devices and voltage standards, new tunnel barriers and new methods of forming them continue to be of interest to avoid the problems of aging and poor thermal stability.

[0008] Atomic-layer deposition (ALD) is an alternative for the synthesis of atomically thin tunnel barriers for high-performance S-l-S tunnel junctions. ALD is a chemical vapor process that utilizes self-limited surface reactions to grow films one atomic layer at a time. For example, one method of creating better S-l-S junctions through the use of an ALD tunnel barrier has been depositing AI2O3 with a series of alternating precursor pulses of H2O and trimethylaluminum which react at the substrate surface. This process results in a fully oxidized and uniform AI2O3 film with atomic-scale thickness control. However, despite this limited success, control of the interface on which ALD is conducted remains challenging.

[0009] The tunnel barrier and subsequent electrode deposition during formation of an S-l-S tunnel-junction are ideally carried out in situ without breaking vacuum (to avoid degradation of critical interfaces by contaminants or native oxide formation). ALD nucleation is dependent on the atomic-level surface characteristics - for example, on inert metal surfaces, such as Pt and Au, it can be completely frustrated for the first 30- 50 cycles of alternating ALD precursor pulses.

[0010] Other researchers have attempted to replace room temperature oxidation of Al with tunnel barrier formation with ALD, but these have been handicapped by lack of cluster tools with ALD chambers integrated with other deposition chambers. Nb/AI/AhOs/Nb Josephson Junctions reported in the literature that use in situ ALD of AI2O3 had an interlayer (IL) >0.5 nm in thickness most likely due to poor vacuum pressure (approximately 500 mTorr) during sample transfer and pre-ALD sample heating. This IL prevented the realization of truly atomically thin tunnel barriers and led to poor-quality Josephson Junctions. Extant ALD methods have been especially problematic in depositing ALD TaN of high resistivity on superconducting metals. The inventors have demonstrated that the characteristics of the ALD TaN film are highly dependent on the underlying material, for example: an ALD process that results in a higher N:Ta ratio film (with higher resistivity) when deposited on oxide, but results in a film with lower N:Ta ratio when deposited on clean metal surfaces. Accordingly, it is to the problem of depositing a uniform, high-resistivity TaN film on superconducting materials that one aspect of the present invention is directed.

[0011] Additionally, a second aspect of the present invention relates to the use of etch stop layers when forming metallic interconnects for standard CMOS applications. These interconnects are formed by etching trenches and via connections into a stack of materials consisting of a layer of insulating material (typically a silicon oxide, SiCOH, or other low-dielectric-constant and inter-layer dielectric (ILD) materials) above a distinct etch stop layer (typically a 20-30 nm layer of Si N , SiCN, etc.). When trenches are formed in the ILD by reactive ion etch, the process is designed to stop or slow down on the etch stop layer. In such cases, the etch stop layer will be removed by a specifically designed process wherever it is exposed by the prior reactive ion etch.

[0012] The trenches formed in the ILD are then lined with a metal diffusion barrier and overfilled with a conducting metal (typically Cu, W, Ru, or other conductive metals used in microelectronic applications), and the excess overburden is polished away through the use of chemical-mechanical planarization (CMP). This process is known as a damascene process, and is repeated sequentially to form a multilayer interconnect structure. [0013] Since the etch stop layer is retained in the dielectric stack between the metal lines, both the thickness and the dielectric constant of this etch stop layer will have a resulting effect on the effective dielectric constant. The effective dielectric constant affects the speed of signals propagating through the interconnect, and hence should be minimized in order to optimize chip performance.

[0014] Accordingly, it is also to the problem of depositing a uniform TaN film of variable resistivity on a series of exposed surfaces (including dielectric and metallic films) that one aspect of the present invention is directed.

BRIEF SUMMARY OF THE INVENTION

[0015] Briefly described, one aspect of the present invention allows the tuning of the tunnel junction characteristics of an atomic layer deposition (ALD) tunnel barrier deposited on various substrate materials, particularly with reference to ALD tunnel barrier resistivity. The tuning can be accomplished through modification of the surface of the underlying superconducting material, such as Ta, Nb, or Al. The surface of the superconducting metal layer can be pretreated prior to deposition of the high-resistivity layer, such as with plasma nitridation with N2, NH3, or any similar nitrogen containing species, ammonia exposure at suitably high temperature, or light oxidation. Alternately, an intervening layer can also be deposited over the superconducting metal layer prior to the formation of the high-resistivity ALD layer. A high-resistivity layer of TaN is deposited via ALD as an atomically thin film having a thickness in a range up to 10 nm.

[0016] In one embodiment, the invention creates a quantum device that includes a substrate having a region of superconducting metal that has been modified by oxidation or nitridation, with a high-resistivity layer of TaN deposited over the modified surface of the superconducting metal layer. The TaN layer is an atomically thin film having a thickness preferably in the range of about 10 nm. The superconducting metal layer can be Ta, Nb, or Al.

[0017] In one embodiment, the quantum device can include an intervening metal nitride layer deposited between the high-resistivity ALD layer and the region of superconducting material, such as a layer of insulating physical vapor deposited (PVD) TaN or PVD NbN.

[0018] In another embodiment, the invention can include a method of manufacturing a quantum device (such as a S-l-S Josephson junction, or any quantum-mechanical circuit that utilizes these junctions, such as SQUIDs, superconducting qubits, and SFQ digital logic families, as described above) by integrating any of the above methods to achieve a high-resistance junction that is suitable for such applications.

[0019] Briefly described, a second aspect of the present invention is the use of an ultra-thin ALD TaN etch stop layer that does not degrade the effective dielectric constant between metal lines used to interconnect underlying transistors. This invention utilizes the deposition of an ALD etch stop layer with variable film properties dependent on the exposed substrate materials, particularly with reference to the etch stop layer resistivity. A high resistivity layer of TaN is formed via ALD on exposed dielectric surfaces (for example: silicon oxide, SiCOH, or other low-k and inter-layer dielectric (ILD) materials), whereas a low resistivity layer of TaN is simultaneously formed on exposed metal surfaces (for example: Cu, W, Ru, or other conductive metals used in microelectronic applications). This eliminates the need for an etch stop layer removal step after trenches are formed in the ILD. Therefore, this ALD layer functions as a high-resistivity etch stop layer for subsequent single or dual damascene etch processes, while maintaining a low resistance contact to the underlying metal pattern due to the surface-dependent nature of the ALD layer resistivity.

[0020] An embodiment of this aspect of the invention includes a substrate having a region of exposed metal that has been sufficiently cleaned to create a pure metal surface, free of naturally or artificially formed surface oxides (as in the case of CMP), onto which an ALD TaN layer with variable resistivity is deposited. The cleaning can be accomplished through in-situ processes, such as sputter cleaning with an inert plasma or surface oxide reduction with a reactive plasma. The underlying metal pattern can be Cu, W, Ru, or any interconnect metal commonly used in standard CMOS device fabrication.

[0021] This aspect of the invention can include a method which can be implemented into the formation of a semiconductor device by integrating the above method to selectively form an ALD layer with surface-dependent resistivity dependent on the underlying material to create an etch stop layer, while maintaining a low-resistivity layer atop the underlying metal lines. In such an embodiment, the method can be repeated throughout the fabrication of such devices, as in the case of back-end-of-line interconnect formation in CMOS logic processes. [0022] Additionally, another aspect of the present invention relates to a system and method of depositing a tuned ALD T aN layer on a surface where dielectrics and metals are exposed at different areas in order to achieve desired ALD TaN properties on each area.

[0023] The present invention therefore provides an advantage in fabrication of both quantum devices and semiconductor devices by enabling the use of novel atomic layer deposition processes, which provide improved film thickness and composition control. In the case of the formation of quantum devices, such as those including S-l-S Josephson junctions, the present invention allows the creation of high-resistance junctions with a tunnel barrier of high-resistivity, even when deposited on superconducting metals, such as Nb, Ta, or Al. The use of a tunnel barrier with a lower energy barrier height, such as TaN, allows for higher barrier transparency at higher thicknesses, versus the 1 -2 nm thicknesses necessary for, say, aluminum oxide tunnel barriers. This decreases sensitivity to thickness when ALD TaN barriers are used as described in the present invention. This, in turn, improves the scalability and consistency of such devices, which makes the invention of interest to the quantum device industry.

[0024] The present invention is further industrially applicable in the CMOS industry in that it allows for the formation of self-aligned metallic interconnects for semiconductor devices, such as CMOS logic devices and memory devices, through the use of an etch-stop layer with a variable, surface-dependent resistivity. This unique film control enables self-aligned metallic contact formation, as well as a more streamlined and multi-functional etch stop layer integration when compared to existing etch-stop methods. These and other advantages of the present invention will be apparent to one of skill in the art after review of the present specification, drawings, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Fig. 1 A is a cross-sectional view of one embodiment of the present invention, utilizing a selective metal treatment to form an ALD thin film of different resistivity at different portions of the surface.

[0026] Fig. 1 B is a cross-sectional view of another embodiment of the present invention, utilizing the underlayer-dependent deposition process to form an ALD thin film of variable resistivity. [0027] Fig. 1 C is a cross-sectional view of another embodiment of the present invention, utilizing a modifying underlayer to form a conformal ALD thin film of high- resistivity.

[0028] Fig. 2A is a cross-sectional view of one embodiment of a Josephson junction, with a modifying underlayer between the ALD barrier and the superconducting metal. [0029] Fig. 2B is a cross-sectional view of one embodiment of a coplanar waveguide resonator, with a modifying underlayer between the ALD capping layer and both the superconducting metal and the underlying substrate.

[0030] Fig. 2C is a cross-sectional view of another embodiment of a coplanar waveguide resonator, with a modifying underlayer between the ALD capping layer and both the superconducting metal and the underlying substrate.

[0031] Fig. 3A is a cross-sectional view of one embodiment of a CMOS device using an etch-stop layer with variable resistivity to form self-aligned metallic interconnects above a field-effect transistor.

[0032] Fig. 3B is a cross-sectional view of a further embodiment of a CMOS device using an etch-stop layer with variable resistivity to form self-aligned metallic interconnects within a multi-layer metallization scheme.

DETAILED DESCRIPTION OF THE INVENTION

[0033] With reference to the figures in which like numerals represent like elements throughout the various views, Fig.1 A is a cross-sectional view of a substrate with an ALD film of varying resistivity (low-resistivity film 12 and high-resistivity film 14) deposited on a superconducting metal layer 10. In the embodiment of Fig. 1A, the superconducting metal 10 may be selectively pre-treated, such as with nitridation or oxidation, or an intervening metal nitride layer deposited (surface layer 16) before the ALD thin film is deposited. As a result of this surface modification, a low-resistivity ALD film 12 and a high-resistivity ALD film 14 are simultaneously deposited on superconducting metal 10 and surface layer 16, respectively. The low-resistivity layer 12 and high-resistivity layer 14 are an atomically thin film having a thickness (A) preferably within a range up to 10 nm. The low-resistivity layer 12 and high-resistivity layer 14 may be TaN. The superconducting metal layer 10 may be Ta and/or Nb.

[0034] With reference to Figs. 1 B-1 C, when so embodied, the surface of the metal layer 20 may also be covered by a dielectric thin film 22 (sacrificial or otherwise) that is intentionally opened at select locations to expose the underlying metal layer. Fig. 1 B is a cross-sectional view of one embodiment of the present invention, wherein the underlayer-dependent deposition process is utilized to form an ALD thin film of variable resistivity. In this embodiment, the surface of the metal layer 20 is left intentionally untreated, such that an atomically thin film of variable resistivity (high-resistivity layer 24 and low-resistivity layer 26) is deposited upon the dielectric thin film 22 and the surface of metal layer 20, respectively.

[0035] Fig. 1 C is a cross-sectional view of another embodiment of the present invention, wherein the surface of metal layer 20 is selectively modified (surface layer 28) prior to deposition of the ALD thin film. This surface modification may be accomplished through nitridation or oxidation of the exposed metal layer 20, or through the deposition of a metal nitride intervening layer, such as TaN, NbN, or a combination thereof. Following this surface modification, a conformal ALD thin film 24 of high- resistivity is deposited on both the dielectric layer 22 and modified surface layer 28.

[0036] With further reference to Figs. 2A-2C, the present invention may be integrated into the formation of quantum devices, such as Josephson junctions, coplanar waveguide resonators, and other structures utilized to form such quantum devices. The embodiments in Figs. 2A-2C leverage the knowledge that an ALD film of high resistivity is formed on both dielectrics and modified metal surface layers. Fig. 2A is a cross-sectional view of one embodiment of a Josephson junction, with a modifying surface layer 32 between the high resistivity ALD tunnel barrier 34 and the underlying superconducting metal layer 30. In this embodiment, the surface of the superconducting metal layer 30 is covered by a sacrificial dielectric thin film that is intentionally opened at select locations to expose the underlying superconducting metal layer. The surface of metal layer 30 is then selectively modified (surface layer 32). This surface modification may be accomplished through nitridation or oxidation of the exposed metal layer 30, or through the deposition of a metal nitride intervening layer, such as TaN, NbN, ora combination thereof. Following this surface modification, a conformal ALD thin film 36 of high-resistivity is deposited on both the sacrificial dielectric layer and modified surface layer 32. Following deposition of the high- resistivity ALD tunnel barrier, a superconducting metal layer 36 is deposited, thus forming a Josephson junction comprised of two superconducting metal layers 30 and 36 and a high-resistivity ALD tunnel barrier 34. The device may be subsequently processed by chemical mechanical planarization (CMP), reactive ion etch (RIE), or other methods known in the art to form patterns in superconducting metal layer 36, after which the sacrificial dielectric film may be removed.

[0037] Fig. 2B is a cross-sectional view of one embodiment of the present invention in a coplanar waveguide resonator, with a modifying underlayer 46,48 between the high-resistivity ALD capping layer 50 and both the superconducting metal layer 42,44 and the underlying substrate 40. In this embodiment, a superconducting metal resonator 44 and superconducting metal ground plane 42 are formed through subtractive metal etch, as is known in the prior art. The surface of both superconducting metal patterns 42,44, as well as the exposed surfaces of the semiconducting substrate 40, are then selectively modified (surface layers 46,48). This surface modification may be accomplished through nitridation or oxidation of the exposed metal layers 42,44, or through the deposition of a metal nitride intervening layer, such as TaN, NbN, ora combination thereof. Following this surface modification, a conformal ALD thin film 50 of high-resistivity is deposited on the modified surface 48 of both the superconducting metal patterns 42,44 as well as the modified surface 46 of the semiconducting substrate 40. This embodiment ensures protective encapsulation of the superconducting resonator structure 44 without risk of electrical shorting to the superconducting ground plane 42, due to the high-resistivity of the ALD thin film 50.

[0038] Fig. 2C is a cross-sectional view of another embodiment of the present invention in a coplanar waveguide resonator, with a modifying underlayer 46,48 between the high-resistivity ALD capping layer 50 and both the superconducting metal layers 42,44 and the underlying substrate 40. In this embodiment, a superconducting metal resonator 44 and superconducting metal ground plane 42 are formed through a damascene patterning approach, as is known in the prior art. The surface of both superconducting metal patterns 42,44, as well as the exposed surfaces of the semiconducting substrate 40, are then selectively modified (surface layers 46,48). This surface modification may be accomplished through nitridation or oxidation of the exposed metal layers 42,44, or through the deposition of a metal nitride intervening layer, such as TaN, NbN, ora combination thereof. Following this surface modification, a conformal ALD thin film 50 of high-resistivity is deposited on the modified surface 48 of both the superconducting metal patterns 42,44 as well as the modified surface 46 of the semiconducting substrate 40. As in the case of Fig. 2B, this embodiment ensures protective encapsulation of the superconducting resonator structure 44 without risk of electrical shorting to the superconducting ground plane 42, due to the high-resistivity of the ALD thin film 50.

[0039] In one embodiment, the invention can also include a method of manufacturing a quantum device on a substrate by forming a layer of superconducting metal 30,42,44 on the substrate, modifying the surface 32,46,48 of the superconducting metal, and depositing a layer of ALD TaN (high-resistivity film 34,50) on the modified superconducting metal layer 32,46,48 such that the TaN layer is an atomically thin film having a thickness in a range up to 10 nm (thickness A). The surface modification of superconducting layers 30,42,44 can include depositing a metal nitride intervening layer 32,46,48 between the high-resistivity ALD layer 34,50 and the surface of superconducting material 30,42,44. The metal nitride intervening layer 32,46,48 can be created by depositing high-resistivity physical vapor deposited (PVD) TaN or NbN. The method can alternately include the selective formation of a treated surface 32,46,48 of the superconducting layers 30,42,44, through the use of nitridation or oxidation, modifying the surface at various locations over the superconducting metal layer 30,42,44 to form a high-resistivity ALD film 34,50.

[0040] As shown in Figs. 2A-2C, the fabricated device of the present invention can be a quantum device, such as a Josephson Junction, including any devices that utilize these junctions, such as superconducting qubits and SFQ circuits, or any control structures, such as coplanar waveguide resonators, utilized in the fabrication of such circuitry. The present invention is particularly advantageous in that tuning of high- resistivity ALD thin films allows for better control characteristics and thermal stability of thin films utilized in the fabrication of such devices compared with room temperature oxidation (in the case of tunnel barrier formation), which then enables scalable, high quality fabrication of such quantum devices.

[0041] With further reference to Figs. 3A-3B, the present invention may be integrated into the formation of CMOS devices, such as transistors, memory architectures, back- end-of-line metallization, and other structures utilized to form such CMOS devices. The embodiments in Fig. 3A-3B leverage the knowledge that ALD thin films are formed with different resistivity on oxides compared to metals to form a self-aligned etch-stop layer with variable resistivity, leading to effectively lower k dielectric stacks with low- resistivity contact between subsequent metallization levels. Fig. 3A is a cross-sectional view of an embodiment of the present invention in a CMOS device 70, utilizing an etchstop layer of variable resistivity to form self-aligned metallic interconnects. In this embodiment, a field-effect transistor (FET) is formed through a series of processes as are known in the art, including ion implantation of a highly doped source and drain 78, formation of a gate oxide 82 and gate 80, sidewall spacers 84, and other such structures relevant to proper transistor device function. Although a planar FET is depicted in the figure, this embodiment may be further integrated to advanced FET architectures, including three-dimensional FETs such as FinFETs, gate-all-around (GAA) FETs, complementary FETs (CFETs), and the like. Following transistor fabrication, an inter-layer dielectric (ILD) film 76 is deposited, and an assortment of middle-of-line (MOL) metal contacts are formed to the source/drain 78 and gate 80 by etching trenches in the ILD 76, depositing a thin barrier/liner material, filling the trench with a metallic material, and planarizing the structure with CMP, a process which is again known in the art. Following formation of the MOL contacts, an atomically thin film of variable resistivity (high-resistivity layer 86 and low-resistivity layer 72) is deposited simultaneously upon the ILD film 76 and the surface of the metallic MOL contacts 74, respectively. This film will function as an etch-stop layer for further metallic interconnects 92, which are formed in a similar fashion to the underlying contacts as described above, without the need for removal of the etch-stop layer prior to barrier/liner deposition (due to the low-resistivity nature of the thin film when present on the surface of metallic materials).

[0042] Fig. 3B is a cross-sectional view of a further embodiment of the present invention in a CMOS device using an etch-stop layer to form self-aligned back-end metallic interconnects. A substrate 102, such as a low-k silicon oxide, is processed to form a plurality of back-end-of-line (BEOL) metallic interconnects 104,106, a process which is well known in the art and has been described above. Following formation of these interconnects, an atomically thin film of variable resistivity (high-resistivity layer 110 and low-resistivity layer 108) is deposited simultaneously upon the low-k dielectric film 102 and the surface of the metallic BEOL interconnects 106,108, respectively. This thin film will function as an etch-stop layer for subsequent metallization processes. A subsequent inter-layer dielectric 112 is deposited and trenches are etched such that another plurality of BEOL metal interconnects may be formed in the trenches. Due to the low-resistivity nature of the etch-stop film when present on the surface of metallic materials, there is no need for etch-stop removal before proceeding with the interconnect formation process. A series of BEOL metallization lines 114 and via contacts 116 are formed in the ILD trenches, and are planarized to prepare for further formation of interconnects. This invention may be integrated in a similar manner as the damascene process is repeated sequentially to form a multilayer interconnect structure.

[0043] In one embodiment, the invention can also include a method of manufacturing a CMOS device on a substrate by forming a patterned array of dielectric materials 76,102 and metallic materials 74,106,108 on a substrate, and depositing an atomically thin film of variable resistivity (high-resistivity layer 86,110 and low-resistivity layer 72,108, having a thickness in a range up to 10 nm) simultaneously upon the dielectric material and the surface of the metallic material, respectively.

[0044] As shown in Figs. 3A-3B, the fabricated device of the present invention can be a CMOS device, such as a field-effect transistor (FET), including an assortment of architectures of these FETs, such as FinFETs, gate-all-around (GAA) FETs, complementary FETs (CFETs), and the like, or any memory or embedded memory devices fabricated in conjunction with these transistors, as well as the multi-layer metallization architectures used to connect and control such devices. The present invention is particularly advantageous in that metal levels with a tight pitch will benefit from an etch-stop layer that is both thin and insulating when present over the dielectric, but is conveniently conductive over underlying metals. A thin and uniformly controlled etch-stop layer (as is enabled by ALD thin films) decreases the effective dielectric constant of the metallization stack, and thereby improves interconnect speed through a lower RC time-constant. This integration scheme will also serve to simplify the fabrication process by eliminating the need for an etch-stop removal process before formation of subsequent metallization layers.

[0045] In one embodiment, the invention may be implemented as a form of area- selective deposition (ASD) such that the surface of a metal layer is preferentially modified at various locations in order to selectively form either an insulating or a conductive portion of subsequently deposited ALD TaN thin films. This allows for the selective formation of a pattern of low- and high-resistivity material atop the metal layer, a process whose applications may extend beyond the scope of those depicted in the aforementioned diagrams. [0046] In one embodiment, the underlying metal layer can be a superconducting metal, such as Ta, Nb, or any other superconducting metals or metallic alloys utilized in the fabrication process of quantum devices and other such applications. Alternatively, the underlying metal layer can be a non-superconducting metal or metal alloy, such as Cu, W, Ru, or any other metallization material utilized in the fabrication process of CMOS devices and other such applications. In both instances, the metallic layer may be formed by physical vapor deposition, chemical vapor deposition, electroplating deposition, epitaxial film growth, or any other deposition method commonly used to form metallic thin films suitable for such applications.

[0047] In one embodiment, the ALD TaN film can be an atomically thin film with a thickness preferentially in the range of 0-10 nm, deposited with such a method that high resistivity films are assured. This atomic layer deposition method may include the use of any of an assortment of tantalum-containing precursors, whether metal-organic or inorganic, any of an assortment of nitrogen-containing co-reactants, and may be either thermally driven or plasma assisted.

[0048] The treatment of exposed metal films may be accomplished by nitridation, including N2 plasma which can occur at low temperatures ranging between 25 and 700 °C by nitrogen plasma generated by low energy electron impact, as is known in the art. Furthermore, the nitridation may be accomplished by an NH3 pretreatment, which can be either a thermal treatment or plasma assisted. The nitridation may also be accomplished through the use of accelerated neutral atom beam (ANAB) processing in a nitrogen ambient. The above pre-treatment methods of the pure metal surface can be employed in order to convert the exposed surface of the metal to a partial nitride, while keeping the thickness of such a modified layer less than 1 nm.

[0049] The treatment of exposed metal films may be accomplished by light oxidation, such as thermal treatment or plasma assisted treatment in an oxidation chamber. Furthermore, the oxidation may be accomplished through the use of chemically- formed surface oxides, as are formed in the case of chemical-mechanical planarization. The oxidation may also be accomplished through the use of accelerated neutral atom beam (ANAB) processing in an oxygen ambient. Native metal oxide formation during atmospheric exposure of the exposed metal surface may also be leveraged as a method of surface oxidation. The above pre-treatment methods of the pure metal surface can be employed in order to convert the exposed surface of the metal to a partial oxide, while keeping the thickness of such a modified layer less than 1 nm.

[0050] If embodied with a metal nitride intervening layer separated from the metal surface, the metal nitride interlayer can be an insulating film formed by a reactively sputtered layer of PVD TaNx or PVD NbNx, such that the nitrogen-to-metal composition ratio is high enough to assure the formation of an insulating layer of PVD material.

[0051] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of one or more aspects of the invention and the practical application, and to enable others of ordinary skill in the art to understand one or more aspects of the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

CLAIMS What is claimed is:

1 . A quantum device, comprising: a substrate including a layer of superconducting metal, the superconducting metal layer having a surface thereof; a modification of the exposed surface of the superconducting metal; and a high-resistivity layer of atomically thin TaN having a thickness up to 10 nm, deposited over the superconducting metal layer surface.

2. The quantum device of claim 1 , wherein the surface modification is achieved through a metal nitride intervening layer deposited between the high- resistivity layer and superconducting metal layer.

3. The quantum device of claim 2, wherein the metal nitride intervening layer is comprised of physical vapor deposited TaN, physical vapor deposited NbN, or a combination thereof, with N content higher than 35 atomic %.

4. The quantum device of claim 1 , wherein the surface modification is achieved through nitridation of the surface of the superconducting metal layer.

5. The quantum device of claim 4, wherein the surface nitridation is achieved through exposure to a nitrogen-containing plasma, including N2 and NH3 plasmas.

6. The quantum device of claim 4, wherein the surface nitridation is achieved through thermal treatment with a nitrogen-containing compound, including NH3 exposure.

7. The quantum device of claim 4, wherein the surface nitridation is achieved through processing with accelerated neutral atom beam (ANAB) processing with N2 present in the ANAB beam.

8. The quantum device of claim 1 , wherein the surface modification is achieved through oxidation of the surface of the superconducting metal layer.

9. The quantum device of claim 8, wherein the surface oxidation is achieved through exposure to an oxidizing plasma.

10. The quantum device of claim 8, wherein the surface oxidation is achieved through oxidation by exposure to an oxygen-containing controlled ambient.

11. The quantum device of claim 8, wherein the surface oxidation is achieved through chemically-formed surface oxides, such as are formed during chemical mechanical planarization of metal surfaces

12. The quantum device of claim 8, wherein the surface oxidation is achieved through naturally-formed atmospheric native oxides.

13. The quantum device of claim 8, wherein the surface oxidation is achieved through processing with accelerated neutral atom beam (ANAB) with O2 present in the ANAB beam.

14. The quantum device of claim 1 , wherein the superconducting metal layer is comprised of Ta, Nb, Al, or any other superconducting metal, metal alloy, or intermetallic compounds and nitrides commonly used in such applications as are known in the art.

15. The quantum device of claim 1 , wherein the atomically thin tantalum nitride layer is deposited through atomic layer deposition.

16. The quantum device of claim 1 , wherein specifically controlled areas of the superconducting metal layer are modified, such that an atomically thin, area- selective tantalum nitride layer of variable-resistivity is formed.

17. The quantum device of claim 1 , wherein the quantum device is a Josephson Junction.

18. The quantum device of claim 1 , wherein the quantum device is a part of a superconducting qubit.

19. The quantum device of claim 1 , wherein the quantum device is a part of a superconducting quantum interference device (SQUID).

20. The quantum device of claim 1 , wherein the quantum device is a component of a single-flux-quantum (SFQ) digital logic architecture.

21. The quantum device of claim 1 , wherein the quantum device is a superconducting coplanar waveguide (CPW) resonator.

22. A semiconductor device, comprising: a substrate comprised of a pattern consisting of a region of exposed metal and a region of exposed dielectric; and a layer of atomically thin, variable-resistivity ALD TaN having a thickness up to 10 nm, deposited simultaneously over the metal layer surface and the dielectric layer surface.

23. The semiconductor device of claim 21 , wherein the metal pattern is comprised of Cu, W, Ru, or any other metal or metal alloy commonly used in such metallization applications as are known in the art.

24. The semiconductor device of claim 21 , wherein the dielectric pattern is comprised of silicon oxide, SiCOH, low-k dielectric, or any other inter-layer dielectric commonly used in such metallization applications as are known in the art.

25. The semiconductor device of claim 21 , wherein the atomically thin tantalum nitride layer is deposited through atomic layer deposition, including thermally- driven atomic layer deposition and plasma-assisted atomic layer deposition.

26 The semiconductor device of claim 21 , wherein specifically controlled areas of the exposed metal layer are modified, such that an atomically thin, area- selective tantalum nitride layer of variable-resistivity is formed.

27. The semiconductor device of claim 21 , wherein the variable-resistivity layer functions as an etch-stop layer.

28. The semiconductor device of claim 21 , wherein the semiconductor device is a CMOS logic device.

29. The semiconductor device of claim 21 , wherein the semiconductor device is a memory or emerging memory device.

30. The semiconductor device of claim 21 , wherein the semiconductor device includes a multi-layer metallization architecture.

31. A method of manufacturing a quantum device on a substrate, comprising: forming of a substrate including a layer of superconducting metal, the superconducting metal layer having a surface thereof; modifying of the exposed surface of the superconducting metal; and depositing of a high-resistivity layer of atomically thin ALD TaN having a thickness up to 10 nm, the high-resistivity layer deposited over the superconducting metal layer surface.

32. The method of claim 31 , wherein the surface modification is achieved through a metal nitride intervening layer deposited between the high-resistivity layer and superconducting metal layer.

33. The method of claim 32, wherein the metal nitride intervening layer is comprised of physical vapor deposited TaN, physical vapor deposited NbN, or a combination thereof.

34. The method of claim 31 , wherein the surface modification is achieved through nitridation of the surface of the superconducting metal layer.

35. The method of claim 34, wherein the surface nitridation is achieved through exposure to a nitrogen-containing plasma, including N2 and NH3 plasmas.

36. The method of claim 34, wherein the surface nitridation is achieved through thermal treatment with a nitrogen-containing compound, including NH3 exposure.

37. The method of claim 34, wherein the surface nitridation is achieved through processing with accelerated neutral atom beam (ANAB) with N2 present in the ANAB beam.

38. The method of claim 31 , wherein the surface modification is achieved through oxidation of the surface of the superconducting metal layer.

39. The method of claim 38, wherein the surface oxidation is achieved through exposure to an oxidizing plasma.

40. The method of claim 38, wherein the surface oxidation is achieved through thermal oxidation.

41. The method of claim 38, wherein the surface oxidation is achieved through chemically-formed surface oxides.

42. The method of claim 38, wherein the surface oxidation is achieved through naturally-formed atmospheric native oxides.

43. The method of claim 38, wherein the surface oxidation is achieved through processing with accelerated neutral atom beam (ANAB) with O2 present in the ANAB beam.

44. The method of claim 31 , wherein the superconducting metal layer is comprised of Ta, Nb, Al, or any other superconducting metal, metal alloy, or intermetallic compounds and nitrides commonly used in such applications as are known in the art.

45. The method of claim 31 , wherein the atomically thin tantalum nitride layer is deposited through atomic layer deposition, including thermally-driven atomic layer deposition and plasma-assisted atomic layer deposition.

46. The method of claim 31 , wherein specifically controlled areas of the superconducting metal layer are modified, such that an atomically thin, area-selective tantalum nitride layer of variable-resistivity is formed.

47. The method of claim 31 , further creating a Josephson Junction.

48. The method of claim 31 , further creating a superconducting qubit.

49. The method of claim 31 , further creating a superconducting quantum interference device (SQUID).

50. The method of claim 31 , further creating a component of a single-flux- quantum (SFQ) digital logic architecture.

51. The method of claim 31 , further creating a superconducting coplanar waveguide (CPW) resonator.

52. A method of manufacturing a semiconductor device on a substrate, comprising: forming of a substrate comprised of a pattern consisting of a region of exposed metal and a region of exposed dielectric; and depositing of a layer of atomically thin, variable-resistivity TaN having a thickness up to 10 nm, the layer deposited simultaneously over the metal layer surface and the dielectric layer surface.

53. The method of claim 52, wherein the metal pattern is comprised of Cu, W, Ru, or any other metal or metal alloy commonly used in such metallization applications as are known in the art.

54. The method of claim 52, wherein the dielectric pattern is comprised of silicon oxide, SiCOH, low-k dielectric, or a combination thereof.

55. The method of claim 52, wherein the atomically thin tantalum nitride layer is deposited through atomic layer deposition, including thermally-driven atomic layer deposition and plasma-assisted atomic layer deposition.

56. The method of claim 52, wherein specifically controlled areas of the exposed metal layer are modified, such that an atomically thin, area-selective tantalum nitride layer of variable-resistivity is formed.

57. The method of claim 52, wherein the variable-resistivity layer functions as an etch-stop layer.

58. The method of claim 52, further creating a CMOS logic device.

59. The method of claim 52, further creating a memory or emerging memory device.

60. The method of claim 52, further creating a multi-layer metallization architecture.