EP4689754A1

EP4689754A1 - Component carrier with stack and optical layer build-up for optical chip

Info

Publication number: EP4689754A1
Application number: EP24714817.4A
Authority: EP
Inventors: Tanja JOERG
Original assignee: AT&S Austria Technologie und Systemtechnik AG
Current assignee: AT&S Austria Technologie und Systemtechnik AG
Priority date: 2023-03-27
Filing date: 2024-03-14
Publication date: 2026-02-11
Also published as: CN121002417A; WO2024200033A1

Abstract

A component carrier (100), which comprises a stack (102, 108) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106), a double cavity (114) formed in, on and/or above the stack (102, 108) and comprising a first cavity (116) being arranged in a stepped configuration with a second cavity (118), and an optical chip (112) arranged at least partially in the double cavity (114) so that the first cavity (116) provides an optical connection and the second cavity (118) provides an electric connection of the optical chip (112).

Description

Component carrier with stack and optical layer build-up for optical chip

Field of the Invention

The invention relates to component carriers and to methods of manufacturing a component carrier.

Technological Background

In the context of growing product functionalities of component carriers equipped with one or more components and increasing miniaturization of such components as well as a rising number of components to be connected to the component carriers such as printed circuit boards, increasingly more powerful array-like components or packages having several components are being employed, which have a plurality of contacts or connections, with ever smaller spacing between these contacts. In particular, component carriers shall be mechanically robust and electrically reliable so as to be operable even under harsh conditions.

Conventional approaches of forming a package which includes an optical functionality have a high complexity and may suffer from signal distortion.

Summary of the Invention

There may be a need to form a compact component carrier with optical functionality and high signal integrity.

According to an exemplary embodiment of a first aspect of the invention, a component carrier is provided which comprises a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, an optical layer build-up on the stack forming an optical waveguide, and an optical chip coupled to the stack and optically coupled with the optical waveguide.

According to an exemplary embodiment of a second aspect the invention, a component carrier is provided which comprises a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, a double cavity formed in, on and/or above the stack and comprising a first cavity being arranged in a stepped configuration with a second cavity, and an optical chip arranged at least partially in the double cavity so that the first cavity provides an optical connection and the second cavity provides an electric connection of the optical chip.

According to an exemplary embodiment of a third aspect of the invention, a component carrier is provided which comprises a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, a first optical chip assembled to the stack, a second optical chip assembled to the stack, and an optical layer bridge formed on and/or in the stack and providing an optical connection of the first optical chip with the second optical chip.

According to an exemplary embodiment of a fourth aspect of the invention, a component carrier is provided which comprises a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, and an optical layer build-up, for example coupled with an optical chip, arranged on the stack and forming an optical waveguide which has an optical waveguide layer arranged at the same vertical level as one of the at least one electrically conductive layer structure of the stack.

According to another exemplary embodiment of the first aspect of the invention, a method of manufacturing a component carrier is provided, wherein the method comprises providing a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, forming an optical layer build-up on the stack to thereby form an optical waveguide, and optically coupling an optical chip with the optical waveguide and coupling the optical chip to the stack.

According to another exemplary embodiment of the second aspect of the invention, a method of manufacturing a component carrier is provided, wherein the method comprises providing a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, forming a double cavity in, on and/or above the stack comprising a first cavity being arranged in a stepped configuration with a second cavity, and assembling an optical chip at least partially in the double cavity so that the first cavity provides an optical connection and the second cavity provides an electric connection of the optical chip. According to another exemplary embodiment of the third aspect of the invention, a method of manufacturing a component carrier is provided, wherein the method comprises providing a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, assembling a first optical chip to the stack, assembling a second optical chip to the stack, and optically connecting the first optical chip with the second optical chip by an optical layer bridge formed on and/or in the stack.

According to another exemplary embodiment of the fourth aspect of the invention, a method of manufacturing a component carrier is provided, wherein the method comprises providing a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, and arranging an optical layer build-up on the stack for forming an optical waveguide which has an optical waveguide layer arranged at the same vertical level as one of the at least one electrically conductive layer structure.

In different embodiments, the first aspect and/or the second aspect and/or the third aspect and/or the fourth aspect may be provided in isolation or may be combined.

In the context of the present application, the term "component carrier" may particularly denote any support structure which is capable of accommodating, directly or indirectly, one or more components thereon and/or therein for providing mechanical support and/or electrical connectivity. In other words, a component carrier may be configured as a mechanical and/or electronic carrier for components. In particular, a component carrier may be one of a printed circuit board, an organic interposer, and an IC (integrated circuit) substrate. A component carrier may also be a hybrid board combining different ones of the above-mentioned types of component carriers.

In the context of the present application, the term "stack" may particularly denote a flat or planar sheet-like body. For instance, the stack may be a layer stack, in particular a laminated layer stack or a laminate. Such a laminate may be formed by connecting a plurality of layer structures by the application of mechanical pressure and/or heat. Preferably, the (in particular laminated) layers may be parallel shifted (in stack thickness direction) in space. Electrically insulating layer structures of the stack may comprise organic material. In the context of the present application, the term "layer structure" may particularly denote a continuous layer, a patterned layer or a plurality of non- consecutive islands within a common plane.

In the context of the present application, the term "optical chip" may particularly denote a chip having an optical functionality. Such an optical chip may comprise at least one integrated chip waveguide. In particular, such an optical chip may be a chip configured for receiving and/or emitting optical signals, and more particularly for converting received optical signals into electric signals by an electrooptical converter (such as a photodiode). The optical chip may also have processing capability for processing optical signals and/or an electric signal. The optical chip may be an electro-optical chip, in particular providing an optical functionality of an electro-optical system. In particular, the optical chip may also have an integrated semiconductor laser diode and/or an amplifier. Hence, examples of integrated circuit elements of an optical chip may be a photodiode and/or a laser diode. For example, integrated group IV devices and/or group III- V devices may be implemented in the optical chip, for example at least one laser, at least one amplifier and/or at least one photodiode. In particular, the optical chip may have waveguide structures integrated to guide the light between different optical elements (like laser diode, photodiode, etc.).

In the context of the present application, the term "optical layer buildup" may particularly denote a stacked arrangement of two or more optically functionally layer structures. For example, an optical layer build-up may be composed of at least three stacked optically functionally layer structures. A central one of said layer structures may be a waveguide core layer along which light (for instance a light signal) may propagate. The waveguide core layer may be covered on both opposing main surfaces with the respective waveguide cladding layer.

In the context of the present application, the term "optical waveguide" may particularly denote a structure that guides optical waves, such as electromagnetic waves in the visible, infrared and/or ultraviolet wavelengths range. Propagation of electromagnetic radiation in a waveguide may be performed with low loss of electromagnetic radiation energy by spatially restricting the transmission of the electromagnetic radiation energy, in particular to one direction. In particular, an optical waveguide may be connected to a fiber connector by a horizontal connection extending parallel to a main surface direction and/or by a vertical connection perpendicular to a main surface direction. In the context of the present application, the optical waveguide of the optical layer build-up may cooperate with a chip waveguide of the optical chip for transmitting light in between.

In the context of the present application, the term "optical waveguide layer" may particularly denote a layer structure being configured for forming part of a waveguide build-up for guiding optical light along or within said waveguide build-up. In particular, said optical light may be enabled to propagate inside of said waveguide build-up in a controlled or defined way. In particular, an optical waveguide layer may form part of an optical layer build-up of a plurality of stacked optical layer structures. More specifically, an optical waveguide layer may be one layer of a stacked configuration of a waveguide core layer between two waveguide cladding layers which form together a stacked optical waveguide. For example, a thickness of a waveguide core layer may be in a range from 2 pm to 15 pm. For example, a thickness of a waveguide cladding layer may be in a range from 10 pm to 500 pm. More generally, a thickness of an optical waveguide layer may be in a range from 1 pm to 800 pm.

In the context of the present application, the term "optically coupled" or "optically connected" may particularly denote an arrangement in which different optical members are linked so that optical electromagnetic radiation is enabled to propagate between said optical members, in particular in a controlled way.

In the context of the present application, the term "coupled with the stack" may particularly denote a mechanical and/or an electrical coupling to the stack.

In the context of the present application, the term "cavity" may particularly denote a recess, groove or hole (in particular blind hole or through hole) extending up to and/or into the stack and/or in the optical layer build-up. Preferably, all the sides of the cavity may be defined by layer structures of the stack and/or the optical layer build-up. In the context of the present application, the term "double cavity" may particularly denote an arrangement of two individual cavities which are connected with each other or are merged so as to form one common integral cavity having two mutually connected cavity portions with different structural properties (in particular different dimensions) for providing cooperating functions. Such cooperating functions may be accommodation functions for accommodating two different entities, in particular an optical entity and an electrical entity. For example, such a double cavity may be formed by firstly forming one cavity and thereafter forming the other cavity. Alternatively, it is possible to form both cavities of a double cavity in one common processing stage. For forming a cavity, it may be for example possible to integrate in a stack a poorly adhesive structure, such as a release layer. Thereafter, a piece of the stack may be cut out circumferentially (for instance mechanically or by a laser) and may be taken out of the stack thanks to the poorly adhesive property of the poorly adhesive structure on the bottom side of the piece. In another approach, it is also possible to form a double cavity by a subtractive process, for instance by two subsequent milling processes with different milling diameter in different depth regions of the stack. For example, the shape of the double cavity can be as follows: A smaller cavity may be on the bottom and a larger cavity can be on top of the smaller one for forming the stepped shape. Preferably, an optical chip is accommodated at least partially in the larger cavity on the top. Preferably, the electrical connection of the optical chip with the stack is provided within the smaller bottom cavity. More preferably, the upper surface of the resulting step comprises at least one waveguide directly exposed to and/or abutting with the optical chip. Preferably, the stack is covered by the optical layer build-up and is exposed by the smaller bottom cavity. In particular, the double cavity may be formed in an optical layer build-up, more particularly extending vertically through the entire optical layer build-up.

In the context of the present application, the term "stepped configuration" may particularly denote a structural feature of a double cavity with a larger cavity section and an integrally connected smaller cavity section being connected with each other at one or more lateral steps. For example, each cavity may comprise a cylindrical, cuboid or frustoconical hollow volume, wherein two such hollow volumes of different dimensions (in particular different diameters) are directly connected with each other to form a larger hollow volume which has at least one step in a connection region between said individual hollow volumes.

In the context of the present application, the term "optical layer bridge" may particularly denote an optical connection structure arranged for optically connecting two different optical members such as optical chips. Consequently, electromagnetic radiation in the optical domain may be enabled to propagate between two different optical members (such as two optical chips) along the optical layer bridge. For example, an optical layer bridge may be formed inside an optical layer build-up with a waveguide core layer (which may be transmissive for light) covered on both opposing main surfaces by a respective waveguide cladding layer (into which the light or at least the majority of light will not propagate). In a respective connection region in which the optical layer bridge is mechanically and optically connected to a respective optical chip, a section of a waveguide cladding layer may be removed so as to establish a direct physical contact between the waveguide core layer and an optical light emission element and/or detection element of the respective optical chip. For example, an optical coupling between the optical chip and the optical layer bridge may then be accomplished by evanescent coupling.

In the context of the present application, the term "an optical waveguide layer arranged at the same vertical level as an electrically conductive layer structure" may particularly denote a spatial configuration according to which the optical waveguide layer and the electrically conductive layer structure share a common vertical position. Said optical waveguide layer and said electrically conductive layer structure may share a common horizontal plane. For instance, said electrically conductive layer structure may extend vertically up to said common horizontal plane, whereas said optical waveguide layer may extend upwardly from said common horizontal plane, or vice versa. It is also possible that at least part of said electrically conductive layer structure and at least part of said optical waveguide structure are arranged side-by-side over an identical or overlapping vertical range. Such a configuration may be manufactured by firstly forming the stack and then arranging the optical layer build-up at least partially on the stack, and optionally partially inside of part of the stack.

In the context of the present application, the term "light" may particularly denote optical electromagnetic radiation in the electromagnetic spectrum having a certain wavelength or wavelength range, for instance visible light, ultraviolet light and/or infrared light. In particular, light may be in the O-band and/or in the C-band. The O-band is from 1260-1360 nm (including 1310 nm), whereas the C-band is from 1530-1560 nm (including 1550 nm). These ranges cover relevant wavelengths used in optical communications. For example, in some applications, 8 wavelengths per waveguide are used, and for instance up to 32 waveguides. Exemplary embodiments may relate to single-mode waveguides that carry only a single ray of light (i.e. a single mode) or may relate to multi-mode waveguides that carry multiple rays of light (i.e. multiple modes). For example, the mentioned light may be an optical light beam.

In the context of the present application, the term "main surface" of a body may particularly denote one of two largest opposing surfaces of the body. The main surfaces may be connected by circumferential side walls. The thickness of a body, such as a stack, may be defined by the distance between the two opposing main surfaces.

According to an exemplary embodiment of the first aspect, a component carrier (such as a printed circuit board or an integrated circuit substrate) of stacked layer type is provided which is equipped with an optical layer build-up on a layer stack with wiring structure. Said optical layer build-up forms an optical waveguide optically coupled with an optical chip which may be mounted on or above the stack. Advantageously, an electrooptical double stack may thus be formed with an electrically conductive wiring structure in a bottom stack and an optically functional top stack providing a waveguide function for propagating light. Such a double stack may lead to a component carrier being highly compact in vertical direction and combining electric and optical functionality. Furthermore, this may lead to short optical and electric paths, and therefore low loss and high signal quality both in an electrical and an optical domain.

According to an exemplary embodiment of the second aspect, a component carrier (such as a printed circuit board or an integrated circuit substrate) of stacked layer type is provided which has a double cavity which may be formed at least partially on top of the stack and/or at least partially integrated in the stack. Said double cavity may comprise a stepped configuration of two partial cavities. Such a double cavity may provide an excellent basis for accommodating an optical chip for simultaneously establishing both an optical and an electric coupling between stack and optical chip.

According to an exemplary embodiment of the third aspect, a component carrier (such as a printed circuit board or an integrated circuit substrate) of stacked layer type is provided which comprises a plurality of optical chips being surface mounted on or above and/or embedded in the stack. Advantageously, an optical layer bridge on and/or in the stack may optically couple said optical chips. This may allow a highly compact configuration for accomplishing an optical chip-to-chip coupling resulting in a short optical path, which may be for example purely horizontal. This may lead, in turn, to a low loss and high signal quality in the optical domain.

According to an exemplary embodiment of the fourth aspect, a component carrier (such as a printed circuit board or an integrated circuit substrate) of stacked layer type is provided which includes an optical layer build-up on the stack. Optionally, such an optical layer build-up may be coupled with an optical chip. Advantageously, said optical layer build-up may form an optical waveguide comprising optical waveguide layers. At least one of said optical waveguide layers may be arranged at the same vertical level as an electrically conductive layer structure of the stack (for example, a main surface of said optical waveguide layer may be coplanar with a main surface of said electrically conductive layer structure). By positioning or locating an optical waveguide layer and an electrically conductive layer structure at the same height level of the component carrier, short optical and electric paths may be obtained. This may lead, in turn, to low loss and high signal quality both in an electrical and an optical domain.

Detailed Description of Exemplary Embodiments

In the following, further exemplary embodiments of the component carriers and the methods will be explained. In an embodiment, an optical layer build-up is provided at the same vertical level as the optical layer bridge. Preferably, the optical layer build-up and the optical layer bridge are provided on the stack. In an embodiment of the corresponding manufacturing method, the optical layer bridge and the optical layer build-up may be formed from a common build-up structure (optionally patterned). In an embodiment, the optical layer bridge is formed based on an optical layer build-up. This may bring the advantage of reducing the amount of total layers (in particular optical layers and/or build up layers) while still ensuring high freedom of the design of the component carrier.

In an embodiment of the fourth aspect, a double cavity may be provided. The cavity may be formed in the optical layer build-up. Preferably, the optical chip is provided in the cavity on the top side. Preferably, the electrical connection of the optical chip with the stack is provided by at least one electrically conductive layer structure of the stack. Furthermore, the stack may be covered by the optical layer build-up and may be exposed by the cavity where the at least one electrically conductive layer structure is provided. This may bring the advantage of combining good mechanical integration of the optical chip within the component carrier and ensuring reliable optical and electronic connection between the component carrier and the optical chip.

In an embodiment, an optical layer build-up is arranged on the stack and forms an optical waveguide which is optically coupled with the optical chip. A double cavity may be provided in the optical layer build-up, and at least a portion of the optical layer build-up may be exposed on the surface of the component carrier. Thus, well established manufacturing processes in the field of PCB technologies may be used to create a reliable connection between the optical layer build-up and the stack.

In an embodiment, the optical chip and the optical waveguide are optically coupled by evanescent coupling. Evanescent coupling between optical chip and optical waveguide may be effected by placing optical coupling portions so close together that the evanescent field generated by one of optical chip and optical waveguide excites a wave in the other one. Such a direct optical connection between the optical chip and the optical waveguide may lead to a short optical path, to a compact design and to low optical losses as well as to a high signal quality. In an embodiment, the optical chip and the optical waveguide are optically coupled with each other by optically coupling, on the one hand, a chip waveguide formed as part of the optical chip on a main surface of the optical chip, and, on the other hand, an exposed waveguide core layer of the optical layer build-up. Said chip waveguide may be integrated in the optical chip. For instance, the chip waveguide may be manufactured in silicon on insulator (SOI) technology or in indium phosphide (InP) technology. This may bring the advantage of connecting and/or coupling the (for example light) signals between the optical chip and the optical waveguide while ensuring small or no signal losses.

In an embodiment, the component carrier comprises a fiber connector arranged on and/or in the stack and being connected with the optical waveguide for establishing an optical connection with an optical fiber. Said optical fiber may be arranged apart from the stack and apart from the optical layer build-up. It is possible that the fiber connector is assembled at a sidewall of the component carrier, for instance at an upper sidewall of the stack and/or an optical layer build-up thereon. In such a sidewall region, a cavity may be formed in which the fiber connector may be accommodated. Thus, the fiber connector may be arranged, partially or entirely, in a cavity formed in the stack and/or in the optical layer build-up. This may lead to a compact design of the component carrier in vertical direction and to an efficient coupling of light (in particular in form of optical light signals) from the component carrier to a periphery or from a periphery to the component carrier.

In an embodiment, the optical layer build-up comprises a stacked optical layer sequence comprising a waveguide core layer between two waveguide cladding layers. Descriptively speaking, light guided by such a waveguide-type optical layer build-up may propagate through the waveguide core layer and will not or at least not predominantly propagate into the waveguide cladding layers. Descriptively speaking, a stacked optical layer sequence with core layer and cladding layers may fulfil the same optical function as a cable-type optical waveguide, however in a very compact design. Thus, the optical waveguide technology can be adjusted to the requirements of laminated layer stack technology. To put it shortly, a planar waveguide may be provided in form of an optical layer build-up of a plurality of optical layer structures, which may be connected for example by lamination.

In an embodiment, a waveguide core layer of the optical layer build-up comprises a plurality of optical coupling channels. Hence, a plurality of physically separate optical transmission paths may be provided in the waveguide core layer in form of independent optical coupling channels. Over each optical coupling channel, a separate optical signal may be transmitted. The optical coupling channels may be arranged side-by-side in a common horizontal plane. Such an approach allows to increase the amount of optical data which can be transmitted over a planar waveguide formed by an optical layer buildup.

In an embodiment, the optical coupling channels extend parallel to each other. All optical coupling channels may be coplanar so that optical signals may be transmitted simultaneously within one and the same plane.

In an embodiment, at least part of the optical coupling channels have an at least partially tapering shape. In particular at an end of the optical coupling channels, at which their optical signals may be coupled into or out of at least one chip waveguide of an optical chip, the optical signal may be focused to comply with small dimensions of a chip waveguide. Apart from the optical chip, the optical coupling channels may have a broader diameter. The tapering optical coupling channels may taper laterally within a horizontal plane. A chip waveguide (i.e. a waveguide integrated with an optical chip) assigned to a respective tapering optical coupling channel may also be arranged with a tapering shape, wherein preferably the tapering directions of the chip waveguide and of the optical coupling channel may be inverse. This may bring the advantage of focusing the optical (in particular light) signal to the contact por- tion(s) of the optical chip in order to reduce signal losses. Any of the tapering sections may have a length in a range from 0.1 mm to 5 mm. This value may equal to the optical coupling length between the chip waveguide and the optical waveguide.

In an embodiment, the optical coupling channels are spaced by optically inactive spacer sections. Such spacer sections may be optically reflective or optically opaque so that optical signals propagating along different optical cou- pling channels can be prevented from being unintentionally coupled into another optical coupling channel. This may avoid an undesired crosstalk between different optical coupling channels.

In an embodiment, there can be a plurality of light signals in one optical coupling channel. Additionally or alternatively, a plurality of optical coupling channels may be formed. It is also possible that an optical coupling channel can transport more than one wavelength simultaneously. For example, an optical coupling channel can carry different wavelengths Al, A2, A3, A4, etc. (for instance up to 8 wavelengths in the O-band or C-band).

In an embodiment, the optical layer build-up is formed based on an organic polymer film material. An organic material may comprise a chemical compound that contains carbon-hydrogen bonds. For example, the optical layer build-up may comprise an organic resin material, an epoxy material, etc. For instance, said organic material may be a polymer, in particular may comprise at least one epoxy, modified acrylate, polysiloxane or organic-inorganic hybrid. Such organic polymer film materials are fully compatible with organic stack material of PCB technology (such as resin, prepreg or FR.4), which may form part of the stack beneath the optical layer build-up. This may bring the advantage of good adhesion between the optical layer build-up and the stack of the component carrier.

In an embodiment, the component carrier comprises a double cavity in the optical layer build-up. A double cavity on an optical layer build-up above a laminated layer stack with wiring structure may enable both an electric connection with the stack and an optical connection with optical layer build-up. This may lead to a compact design and high signal integrity, both in an electric and in an optical domain.

Preferably, the double cavity comprises a first cavity establishing an optical connection of the optical chip, arranged at least partially in the double cavity, with the optical layer build-up, and comprises a second cavity establishing an electric connection of the optical chip with the stack. The optical chip may be mechanically coupled to the stack and/or to the optical layer build-up. Preferably, the optical chip may be in contact with the optical layer build-up so as to establish an optical connection in between. Moreover, the optical chip may be in contact with the stack so as to establish an electrical connection in between.

In an embodiment, the first cavity and the second cavity form a stepped configuration. The second cavity may have a smaller diameter than the first cavity. A step may be formed between the first cavity and the second cavity. Such a stepped-tapering geometry may also contribute to a self-centering of an optical chip when assembled into the double cavity.

In a preferred configuration, the component carrier comprises a double cavity formed in, on and/or above the stack and comprising a first cavity being arranged in a stepped configuration with a second cavity. Preferably, the optical chip is arranged at least partially in the double cavity so that the first cavity provides an optical connection and the second cavity provides an electric connection of the optical chip. Hence, an electric connection and an optical connection may be established simultaneously when assembling the optical chip in the double cavity. This simplifies the manufacturing process and keeps signal paths short.

In an embodiment, the double cavity is formed in an optical layer buildup formed on the stack. More specifically, the double cavity may be formed to extend entirely through the optical layer build-up up to an exposed upper main surface of the stack. Inserting an optical chip into such a double cavity may then establish automatically both an optical and an electrical connection. This may be done in a very simple way.

In an embodiment, a horizontal surface (which may be an optical coupling surface) of the first cavity is defined at least partially by a waveguide core layer of the optical layer build-up. In other words, the first cavity may expose a waveguide core layer which, in other sections of the optical layer buildup, may be covered on both opposing main surfaces by a respective waveguide cladding layer. By removing a section of the upper waveguide cladding layer for exposing the waveguide core layer at a bottom of the first cavity, an optical connection with a chip waveguide at a bottom side of the optical chip may be efficiently prepared.

Still referring to the previously described embodiment, an optical coupling may be established between the waveguide core layer and a chip wave- guide formed at a bottom main surface of the optical chip. Additionally or alternatively, an electrical coupling may be established between stack pads of the at least one of the at least one electrically conductive layer structure on the horizontal surface of the second cavity and chip pads formed at the bottom main surface of the optical chip.

In an embodiment (which may or may not be combined with the aforementioned embodiment), a horizontal surface (which may be an electrical coupling surface) of the second cavity is defined at least partially by at least one of the at least one electrically conductive layer structure. To put it shortly, formation of the second cavity may remove a bottom portion of the optical layer build-up to thereby expose a main surface of the stack beneath the optical layer build-up. As a result, at least one electrically conductive layer structure at a top main surface of the stack may be exposed. Consequently, assembling an optical chip in the first cavity may allow to form an electric connection between at least one bottom-sided optical chip pad with a corresponding stack pad of the exposed electrically conductive layer structure by an electric connection structure (such as a solder structure or a sinter structure) in between. Preferably, the vertical thickness of the second cavity may correspond to the thickness of the electric connection structure plus the thicknesses of the optical chip pad and the stack pad.

In an embodiment, the component carrier comprises a second optical chip assembled to the stack, and an optical layer bridge formed on and/or in the stack and providing an optical connection of the optical chip with the second optical chip. Such an optical layer bridge may extend purely horizontally, purely vertically, in a slanted way, or may comprise horizontal and vertical sections for optically coupling the various optical chips with each other. The optical layer bridge may be formed as an optical layer build-up, which may be composed for example of a plurality of optically functional stacked layer structures.

In an embodiment, the optical layer bridge comprises an optical layer build-up forming an optical waveguide. Such a stacked layer-type optical waveguide may be composed of a central waveguide core layer sandwiched between two peripheral waveguide cladding layers. Preferably, an optical coupling can be established between a waveguide core layer of the optical layer build-up and a chip waveguide formed at a bottom main surface of the first optical chip and/or of the second optical chip. This may bring the advantage of transferring signals between the first optical chip and the second optical chip in a fast and reliable way (referring to the speed of light).

In an embodiment, an optical layer build-up arranged on the stack and forming an optical waveguide has an optical waveguide layer arranged at the same vertical level as one of the at least one electrically conductive layer structure. Such an at least partially coplanar configuration of optical waveguide layer and electrically conductive layer structure provides an appropriate basis for establishing an electrical and an optical coupling in a spatially compact way.

In an embodiment, the component carrier comprises an optical chip assembled to the stack, being optically coupled with the optical waveguide and being electrically coupled with the at least one electrically conductive layer structure. Such an optical chip may be at least partially embedded in the cavity, may be surface mounted or may be completely embedded in an interior of the component carrier. This may bring the advantage of combining good mechanical integration of the optical chip within the component carrier and ensuring reliable optical and electronic connection between the component carrier and the optical chip.

In an embodiment, the component carrier comprises a cavity (which may be a double cavity with stepped configuration, for example configured as described above) in the optical layer build-up and on or above the stack for establishing an optical connection of the optical chip and for establishing an electric connection of the optical chip. Arranging the component carrier in a cavity may lead to a compact design in a vertical direction. Furthermore, this may render the signal paths short, which may have a positive impact on signal integrity.

In an embodiment, the component carrier comprises a further cavity (which may be a double cavity with stepped configuration, for example as described above) in the same optical layer build-up and on or above the stack for establishing an optical connection of a further optical chip and establishing an electric connection of the further optical chip. Hence, also a multi-cavity arrangement may be implemented in the stack and/or the optical layer build-up for simplifying chip assembly and for rendering chip assembly more efficient.

In an embodiment, the component carrier comprises an electric chip assembled to the stack and being electrically coupled with the optical chip. In the context of the present application, the term "electric chip" may particularly denote a chip having an electric functionality. For example, the electric chip may be configured for processing electric signals, in particular received from an optical chip. It is also possible that the electric chip comprises a drive functionality, in particular for driving an optical chip. The electric chip may be an electro-optical chip, in particular providing an electric functionality of an electro-optical system. In particular, the electric chip may have amplifying functionality, for instance provided by one or more transimpedance amplifiers (TIAs). When embodied as a transmitter, the electric chip may function as interface between a modulator and its driver. When embodied as receiver, the electric chip may function as interface between the photodiode and an assigned TIA.

In an embodiment, the component carrier comprises a horizontal electric connection trace arranged at a main surface of the stack and electrically coupling the electric chip with the optical chip. For example, such a horizontal electric connection trace may be provided between the stack and the optical layer build-up. A horizontal electric connection trace may electrically couple the optical chip and the electric chip in a short and simple way. Thus, such a configuration may also contribute to low signal loss at high signal quality.

In an embodiment, a central portion of one main surface of the optical chip has an electric interface (preferably configured as chip pads) and a peripheral portion of said main surface of the optical chip has an optical interface (preferably embodied as chip waveguide(s) integrated with the optical chip). This may allow to automatically establish both an optical coupling and an electrical coupling when the optical chip is assembled in a correspondingly configured cavity extending through an optical layer build-up and up to a stack with electric wiring structure. The central portion of the optical chip may then be electrically coupled with an electrically conductive layer structure of the stack, whereas the peripheral portion may then be optically coupled with an electromagnetic radiation emitting and/or detecting portion of the optical chip.

In an embodiment, the component carrier comprises a highly thermally conductive block being thermally coupled with the optical chip. During operation of an optical chip, a considerable amount of heat may be generated. In order to avoid overheating of the optical chip, heat may be dissipated in an efficient and simple way by thermally coupling a highly thermally conductive block (for example having a thermal conductivity of at least 50 W/mK) with the optical chip. For example, such a highly thermally conductive block may be a metal block (in particular a copper block or an aluminum block) or a ceramic block (for example comprising aluminum oxide or aluminum nitride), optionally covered with at least one metallic surface layer. In one embodiment, a highly thermally conductive block may be embedded in the stack, and the optical chip may be mounted on top of the highly thermally conductive block. However, it is also possible to embed the optical chip in the stack and to surface mount the highly thermally conductive block on top of the optical chip.

In an embodiment, the highly thermally conductive block is in direct contact with or is connected by a plurality of thermal vias with the optical chip. For example, the optical chip may be mounted directly on top of the highly thermally conductive block, so that heat may be dissipated towards a bottom side of the optical chip and optical and/or electrical signals may be handled by the optical chip at a top side thereof. In another embodiment, it is also possible that a set of thermal vias, such as metallized vias (for instance copper- filled laser vias), is arranged side-by-side and in contact with one main surface of the optical chip, wherein said thermal vias are connected to the highly thermally conductive block. As a result, the highly thermally conductive block can extend up to a bottom of the stack even when the stack is quite thick, wherein a vertical distance between the highly thermally conductive block and the optical chip may be bridged by the thermal vias, which may also be provided in a stacked configuration.

In an embodiment, the highly thermally conductive block and the optical chip are stacked and extend through the entire stack (in stack thickness direction). More specifically, the highly thermally conductive block and the optical chip may be in direct contact or may be contacted indirectly by thermal vias. The highly thermally conductive block and the optical chip may both be embedded in the stack, or one of them may be surface mounted on the stack whereas the other one may be embedded in the stack. This may bring the advantage of transporting heat to an exposed surface in an efficient way.

In an embodiment, the component carrier comprises an electric chip being stacked with the highly thermally conductive block and with the optical chip, wherein the optical chip is arranged vertically in between the electric chip and the highly thermally conductive block. For example, such a configuration is shown in Figure 12. For instance, the highly thermally conductive block and the optical chip may be embedded in the stack, whereas the electric chip may be surface mounted on the stack. The heat flow may occur vertically downwardly from the optical chip to the highly thermally conductive block. The signal flow between optical chip and electric chip may occur above the optical chip along a vertical direction. Hence, heat flow and signal flow may be advantageously decoupled from each other.

In an embodiment, the component carrier comprises an electric chip being assembled on the stack laterally displaced with respect to the highly thermally conductive block and with respect to the optical chip, wherein the optical chip is electrically coupled with the electric chip by the at least one electrically conductive layer structure. Such a configuration is shown for example in Figure 13. For example, the highly thermally conductive block and the optical chip may be embedded in the stack, whereas the electric chip may be surface mounted on the stack. The heat flow may occur vertically downwardly from the optical chip to the highly thermally conductive block. The signal flow between optical chip and electric chip may occur above the optical chip along a horizontal direction. Since the upper main surface of the optical chip may be exposed in such an embodiment, the optical chip may experience efficient heat removal at both opposing main surfaces thereof.

In an embodiment, the component carrier comprises at least one alignment mark formed at the optical layer build-up. Thus, the optical layer buildup may not only be used for providing an optical function (such as a waveguide function with planar configuration), but may additionally comprise one or more alignment marks for improving alignment accuracy during a manufacturing process. This may bring the advantage of reducing process steps of the manufacture of the component carrier.

In an embodiment, the component carrier comprises a stack of at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier may be a laminate of the mentioned electrically insulating layer structure(s) and electrically conductive layer structure(s), in particular formed by applying mechanical pressure and/or thermal energy. The mentioned stack may provide a plate-shaped component carrier capable of providing a large mounting surface for further components and being nevertheless very thin and compact.

In an embodiment, the component carrier is shaped as a plate. This contributes to the compact design, wherein the component carrier nevertheless provides a large basis for mounting components thereon. In particular, a naked die as example for an electronic component can be surface mounted on a thin plate such as a printed circuit board.

In an embodiment, the component carrier is configured as one of the group consisting of a printed circuit board, a substrate (in particular an IC substrate), and an interposer.

In the context of the present application, the term "printed circuit board" (PCB) may particularly denote a plate-shaped component carrier which is formed by laminating several electrically conductive layer structures with several electrically insulating layer structures, for instance by applying pressure and/or by the supply of thermal energy. As preferred materials for PCB technology, the electrically conductive layer structures are made of copper, whereas the electrically insulating layer structures may comprise resin and/or glass fibers, so-called prepreg or FR4 material. The various electrically conductive layer structures may be connected to one another in a desired way by forming holes through the laminate, for instance by laser drilling or mechanical drilling, and by partially or fully filling them with electrically conductive material (in particular copper), thereby forming vias or any other through-hole connections. The filled hole either connects the whole stack, (through-hole connections extending through several layers or the entire stack), or the filled hole connects at least two electrically conductive layers, called via. Similarly, optical interconnections can be formed through individual layers of the stack in order to receive an electro-optical circuit board (EOCB). A printed circuit board is usually configured for accommodating one or more components on one or both opposing surfaces of the plate-shaped printed circuit board. They may be connected to the respective main surface by soldering. A dielectric part of a PCB may be composed of resin with reinforcing fibers (such as glass fibers).

In the context of the present application, the term "substrate" may particularly denote a small component carrier. A substrate may be a, in relation to a PCB, comparably small component carrier onto which one or more components may be mounted and that may act as a connection medium between one or more chip(s) and a further PCB. For instance, a substrate may have substantially the same size as a component (in particular an electronic component) to be mounted thereon (for instance in case of a Chip Scale Package (CSP)). More specifically, a substrate can be understood as a carrier for electrical connections or electrical networks as well as component carrier comparable to a printed circuit board (PCB), however with a considerably higher density of laterally and/or vertically arranged connections. Lateral connections are for example conductive paths, whereas vertical connections may be for example drill holes. These lateral and/or vertical connections are arranged within the substrate and can be used to provide electrical, thermal and/or mechanical connections of housed components or unhoused components (such as bare dies), particularly of IC chips, with a printed circuit board or intermediate printed circuit board. Thus, the term "substrate" also includes "IC substrates". A dielectric part of a substrate may be composed of resin with reinforcing particles (such as reinforcing spheres, in particular glass spheres).

The substrate or interposer may comprise or consist of at least a layer of glass, silicon (Si) and/or a photoimageable or dry-etchable organic material like epoxy-based build-up material (such as epoxy-based build-up film) or polymer compounds (which may or may not include photo- and/or thermosensitive molecules) like polyimide or polybenzoxazole.

In an embodiment, the at least one electrically insulating layer structure comprises at least one of the group consisting of a resin or a polymer, such as epoxy resin, cyanate ester resin, benzocyclobutene resin, Melamine derivates, Polybenzoxabenzole (PBO), bismaleimide-triazine resin, polyphenylene deri- vate (e.g. based on polyphenylenether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), Bisbenzocyclobu- tene (BCB) and/or a combination thereof. Reinforcing structures such as webs, fibers, spheres or other kinds of filler particles, for example made of glass (multilayer glass) in order to form a composite, could be used as well. A semicured resin in combination with a reinforcing agent, e.g. fibers impregnated with the above-mentioned resins is called prepreg. These prepregs are often named after their properties e.g. FR4 or FR5, which describe their flame retardant properties. Although prepreg particularly FR4 are usually preferred for rigid PCBs, other materials, in particular epoxy-based build-up materials (such as build-up films) or photoimageable dielectric materials, may be used as well. For high frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymer and/or cyanate ester resins, may be preferred. Besides these polymers, low temperature cofired ceramics (LTCC) or other low, very low or ultra-low DK materials may be applied in the component carrier as electrically insulating structures.

In an embodiment, the at least one electrically conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, tungsten and magnesium. Although copper is usually preferred, other materials or coated versions thereof are possible as well, in particular coated with supra-conductive material or conductive polymers, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT), respectively.

At least one component can be selected from a group consisting of an electrically non-conductive inlay, an electrically conductive inlay (such as a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (for example a heat pipe), a light guiding element (for example an optical waveguide or a light conductor connection), an electronic component, or combinations thereof. An inlay can be for instance a metal block, with or without an insulating material coating (IMS-inlay), which could be surface mounted for the purpose of facilitating heat dissipation. Suitable materials are defined according to their thermal conductivity, which should be at least 2 W/mK. Such materials are often based, but not limited to metals, metal-oxides and/or ceramics as for instance copper, aluminium oxide (AI2O3) or aluminum nitride (AIN). In order to increase the heat exchange capacity, other geometries with increased surface area are frequently used as well. Furthermore, a component can be an active electronic component (having at least one p-n-junction implemented), a passive electronic component such as a resistor, an inductance, or capacitor, an electronic chip, a storage device (for instance a DRAM or another data memory), a filter, an integrated circuit (such as field-programmable gate array (FPGA), programmable array logic (PAL), generic array logic (GAL) and complex programmable logic devices (CPLDs)), a signal processing component, a power management component (such as a field-effect transistor (FET), metal-oxide-semiconductor field-effect transistor (MOSFET), complementary metal-oxide-semiconductor (CMOS), junction field-effect transistor (JFET), or insulated-gate field-effect transistor (IGFET), all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (GazOs), indium gallium arsenide (InGaAs) and/or any other suitable inorganic compound), an optoelectronic interface element, a light emitting diode, a photocoupler, a voltage converter (for example a DC/DC converter or an AC/DC converter), a cryptographic component, a transmitter and/or receiver, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductance, a battery, a switch, a camera, an antenna, a logic chip, and an energy harvesting unit. However, other components may be surface mounted on the component carrier. For example, a magnetic element can be used as a component. Such a magnetic element may be a permanent magnetic element (such as a ferromagnetic element, an antiferromagnetic element, a multiferroic element or a ferrimagnetic element, for instance a ferrite core) or may be a paramagnetic element. However, the component may also be an IC substrate, an interposer or a further component carrier, for example in a board-in-board configuration. The component may be surface mounted on the component carrier and/or may be embedded therein. Moreover, also other components, in particular those which generate and emit electromagnetic radiation and/or are sensitive with regard to electromagnetic radiation propagating from an environment, may be used as component. In an embodiment, the component carrier is a laminate-type component carrier. In such an embodiment, the component carrier is a compound of multiple layer structures which are stacked and connected together by applying a pressing force and/or heat.

After processing interior layer structures of the component carrier, it is possible to cover (in particular by lamination) one or both opposing main surfaces of the processed layer structures symmetrically or asymmetrically with one or more further electrically insulating layer structures and/or electrically conductive layer structures. In other words, a build-up may be continued until a desired number of layers is obtained.

After having completed formation of a stack of electrically insulating layer structures and electrically conductive layer structures, it is possible to proceed with a surface treatment of the obtained layers structures or component carrier.

In particular, an electrically insulating solder resist may be applied to one or both opposing main surfaces of the layer stack or component carrier in terms of surface treatment. For instance, it is possible to form such a solder resist on an entire main surface and to subsequently pattern the layer of solder resist so as to expose one or more electrically conductive surface portions which shall be used for electrically coupling the component carrier to an electronic periphery. The surface portions of the component carrier remaining covered with solder resist may be efficiently protected against oxidation or corrosion, in particular surface portions containing copper.

It is also possible to apply a surface finish selectively to exposed electrically conductive surface portions of the component carrier in terms of surface treatment. Such a surface finish may be an electrically conductive cover material on exposed electrically conductive layer structures (such as pads, conductive tracks, etc., in particular comprising or consisting of copper) on a surface of a component carrier. If such exposed electrically conductive layer structures are left unprotected, then the exposed electrically conductive component carrier material (in particular copper) might oxidize, making the component carrier less reliable. A surface finish may then be formed for instance as an interface between a surface mounted component and the component carrier. The surface finish has the function to protect the exposed electrically conductive layer structures (in particular copper circuitry) and enable a joining process with one or more components, for instance by soldering. Examples for appropriate materials for a surface finish are Organic Solderability Preservative (OSP), Electroless Nickel Immersion Gold (ENIG), Electroless Nickel Immersion Palladium Immersion Gold (ENIPIG), gold (in particular hard gold), chemical tin, nickel-gold, nickel-palladium, etc.

The aspects defined above and further aspects of the invention are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment.

Figure 1 illustrates a cross-sectional view of a component carrier according to an exemplary embodiment of the invention.

Figure 2 illustrates the component carrier according to Figure 1 without assembled optical chip.

Figure 3 illustrates a cross-sectional view of a component carrier according to another exemplary embodiment of the invention.

Figure 4 illustrates a cross-sectional view of a component carrier according to another exemplary embodiment of the invention.

Figure 5 illustrates a cross-sectional view of the component carrier according to Figure 2 with additional views.

Figure 6 illustrates different views of a component carrier according to another exemplary embodiment of the invention.

Figure 7 illustrates different views of a component carrier according to another exemplary embodiment of the invention.

Figure 8 illustrates different views of a component carrier according to another exemplary embodiment of the invention.

Figure 9 illustrates a plan view of a component carrier before assembling an optical chip according to an embodiment of the invention corresponding to Figure 2.

Figure 10 illustrates a plan view of the component carrier of Figure 9 after assembling an optical chip corresponding to Figure 1.

Figure 11 illustrates a cross-sectional view of a component carrier according to another exemplary embodiment of the invention.

Figure 12 illustrates a cross-sectional view of a component carrier according to another exemplary embodiment of the invention.

Figure 13 illustrates a cross-sectional view of a component carrier according to another exemplary embodiment of the invention.

Figure 14 illustrates a cross-sectional view of a component carrier according to another exemplary embodiment of the invention.

The illustrations in the drawings are schematic. In different drawings, similar or identical elements are provided with the same reference signs.

Before, referring to the drawings, exemplary embodiments will be described in further detail, some basic considerations will be summarized based on which exemplary embodiments of the invention have been developed.

According to an exemplary embodiment of a first aspect, a laminated layer stack-type component carrier (for example a PCB or an IC substrate) comprises an optical layer build-up with optical waveguide function on a stack with wiring structure. The optical waveguide can be optically coupled with an optical chip assembled at the stack (for instance being surface mounted on the stack or embedded in the stack). A double stack with bottom-sided electric functionality and top-sided optical functionality may electrically and optically connect an assembled chip. Advantageously, this may result in short optical and electric paths and consequently in excellent optical and electrical signal integrity.

According to an exemplary embodiment of a second aspect, a (preferably PCB-type or IC substrate-type) component carrier may be equipped with a double cavity having a stepped configuration. Assembling an optical chip in the double cavity may establish both an electric and an optical connection between the electro-optical stack and the optical chip simultaneously. This may lead to a simple manufacturing method and to short signal paths.

According to an exemplary embodiment of a third aspect, a laminated layer stack-type component carrier (for example a PCB or an IC substrate) is implemented with at least two optical chips assembled on and/or in the stack. The optical chips may be optically coupled by a - preferably horizontal - optical layer bridge extending along the stack. Such a manufacturing architecture may allow to obtain a flat component carrier with low space consumption and a reliable and low-loss connection between optical chips. According to an exemplary embodiment of a fourth aspect, a (for instance PCB-type or IC substrate-type) component carrier provides an optical layer build-up on a stack with wiring structure. Said optical layer build-up may be a multilayer structure configured for providing an optical waveguide. One of the optical layers may share a common (preferably horizontal) plane with an electrically conductive layer structure of the stack. This may lead to a flat design, to short optical and electric paths and thus to excellent signal integrity.

Exemplary embodiments of the invention may provide a component carrier-type package with optical waveguide film materials for evanescent coupling between an optical chip and an optical fiber.

An optical chip (such as a photonic integrated circuit, PIC, or a photonic interposer) may be assembled in a double cavity. A first cavity may be configured for establishing electrical interconnects, and a second cavity may be foreseen for creating optical interconnects. Optionally, an edge of the double cavity can be used as alignment marks.

Exemplary embodiments provide advantages: Advantageously, an optical film material may be used for forming additional optical build-up layers on an organic substrate or PCB for optically coupling based on evanescent field coupling. Moreover, component carriers according to exemplary embodiments of the invention may be fully compatible with organic substrate or PCB designs and manufacturing processes. For example, an optical polymer waveguide material can be structured using laser direct imaging (LDI) or nanoimprint lithography (NIL). An achievable accuracy may be so high that it may be possible to form tapered structures in an optical layer build-up to relax mode size mismatch between a silicon on insulator (SOI) waveguide of an optical chip and a polymer waveguide of the optical layer build-up. Further advantageously, evanescent field coupling may be created between optical chip and an optical layer build-up. While edge coupling requires optical chips be diced and polished, evanescent field coupling does not require such a processing. Advantageously, one or more optical input and/or output terminals (for instance using a silicon waveguide) may be provided on the optical chip surface. Furthermore, exemplary embodiments of the invention may allow to relax alignment and manufacturing tolerances compared to edge coupling. Grating coupling show wavelength and polarization dependencies, while evanescent field coupling implemented according to an exemplary embodiment of the invention can reduce wavelength and polarization dependence. Furthermore, one or more additional alignment marks (for instance for alignment during flip chip bonding) may be provided at a cavity edge on top of an optical layer build-up layer. The material of the optical layer build-up may be electrically insulating for preventing shorts with a top sided redistribution layer of the stack.

Exemplary applications of exemplary embodiments of the invention are co-packaged optics and (in particular silicon or InP-based) photonics in data communication and telecommunication applications. This may include the packaging of switches and transceivers for integration in data centers and 5G radio access networks. Moreover, exemplary embodiments of the invention are highly appropriate for automotive applications, like lidar, radar, etc. More generally, exemplary embodiments of the invention may be implemented advantageously for all applications that need high speed data transmission or high data rate transmission. For example, component carriers according to exemplary embodiments of the invention may be employed in data centers. Exemplary embodiments of the invention provide a one package technology for multiple applications, such as data communication and telecommunication. Exemplary applications are transceivers, switches, network interfacing cards in data centers and 5G radio access networks, automotive packages, etc.

Exemplary embodiments of the invention provide a package which includes a component carrier, which may be based on an organic substrate or a PCB composed of a core and build-up layers with additional optical layer buildup layers (in particular cladding and core material) which may be based on optical film material. A double cavity may be formed in the optical layer build-up layers and may be used to electrically and optically interconnect an optical or photonic chip. The optical interconnections to the optical chip may be based on evanescent coupling between a waveguide on the optical chip (for example an SOI- or InP-based waveguide) and a waveguide in the optical layer build-up layers. Thus, cores of the waveguides on the optical chip and of the optical layer build-up layer may be brought in physical contact or close proximity with each other. The optical modes may leak adiabatically from an input core through the cladding into an output waveguide core. To further increase the coupling efficiency, the waveguide can exhibit a tapered structure. The optical chip may be surface mounted on the component carrier. The electric interconnection between the optical chip and the component carrier may be based on solder balls, micro-bumps, copper pillar bumps, etc., allowing a flip chip assembly of the optical chip. The optical chip and the component carrier can both have a redistribution structure (for instance a redistribution layer, RDL) on top. The edge of the cavity and alignment markers on the optical buildfilms can be used to increase alignment accuracy of the optical chip. A cavity on the component carrier build-up layers may be used to attach a fiber connector to the package. The optical signals may be coupled from the fiber connector to the waveguide in the optical layer build-up layers to the waveguide on the optical chip, and vice versa. The optical layer build-up layers may be optically transparent, photosensitive and may comprise an organic material (in particular a polymer, more particularly epoxies, modified acrylates, polysiloxanes or organic-inorganic hybrids). The cladding material surrounds the core material, which carries the optical signals. The cladding and core material of the optical layer build-up layers may differ in refraction index. This difference in the refraction indices may cause total internal reflection at the core-cladding boundary, thus guiding the electromagnetic signals. The optical layer build-up layers can be laminated and structured on the component carrier or fabricated by nanoimprint lithography. The optical layer build-up layers can also have electrically conductive areas on top or between (for instance by vias) the build-up, if desired or required.

Figure 1 illustrates a cross-sectional view of a component carrier 100 according to an exemplary embodiment of the invention. Figure 2 illustrates the component carrier 100 according to Figure 1, however without assembled optical chip 112.

The illustrated component carrier 100 (such as a printed circuit board or an integrated circuit substrate) comprises an optical chip 112 mounted by a connection structure 160 (such as solder bumps) on a layer stack 102. Additionally or alternatively to the surface mounted optical chip 112, it is also possible to embed one or more components in the stack 102 (not shown). In the shown embodiment, the optical chip 112 (which may be for example a photonic chip or a photonic interposer) comprises at its bottom side a plurality of electrically conductive chip pads 162 for establishing an electric connection, by the connection structure 160, with electrically conductive stack pads 164 at a top side of the layer stack 102. Furthermore, the optical chip 112 may comprise one or more chip waveguides 166 (which may be manufactured for example in SOI-technology or InP-technology) for establishing an optical connection with a stack waveguide 110 of an optical layer build-up 108 described below in further detail. More specifically, optical signals may be transmitted from stack waveguide 110 to chip waveguide 166 or from chip waveguide 166 to stack waveguide 110. Said optical coupling may be preferably accomplished by evanescent coupling by forming a direct physical connection or close spatial vicinity between chip waveguide 166 and stack waveguide 110.

For example, optical chip 112 may convert a received optical signal into an electrical signal, and/or may convert an electrical signal into an optical signal to be transmitted. Such an optical chip 112 may comprise for example one or more photodiodes, a multiplexer, a processor, etc.

As already mentioned, the component carrier 100 comprises a laminated layer stack 102 comprising a plurality of electrically conductive layer structures 104 and of electrically insulating layer structures 106. The electrically conductive layer structures 104 may comprise patterned copper layers which may form horizontal pads and/or a horizontal wiring structure. The electrically conductive layer structures 104 may also form the above-mentioned stack pads 164. Additionally or alternatively, the electrically conductive layer structures 104 may comprise vertical through connections such as copper pillars and/or copper filled laser vias. Moreover, the stack 102 of the component carrier 100 may comprise one or more electrically insulating layer structures 106 (such as prepreg sheets, resin sheets or a core made of FR4). Also surface finish (like ENIG or ENEPIG, a solder resist, etc.) may be optionally applied on the top side and/or on the bottom side of the stack 102 (not shown).

In the shown embodiment, the stack 102 comprises a central core 176 (which may be made of fully cured material such as FR4 material, or glass) having organic build-up structures 178, 180 on both opposing main surfaces thereof. Each organic build-up structure 178, 180 may comprise for instance organic resin layers, optionally comprising reinforcing structures. For example, central core 176 may also act as optical cladding material (i.e. may fulfill the function of below described waveguide cladding layer 124), in particular when an optical chip 112 is embedded in central core 176 (see for example Figure 14).

Furthermore, wiring structures of copper may be formed inside of the organic build-up structures 178, 180, and for example also in central core 176 (not shown in Figure 1). However, also coreless configurations of stack 102 are possible in other embodiments.

Moreover, component carrier 100 comprises an optical layer build-up 108 on the stack 102 which forms an optical stack waveguide 110. The optical layer build-up 108 comprises a stacked optical planar layer sequence comprising an at least partially optically transparent central waveguide core layer 130 sandwiched between two waveguide cladding layers 124, 134, one on the top side and one on the bottom side of the waveguide core layer 130. For example, the waveguide cladding layers 124, 134 and the waveguide core layer 130 may be made of different organic polymer materials. The materials of the waveguide core layer 130 on the one hand and of the waveguide cladding layers 124, 134 on the other hand may have different values of the refraction index, so that a light signal propagating in the waveguide core layer 130 may be totally internally reflected (or at least reflected predominantly) at an interface to the waveguide cladding layers 124, 134. As a result, light may be guided in the waveguide core layer 130 without propagating predominantly into the waveguide cladding layers 124, 134. Moreover, the waveguide cladding layers 124, 134 and/or the waveguide core layer 130 may have electrically insulating properties in order to suppress and/or prevent electric shorts between the electrically conductive layer structures 104 of the stack 102. Additionally, an adhesion promoting layer (not shown) may be located between the stack 102 and the optical layer build-up 108.

As shown, the optical chip 112 is electrically and mechanically coupled to the stack 102 and is optically coupled with the optical stack waveguide 110. Now referring additionally to Figure 2, said electric and optical coupling of optical chip 112 is accomplished by a double cavity 114 formed as a stepped through hole in optical stack waveguide 110. The double cavity 114 extends up to an upper main surface of stack 102 so that stack pads 164 are exposed by the double cavity 114 at a lower end thereof. As shown, the double cavity 114 is formed by a top-sided first cavity 116 being arranged in a stepped configuration with a bottom-sided second cavity 118. As shown as well, a horizontal surface of the first cavity 116 is defined by a locally exposed waveguide core layer 130 of the optical layer build-up 108. Furthermore, a horizontal surface of the second cavity 118 is defined by the exposed uppermost electrically conductive layer structure 104 and its stack pads 164. Each of the first cavity 116 and the second cavity 118 may be formed by a cylindrical or rectangular recess. The first cavity 116 may be shaped and dimensioned for accommodating a bottom portion of the optical chip 112, as shown in Figure 1. The second cavity 118 may be shaped and dimensioned for accommodating the connection structure 160 and the chip pads 162 as well as the stack pads 164 when the bottom portion of the optical chip 112 is accommodated in the first cavity 116. Empty gaps in the second cavity 118 which are not filled by the pads 162, 164 and the connection structure 160 may be filled partially or entirely by an underfill 168. Still referring to Figure 2, first cavity 116 and second cavity 118 may be arranged coaxially, as indicated by a common symmetry axis 170. The first cavity 116 may have a larger horizontal diameter than the second cavity 118. In the shown embodiment, the first cavity 116 is shallower than the second cavity 118. A central portion of the first cavity 116 and the entire second cavity 118 may be formed by a vertical through hole extending through the entire optical layer build-up 108. A peripheral portion of the first cavity 116 may be created by removing only part of a top-sided waveguide cladding layer 134 of the optical layer build-up 108, while maintaining the exposed portion of the central waveguide core layer 130 intact.

Now referring again to Figure 1, only a bottom portion of the optical chip 112 is arranged in the double cavity 114, whereas an upper portion of the optical chip 112 protrudes beyond the optical layer build-up 108. The designs of the optical chip 112 and of the double cavity 114 are adapted to each other so that the first cavity 116 provides an optical connection and the second cavity 118 provides an electric connection of the optical chip 112.

Optionally, the optical chip 112 may be in direct contact with the waveguide cladding layer 134 via its side walls. A further option is that there may be an empty space between the side wall of the optical chip 112 and the waveguide cladding layer 134. Further additionally, on top of the optical layer build-up 108 and/or the optical chip 112, there may be a mold material. This may prevent mechanical damage and/or signal loss through light interferences.

More specifically, assembling the bottom portion of the optical chip 112 in the double cavity 114 may lead to an electric coupling of the stack pads 164 with the chip pads 162 by the connection structure 160. The connection structure 160 may be previously attached to the stack pads 164 and/or to the chip pads 162. The electric connection can be rendered permanent by carrying out a solder process (or alternatively a sinter process or a gluing process). Simultaneously with the formation of the electric connection between the chip pads 162 of the optical chip 112 and the stack pads 164 of stack 102, assembly of the optical chip 112 in the double cavity 114 establishes an optical coupling between one or more chip waveguide 166 at a peripheral portion bottom surface of the optical chip 112 and the exposed waveguide core layer 130 of stack waveguide 110. Advantageously, the aforementioned optical coupling between optical layer build-up 108 and optical chip 112 may be accomplished by evanescent coupling, as indicated by reference sign 172.

The optical layer build-up 108, being mechanically and optically coupled with the optical chip 112, can be formed directly on the stack 102 and may constitute the optical stack waveguide 110. The latter has an optical waveguide layer 124, more specifically the lower waveguide cladding layer directly beneath the waveguide core layer 130, which has a bottom main surface arranged at the same vertical level as a top main surface of the uppermost of the electrically conductive layer structures 104 of the stack 102. This coplanarity of the top side of the uppermost electrically conductive layer structure 104 and the bottom side of waveguide cladding layer 124 is indicated by a horizontal line 174 in Figure 1.

As already mentioned, the optical layer build-up 108 is formed on the stack 102 and constitutes a layer-type optical stack waveguide 110 which is optically coupled with the integrated chip waveguide 166 at the bottom main surface of the optical chip 112. Advantageously, the optical chip 112 and the optical waveguide 110 are optically coupled by evanescent coupling.

Furthermore, Figure 1 shows a fiber connector 126 arranged in a further cavity 144 formed partially in the stack 102 and partially in the optical layer build-up 108. The fiber connector 126 inserted partially in cavity 144 is connected mechanically with the optical waveguide 110 and optically with the waveguide core layer 130 thereof for establishing an optical connection with an optical fiber 128 arranged externally from the stack 102 and from the optical layer build-up 108. An optical signal may be coupled from the optical fiber 128 via the fiber connector 126 into the stack waveguide 110 and from there in the chip waveguide 166 of the optical chip 112. However, it may be also possible, additionally or alternatively, that an optical signal is coupled from the chip waveguide 166 of the optical chip 112 into the stack waveguide 110 and from there to the fiber connector 126 and into the optical fiber 128.

As can be taken from Figure 2, one or more alignment marks 136 may be formed on top of the optical layer build-up 108. Thus, alignment marks 136 may be formed at a cavity edge of the optical layer build-up 108. This may simplify assembly of optical chip 112, for instance in a flip chip configuration.

Concluding, the embodiment of Figure 1 and Figure 2 shows a packagetype component carrier 100 with optical waveguide build-up layers (see reference signs 124, 130, 134) for evanescent coupling between a PIC-type optical chip 112 and the fiber 128. The optical layer build-up layers (made of cladding and core material) of optical layer build-up 108 may be based on organic material (in particular based on a polymer film) in which double cavity 114 may be formed. To put it shortly, the first cavity 116 is configured for providing optical interconnects, i.e. for optically coupling the waveguide core layer 130 of the optical layer build-up 108 to a core of chip waveguide 166 which may be integrated in the optical chip 112. Moreover, the second cavity 118 serves for creating electrical interconnects by connection structure 160 (for example solder balls, micro-bumps, copper pillar bumps, etc.) for flip chip assembly of the optical chip 112. Thus, double cavity 114 in material of the optical layer buildup 108 may function for assembling the optical chip 112. Apart from this, a further cavity 144 is formed for accommodating the fiber connector 126. Cavities 116, 118, 144 contribute to a compact design of component carrier 100.

Cores of the integrated chip waveguide 166 of the optical chip 112 (which may be for example SOI or InP-based) and polymer stack waveguide 110 made of material of optical layer build-up 108 may be brought into direct physical contact or in close spatial proximity for accomplishing an optical coupling by evanescent coupling.

Summarizing, the embodiment of Figure 1 provides a package-type component carrier 100 with optical waveguide film material for forming optically build-up 108 for accomplishing evanescent coupling between the optical chip 112 and an outside of component carrier 100. The build-up layers (i.e. cladding and core material) of the layers 124, 130, 134 may be based on optical dry film material.

Figure 3 illustrates a cross-sectional view of a component carrier 100 according to another exemplary embodiment of the invention.

The embodiment of Figure 3 differs from the embodiment of Figure 1 in particular in that, according to Figure 3, the illustrated component carrier 100 comprises a first optical chip 112 and a second optical chip 120 both being assembled to the stack 102. More specifically, optical chips 112, 120 may both be surface mounted on top of the component carrier 100. Furthermore, an optical layer bridge 122 formed on the laminated layer stack 102 provides an optical connection of the first optical chip 112 with the second optical chip 120. In another embodiment, it is also possible that an optical layer bridge 122 optically couples more than two optical chips with each other. As shown, optical layer bridge 122 comprises an optical layer build-up 108 forming an optical stack waveguide 110.

To put it shortly, each optical chip 112, 120 of Figure 3 is electrically coupled with the uppermost electrically conductive layer structure 104 of stack 102, and consequently to the stack pads 164, by respective chip pads 162 and respective connection structures 160, as described above referring to Figure 1. Furthermore, the chip waveguides 166 at a bottom side of each optical chip 112, 120 of Figure 3 are optically coupled by evanescent coupling with an exposed portion of waveguide core layer 130 of the optical layer build-up 108, as described above referring to Figure 1. According to Figure 3, the optical layer build-up 108 is patterned so as to form two double cavities 154, 155 which may have the properties of double cavity 114 described above referring to Figure 1 and Figure 2. A central portion of the patterned optical layer build-up 108 of Figure 3 constitutes an optical layer bridge 122 which has two exposed portions of its waveguide core layer 130. One of said exposed portions is optically coupled with chip waveguide 166 of optical chip 112, whereas the other exposed portion is optically coupled with chip waveguide 166 of optical chip 120. This establishes a mutual optical coupling between the optical chips 112, 120.

More specifically, double cavity 154 is formed in the optical layer buildup 108 and above the stack 102 for establishing an optical connection of the optical chip 112 and for establishing an electric connection of the optical chip 112. Correspondingly, further double cavity 155 in the same optical layer build-up 108 and above the stack 102 serves for establishing an optical connection of further optical chip 120 and for establishing an electric connection of the further optical chip 120.

Hence, the embodiment of Figure 3 illustrates how two optical chips 112, 120, each for example embodied as photonic integrated circuit or photonic interposer, can be coupled optically along a purely horizontal optical connection path. This short optical path leads to an excellent optical signal integrity.

Figure 4 illustrates a cross-sectional view of a component carrier 100 according to another exemplary embodiment of the invention.

The embodiment of Figure 4 differs from the embodiment of Figure 3 in particular in that, according to Figure 4, the further optical chip 120 is substituted by an electric chip 142 assembled to the stack 102 and being electrically coupled with the optical chip 112. For example, the electric chip 142 may comprise a driver for driving the optical chip 112, a transimpedance amplifier (TIA), an application specific integrated circuit (ASIC), etc. The electric chip 142 is surface mounted on the stack 102 by connection structure 160, stack pads 164 and chip pads 162. The optical layer build-up 108 is absent in a region where the electric chip 142 is assembled.

For establishing the electric connection between the optical chip 112 and the electric chip 142, a purely horizontal electric connection trace 146 is provided which is arranged at a main surface of the stack 102 and electrically couples the electric chip 142 with the optical chip 112. Thus, a very short electric signal path can be established between electric chip 142 and optical chip 112. The optical connection of the optical chip 112 in Figure 4 may be the same as described above referring to Figure 1. According to Figure 4, Very Short Reach (VSR) or Extra Short Reach (XSR) interconnects may be possible. Preferably, the electric chip 142 may not be in direct contact with the optical layer build-up 108.

Figure 5 illustrates a cross-sectional view of the component carrier 100 according to Figure 2 with additional views. More specifically, Figure 5 shows a top view 182 of optical layer build-up 108 along a viewing direction 184. Furthermore, Figure 5 illustrates a cross-sectional view 186 of optical layer build-up 108 along a cutting plane 188.

The above-mentioned alignment marks 136 formed at the optical layer build-up 108 are visible in the top view 182.

Furthermore, both the top view 182 and the cross-sectional view 186 show that the waveguide core layer 130 of the optical layer build-up 108 comprises a plurality of optical coupling channels 140 extending parallel to each other. The optical coupling channels 140 are spaced by optically inactive spacer sections 138. The optical coupling channels 140 and the inactive spacer sections 138 may be made of different materials having different refraction indices so that light propagating along an optical coupling channel 140 may be totally internally reflected (or may be at least reflected predominantly) at the interface to an adjacent inactive spacer section 138. Preferably, the inactive spacer sections 138 may have similar and/or identical dimensions, in particular in two dimensions. Thus, a plurality of optical signals may be transmitted simultaneously with such a configuration. In one example, a plurality of optical signals may be simultaneously transmitted having one wavelength. In another example, a plurality of optical signals may be simultaneously transmitted having at least two wavelengths.

Figure 6 illustrates different views of a component carrier 100 according to another exemplary embodiment of the invention. In addition to the illustration of Figure 5, Figure 6 shows chip waveguides 166 at a bottom side of an optical chip 112 (not shown in Figure 6). Hence, Figure 6 illustrates that the chip waveguides 166 and the optical coupling channels 140 of the optical layer build-up 108 with its layer waveguide 110 can be properly aligned. This means that the chip waveguides 166 and the optical coupling channels 140 are mutually located so that optical signals can be reliably transmitted between chip waveguides 166 and optical coupling channels 140. This is also illustrated in a detail 190 in Figure 6.

Figure 7 illustrates different views of a component carrier 100 according to another exemplary embodiment of the invention.

The embodiment of Figure 7 differs from the embodiment of Figure 5 in particular in that, according to Figure 7, the optical coupling channels 140 have a tapering shape. The narrow ends of the tapering optical coupling channels 140 face the optical chip 112 (not shown in Figure 7) when assembled, whereas the broad ends of the tapering optical coupling channels 140 face away from the optical chip 112. This promotes proper optical coupling of light between the optical coupling channels 140 and the miniature chip waveguides 166 at a bottom side of the respective optical chip 112.

Figure 8 illustrates different views of a component carrier 100 according to another exemplary embodiment of the invention.

In addition to Figure 7, Figure 8 illustrates a tapered polymer waveguide structure for better mode size match to a silicon-based chip waveguide 166 of optical chip 112. Hence, Figure 8 illustrates that tapering chip waveguides 166 and inverse tapering optical coupling channels 140 of the optical layer build-up 108 with its layer waveguide 110 can be properly aligned. This is also illustrated in a detail 192 in Figure 8. In Figure 8, the tapering directions of the tapering chip waveguides 166 and the tapering optical coupling channels 140 are inverse or antiparallel to each other.

Figure 9 illustrates a plan view of a component carrier 100 before assembling an optical chip 112 according to an embodiment of the invention corresponding to Figure 2. Figure 10 illustrates a plan view of the component carrier 100 of Figure 9 after assembling the optical chip 112 corresponding to Figure 1. Shown are optical interconnects, electrical interconnects and an additional cavity 144 at the stack 102 (which may be formed by IC substrate or PCB build-up layers) and at the optical layer build-up 108 for attachment of the fiber connector 126.

Optionally, thermal management structures for dissipating heat, electromagnetic shielding structures for shielding electromagnetic radiation, and/or barrier layers for protection purposes (for instance against corrosion and/or oxidation) may be foreseen in each embodiment. Figure 11 illustrates a cross-sectional view of a component carrier 100 according to another exemplary embodiment of the invention comprising two embedded optical chips 112, 120.

The latter may generate a considerable amount of heat during operation of the component carrier 100. In order to remove such heat from the component carrier 100 for ensuring a high performance and reliability thereof, component carrier 100 according to Figure 11 is equipped with highly thermally conductive blocks 148 being thermally coupled with the optical chips 112, 120. The highly thermally conductive blocks 148 may be copper blocks having a very high thermal conductivity. The highly thermally conductive block 148 beneath optical chip 112 is in direct physical contact with a full main surface of said optical chip 112. The other highly thermally conductive block 148 beneath optical chip 120 is thermally and mechanically connected to the bottom main surface of said optical chip 120 by a plurality of thermal vias 150. Said thermal vias 150 may be metallized vias, such as copper filled laser vias. In view of the described construction, heat can be efficiently dissipated from the optical chips 112, 120 via the assigned highly thermally conductive block 148 to the bottom side of the component carrier 100. On the top side of the optical chips 112, 120, the optical chips 112, 120 are optically coupled with each other by optical layer bridge 122, as described above.

The connection sides of the optical chips 112, 120 are flipped upside down in Figure 11 in comparison with the previously described embodiments. Thus, the chip waveguide 166 is located in the top main surface of the respective optical chip 112, 120 and the respective waveguide core layer 130 is exposed on the bottom side of the optical waveguide 110 in order to optically connect both constituents. Furthermore, the optical chips 112, 120 are embedded in the stack 102 in Figure 11, and the optical build-up layer 108 is protruding.

As shown, the highly thermally conductive blocks 148 and the optical chips 112, 120 are pairwise vertically stacked and extend through the entire stack 102. According to Figure 11, the optical chips 112, 120 are embedded in substrate-type or PCB-type laminated layer stack 102. The illustrated thermal management architecture is based on the highly thermally conductive blocks 148 on the bottom or back side, whereas the signal paths of the optical chips 112, 120 are formed on the top or front side.

As shown, an optional solder resist 196 may be formed only on those surface portions of the component carrier 100 where the optical layer build-up 108 is absent, since the optical layer build-up 108 may also provide a protection against solder, oxidation and corrosion. It is also possible that the solder resist 196 is substituted by the lowermost waveguide cladding layer 124.

Reference sign 191 in Figure 11 shows an electrical interface with electrical fanout or redistribution layer functionality for an electric coupling with the electrically conductive layer structures 104 of stack 102. Reference sign 193 in Figure 11 shows an optical redistribution layer for an optical coupling between the optical chips 112, 120. Reference sign 195 in Figure 11 shows an electrical redistribution layer on top of the optical chip 112.

Hence, the embodiment of Figure 11 illustrates that optical build-up layers can be structured like electrical build-up layers. What concerns the electrical interface, an electrical fanout may be accomplished by a redistribution layer (RDL) to stack 102. In addition, an optical RDL may be formed between the optically connected optical chips 112, 120, for instance as part of optical layer bridge 122. For example, the optical RDL may be formed inside the optical build-up layerl08. An electric RDL may be formed on an optical chip 112, 120. Thermal management is accomplished by the embedded highly thermally conductive blocks 148, which may be made of a metal such as copper or of a ceramic such as aluminum nitride.

Figure 12 illustrates a cross-sectional view of a component carrier 100 according to another exemplary embodiment of the invention.

The embodiment of Figure 12 differs from the embodiment of Figure 11 in particular in that, according to Figure 12, only one optical chip 112 is foreseen. Additionally, an electric chip 142 is provided which is stacked with the highly thermally conductive block 148 and with the optical chip 112 so that the optical chip 112 is arranged vertically in between the electric chip 142 and the highly thermally conductive block 148. The optical chip 112 and the electric chip 142 are electrically connected with each other by chip pads 162 and connection structure 160. The optical chip 112 is optically coupled with fiber con- nector 126 as described above referring to Figure 1, wherein in Figure 12 optical chip 112 is embedded in stack 102. Since the optical chip 112 is embedded in the stack 102, thermal management by heat dissipation is accomplished via highly thermally conductive block 148 on the back side. A signal path is provided on the opposing front side of the optical chip 112. Electric chip 142, which may be an ASIC, is surface mounted on the optical chip 112.

Figure 13 illustrates a cross-sectional view of a component carrier 100 according to another exemplary embodiment of the invention.

The embodiment of Figure 13 differs from the embodiment of Figure 12 in particular in that, according to Figure 13, the electric chip 142 is assembled on the stack 102 laterally displaced with respect to the highly thermally conductive block 148 and with respect to the optical chip 112. The optical chip 112 is electrically coupled with the electric chip 142 by an electrically conductive layer structure 104 forming a horizontal electric connection trace 146 on an upper main surface of stack 102. The horizontal electric connection trace 146 may provide also an electrical fanout or redistribution layer functionality for an electrical coupling with the electrically conductive layer structures 104 of stack 102 and/or with the electric chip 142.

Thus, the optical chip 112 is embedded in the stack 102, allowing for a thermal management by highly thermally conductive block 148 on the back. A signal path is formed on the front side. An electrical connection between optical chip 112 and electric chip 142 is accomplished via direct fan-out.

Figure 14 illustrates a cross-sectional view of a component carrier 100 according to another exemplary embodiment of the invention.

The embodiment of Figure 14 differs from the embodiment of Figure 13 in particular in that, according to Figure 14, three electric chips 142 are assembled on an upper layer stack 102 and two optical chips 112 are embedded in optical layer build-up 108 beneath said upper layer stack 102. Furthermore, a lower layer stack 102 is arranged beneath the optical layer build-up 108. In other words, the optical layer build-up 108 is sandwiched between the upper layer stack 102 and the lower layer stack 102. Each of stacks 102 may comprise a plurality of electrically conductive layer structures 104 and a plurality of electrically insulating layer structures 106, for instance as described above referring to Figure 1. The optical layer build-up 108 comprises a plurality of stacked optical layer structures (here embodied for example as central waveguide core layer 130 and two peripheral waveguide cladding layers 124, 134) and comprises a plurality of electrically conductive layer structures 104. A person skilled in the art will understand that this is a general principle which can be applied in any embodiment. Hence, the optical layer structures of the optical layer build-up 108 can be structured like electrical build-up layers of stacks 102.

In the shown embodiment, the optical chips 112 are embedded in a core of an optical substrate or optical PCB, and a core of the optical substrate or PCB may act as optical cladding layer.

As shown, filler material 199 may fill gaps between the respective optical chip 112 and the optical layer build-up 108. For example, the filler material 199 may be the same material as for the dielectric build-up in the stacks 102, may be the same material as for the waveguide cladding layers 124, 134, and/or may be another epoxy material.

The optical chips 112 may be optically coupled with each other by optical bridge 122. Any of the optical chips 112 may also be optically coupled, for instance with fiber connector 126, by optical waveguide 110 formed by the optical layer build-up 108. The electric chips 142 may be electrically coupled with each other by electrically conductive layer structures 104. The electric chips 142 and the optical chips 112 may be coupled with each other by electrically conductive layer structures 104. For instance, the central electric chip 142 may be an ASIC, whereas the two peripheral electric chips 142 may be drivers and/or TIAs. For example, the optical chips 112 may be photonic ICs and/or photonic interposers. In addition, one or more passive components 194 (such as capacitance components or inductor components) may be surface mounted on the upper stack 102.

It should be noted that the term "comprising" does not exclude other elements or steps and the "a" or "an" does not exclude a plurality. Also, elements described in association with different embodiments may be combined.

It should also be noted that reference signs in the claims shall not be construed as limiting the scope of the claims. Implementation of the invention is not limited to the preferred embodiments shown in the figures and described above. Instead, a multiplicity of variants is possible which use the solutions shown and the principle according to the invention even in the case of fundamentally different embodiments.

Claims

Claims:

1. A component carrier (100), which comprises: a stack (102, 108) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106); a double cavity (114) formed in, on and/or above the stack (102, 108) and comprising a first cavity (116) being arranged in a stepped configuration with a second cavity (118); and an optical chip (112) arranged at least partially in the double cavity (114) so that the first cavity (116) provides an optical connection and the second cavity (118) provides an electric connection of the optical chip (112).

2. A component carrier (100), which comprises: a stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106); an optical layer build-up (108) on the stack (102) forming an optical waveguide (110); and an optical chip (112) coupled to the stack (102) and optically coupled with the optical waveguide (110).

3. A component carrier (100), which comprises: a stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106); a first optical chip (112) assembled to the stack (102); a second optical chip (120) assembled to the stack (102); and an optical layer bridge (122) formed on and/or in the stack (102) and providing an optical connection of the first optical chip (112) with the second optical chip (120).

4. A component carrier (100), which comprises: a stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106); and an optical layer build-up (108), in particular coupled with an optical chip (112), arranged on the stack (102) and forming an optical waveguide (110) which has an optical waveguide layer (124) arranged at the same vertical level as one of the at least one electrically conductive layer structure (104) of the stack (102).

5. The component carrier (100) according to any of claims 1 to 4, wherein an optical layer build-up (108) is arranged on the stack (102) and forms an optical waveguide (110) which is optically coupled with the optical chip (112).

6. The component carrier (100) according to claim 2 or 5, comprising at least one of the following features: wherein the optical chip (112) and the optical waveguide (110) are optically coupled by evanescent coupling; wherein the optical chip (112) and the optical waveguide (110) are optically coupled with each other by optically coupling, on the one hand, a chip waveguide (166) formed as part of the optical chip (112) on a main surface of the optical chip (112), and, on the other hand, a waveguide core layer (130) of the optical layer build-up (108).

7. The component carrier (100) according to claim 2, 5 or 6, comprising a fiber connector (126) arranged on and/or in the stack (102) and being connected with the optical waveguide (110) for establishing an optical connection with an optical fiber (128).

8. The component carrier (100) according to claim 7, wherein the fiber connector (126) is arranged in a cavity (144) formed in the stack (102) and/or in the optical layer build-up (108).

9. The component carrier (100) according to any of claims 2 or 5 to 8, wherein the optical layer build-up (108) comprises a stacked optical layer sequence comprising a waveguide core layer (130) between two waveguide cladding layers (124, 134).

10. The component carrier (100) according to any of claims 2 or 5 to 9, wherein a waveguide core layer (130) of the optical layer build-up (108) comprises a plurality of optical coupling channels (140).

11. The component carrier (100) according to claim 10, wherein the optical coupling channels (140) extend parallel to each other.

12. The component carrier (100) according to claim 10 or 11, wherein at least part of the optical coupling channels (140) have an at least partially tapering shape.

13. The component carrier (100) according to any of claims 10 to 12, wherein the optical coupling channels (140) are spaced by optically inactive spacer sections (138).

14. The component carrier (100) according to any of claims 2 or 5 to 13, wherein the optical layer build-up (108) is formed based on an organic polymer film material.

15. The component carrier (100) according to any of claims 2 or 5 to 14, comprising a double cavity (114) in the optical layer build-up (108), in particular extending vertically through the entire optical layer build-up (108).

16. The component carrier (100) according to claim 15, wherein the double cavity (114) comprises a first cavity (116) establishing an optical connection of the optical chip (112), arranged at least partially in the double cavity (114), with the optical layer build-up (108), and comprises a second cavity (118) establishing an electric connection of the optical chip (112) with the stack (102).

17. The component carrier (100) according to claim 15 or 16, wherein the first cavity (116) and the second cavity (118) form a stepped configuration.

18. The component carrier (100) according to any of claims 2 or 3 to 17, comprising a double cavity (114) formed in, on and/or above the stack (102) and comprising a first cavity (116) being arranged in a stepped configuration with a second cavity (118); wherein the optical chip (112) is arranged at least partially in the double cavity (114) so that the first cavity (116) provides an optical connection and the second cavity (118) provides an electric connection of the optical chip (112).

19. The component carrier (100) according to claim 1 or 18, wherein the double cavity (114) is formed in an optical layer build-up (108) formed on the stack (102).

20. The component carrier (100) according to claim 19, wherein a horizontal surface of the first cavity (116) is defined at least partially by a waveguide core layer (130) of the optical layer build-up (108), and/or a horizontal surface of the second cavity (118) is defined at least partially by at least one of the at least one electrically conductive layer structure (104), wherein in particular an optical coupling is established between the waveguide core layer (130) and a chip waveguide (166) formed at a bottom main surface of the optical chip (112) and/or an electrical coupling is established between stack pads (164) of the at least one of the at least one electrically conductive layer structure (104) on the horizontal surface of the second cavity (118) and chip pads (162) formed at the bottom main surface of the optical chip (112).

21. The component carrier (100) according to any of claims 1, 2 or 4 to 20, comprising: a second optical chip (120) assembled to the stack (102); and an optical layer bridge (122) formed on and/or in the stack (102) and providing an optical connection of the optical chip (112) with the second optical chip (120).

22. The component carrier (100) according to claim 3 or 21, wherein the optical layer bridge (122) comprises an optical layer build-up (108) forming an optical waveguide (110), wherein in particular an optical coupling is established between a waveguide core layer (130) of the optical layer build-up (108) and a chip waveguide (166) formed at a bottom main surface of the first optical chip (112) and/or of the second optical chip (120).

23. The component carrier (100) according to any of claims 1 to 3 or 5 to 22, wherein an optical layer build-up (108) arranged on the stack (102) and forming an optical waveguide (110) has an optical waveguide layer (124) arranged at the same vertical level as one of the at least one electrically conductive layer structure (104).

24. The component carrier (100) according to claim 4 or 23, comprising an optical chip (112) assembled to the stack (102), being optically coupled with the optical waveguide (110) and being electrically coupled with the at least one electrically conductive layer structure (104).

25. The component carrier (100) according to any of claims 2 or 4, comprising a cavity (154), in particular a double cavity with stepped configuration, in the optical layer build-up (108) and on or above the stack (102) for establishing an optical connection of the optical chip (112) and for establishing an electric connection of the optical chip (112).

26. The component carrier (100) according to claim 25, comprising a further cavity (155), in particular a double cavity with stepped configuration, in the same optical layer build-up (108) and on or above the stack (102) for establishing an optical connection of a further optical chip (120) and establishing an electric connection of the further optical chip (120).

27. The component carrier (100) according to any of claims 1 to 26, comprising an electric chip (142) assembled to the stack (102) and being electrically coupled with the optical chip (112).

28. The component carrier (100) according to claim 27, comprising a horizontal electric connection trace (146) arranged at a main surface of the stack (102) and electrically coupling the electric chip (142) with the optical chip (112).

29. The component carrier (100) according to any of claims 1 to 28, wherein a central portion of one main surface of the optical chip (112) has an electric interface, in particular chip pads (162), and a peripheral portion of said main surface of the optical chip (112) has an optical interface, in particular a chip waveguide (166) integrated with the optical chip (112).

30. The component carrier (100) according to any of claims 1 to 29, comprising a highly thermally conductive block (148) being thermally coupled with the optical chip (112).

31. The component carrier (100) according to claim 30, wherein the highly thermally conductive block (148) is in direct contact with or is connected by a plurality of thermal vias (150) with the optical chip (112).

32. The component carrier (100) according to claim 30 or 31, wherein the highly thermally conductive block (148) and the optical chip (112) are stacked and extend through the entire stack (102).

33. The component carrier (100) according to claim 32, comprising an electric chip (142) being stacked with the highly thermally conductive block (148) and with the optical chip (112), wherein the optical chip (112) is arranged vertically in between the electric chip (142) and the highly thermally conductive block (148).

34. The component carrier (100) according to claim 32, comprising an electric chip (142) being assembled on the stack (102) laterally displaced with respect to the highly thermally conductive block (148) and with respect to the optical chip (112), wherein the optical chip (112) is electrically coupled with the electric chip (142) by the at least one electrically conductive layer structure (104).

35. The component carrier (100) according to any of claims 2 or 4, comprising at least one alignment mark (136) formed at the optical layer build-up (108).

36. A method of manufacturing a component carrier (100), wherein the method comprises: providing a stack (102, 108) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106); forming a double cavity (114) in, on and/or above the stack (102, 108) comprising a first cavity (116) being arranged in a stepped configuration with a second cavity (118); and assembling an optical chip (112) at least partially in the double cavity (114) so that the first cavity (116) provides an optical connection and the second cavity (118) provides an electric connection of the optical chip (112).

37. A method of manufacturing a component carrier (100), wherein the method comprises: providing a stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106); forming an optical layer build-up (108) on the stack (102) to thereby form an optical waveguide (110); and optically coupling an optical chip (112) with the optical waveguide (110) and coupling the optical chip (112) to the stack (102).

38. A method of manufacturing a component carrier (100), wherein the method comprises: providing a stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106); assembling a first optical chip (112) to the stack (102); assembling a second optical chip (120) to the stack (102); and optically connecting the first optical chip (112) with the second optical chip (120) by an optical layer bridge (122) formed on and/or in the stack (102).

39. A method of manufacturing a component carrier (100), wherein the method comprises: providing a stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106); and arranging an optical layer build-up (108) on the stack (102) for forming an optical waveguide (110) which has an optical waveguide layer (124) arranged at the same vertical level as one of the at least one electrically conductive layer structure (104).