Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
  • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
  • H03F1/0216—Continuous control
  • H03F1/0222—Continuous control by using a signal derived from the input signal
  • H03F1/0227—Continuous control by using a signal derived from the input signal using supply converters
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
  • H03F1/14—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of neutralising means
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
  • H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
  • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
  • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
  • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
  • H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
  • H03F3/45098—PI types
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/534—Transformer coupled at the input of an amplifier
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/537—A transformer being used as coupling element between two amplifying stages
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/541—Transformer coupled at the output of an amplifier

Definitions

• the technology of the disclosure relates generally to neutralizing memory distortion in a differential power amplifier circuit.
• Mobile communication devices have become increasingly common in current society for providing wireless communication services.
• the prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices.
• Increased processing capability in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.
• a transmission circuit typically amplifies a radio frequency (RF) signal to a higher power before transmission.
• RF radio frequency
• a transceiver circuit is configured to generate the RF signal
• a power management circuit is configured to generate a modulated voltage
• a power amplifier circuit is configured to amplify the RF signal based on the modulated voltage
• an antenna circuit is configured to radiate the RF signal in one or more RF frequencies.
• the RF signal transmitted in the 5G and 5G-NR systems is subject to stringent adjacent channel leakage ratio (ACLR) requirements imposed by standard bodies and/or regulatory authorities.
• the ACLR defines a ratio between a power of the RF signal transmitted on an intended radio channel and the power of the RF signal received in an unintended adjacent radio channel.
• a remodulation term(s) such as a third order intermodulation product (IMD3)
• IMD3 third order intermodulation product
• Embodiments of the disclosure relate to memory distortion neutralization in a differential power amplifier circuit.
• the differential power amplifier circuit includes a pair of differential amplifiers each configured to amplify a radio frequency (RF) signal based on a modulated voltage.
• a neutralization circuit is configured to inject a neutralization current into each of the differential amplifiers to thereby neutralize a modulated leakage current that causes an unwanted memory distortion to degrade an adjacent channel leakage ratio (ACLR) of the differential power amplifier circuit.
• ACLR adjacent channel leakage ratio
• a differential power amplifier circuit includes an output stage.
• the output stage includes a collector node.
• the collector node is coupled to a power management integrated circuit (PMIC) to receive a modulated voltage.
• PMIC power management integrated circuit
• the output stage also includes an interstage transformer.
• the interstage transformer is configured to receive an RF signal.
• the output stage also includes a pair of differential amplifiers. Each differential amplifier in the pair of differential amplifiers is coupled to the interstage transformer and configured to amplify the RF signal based on the modulated voltage received via the collector node.
• the output stage also includes an output transformer.
• the output transformer is coupled to each differential amplifier in the pair of differential amplifiers.
• the output transformer includes a center tap coupled to the collector node to receive the modulated voltage.
• the output transformer is configured to output the RF signal amplified by each differential amplifier in the pair of differential amplifiers.
• the output stage also includes a neutralization circuit.
• the neutralization circuit is coupled between the interstage transformer and the output transformer and configured to inject an output-stage neutralization current into each differential amplifier in the pair of differential amplifiers to thereby suppress a modulated leakage current caused by the modulated voltage in each of the differential amplifier in the pair of differential amplifiers.
• a wireless device in another aspect, includes transmit circuitry.
• the transmit circuitry includes a differential power amplifier circuit.
• the differential power amplifier circuit includes an output stage.
• the output stage includes a collector node.
• the collector node is coupled to a power management integrated circuit (PMIC) to receive a modulated voltage.
• PMIC power management integrated circuit
• the output stage also includes an interstage transformer.
• the interstage transformer is configured to receive an RF signal.
• the output stage also includes a pair of differential amplifiers. Each differential amplifier in the pair of differential amplifiers is coupled to the interstage transformer and configured to amplify the RF signal based on the modulated voltage received via the collector node.
• the output stage also includes an output transformer. The output transformer is coupled to each differential amplifier in the pair of differential amplifiers.
• the output transformer includes a center tap coupled to the collector node to receive the modulated voltage.
• the output transformer is configured to output the RF signal amplified by each differential amplifier in the pair of differential amplifiers.
• the output stage also includes a neutralization circuit.
• the neutralization circuit is coupled between the interstage transformer and the output transformer and configured to inject an output-stage neutralization current into each differential amplifier in the pair of differential amplifiers to thereby suppress a modulated leakage current caused by the modulated voltage in each differential amplifier in the of differential amplifiers.
• a method for neutralizing memory distortion in a differential power amplifier circuit includes receiving a modulated voltage and an RF signal. The method also includes amplifying the RF signal based on the modulated voltage. The method also includes outputting the RF signal amplified by each of the differential amplifiers in the pair of differential amplifiers. The method also includes injecting an output-stage neutralization current into each differential amplifier in the pair of differential amplifiers to thereby suppress a modulated leakage current caused by the modulated voltage in each differential amplifier in the pair of differential amplifiers.
• Figure 1 A is a schematic diagram of an existing wireless transmission circuit that can suffer degraded adjacent channel leakage ratio (ACLR) performance due to memory distortion caused by a power amplifier circuit in a radio frequency (RF) signal;
• ACLR adjacent channel leakage ratio
• Figure 1 B is a schematic diagram illustrating an inner structure of an output-stage in the power amplifier circuit in Figure 1 A;
• Figure 2 is a schematic diagram of an exemplary differential power amplifier circuit wherein a neutralization circuit is configured according to an embodiment of the present disclosure to neutralize a memory distortion;
• Figures 3A and 3B are schematic diagrams providing exemplary illustrations of the neutralization circuit in the differential power amplifier circuit of Figure 2;
• Figure 4 is a schematic diagram of an exemplary differential power amplifier circuit configured according to another embodiment of the present disclosure to neutralize the memory distortion;
• Figure 5 is a schematic diagram of an exemplary differential power amplifier circuit configured according to yet another embodiment of the present disclosure to neutralize the memory distortion
• Figure 6 is a schematic diagram of an exemplary user element wherein the differential power amplifier circuits of Figures 2, 4, and 5 can be provided;
• Figure 7 is a flowchart of an exemplary process for neutralizing memory distortion in the differential power amplifier circuits of Figures 2, 4, and 5.
• Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
• Embodiments of the disclosure relate to memory distortion neutralization in a differential power amplifier circuit.
• the differential power amplifier circuit includes a pair of differential amplifiers each configured to amplify a radio frequency (RF) signal based on a modulated voltage.
• a neutralization circuit is configured to inject a neutralization current into each of the differential amplifiers to thereby neutralize a modulated leakage current that causes an unwanted memory distortion to degrade an adjacent channel leakage ratio (ACLR) of the differential power amplifier circuit.
• ACLR adjacent channel leakage ratio
• FIG. 1 A is a schematic diagram of an exemplary existing wireless transmission circuit 10 that can suffer degraded ACLR performance due to memory distortion caused by a power amplifier circuit 12 in an RF signal 14.
• the existing wireless transmission circuit 10 includes a transceiver circuit 16 and a power management integrated circuit (PMIC) 18.
• the transceiver circuit 16 is configured to generate and provide the RF signal 14 to the power amplifier circuit 12.
• the transceiver circuit 16 is also configured to generate a time-variant target voltage VTGT(t) according to a time-variant power envelope PENV(I) of the RF signal 14 and provide the time-variant target voltage VTGT(I) to the PMIC 18.
• the PMIC 18 is configured to generate a time-variant modulated voltage Vcc(t), such as an envelope tracking (ET) modulated voltage or an average power tracking (APT) modulated voltage, based on (a.k.a. track) the time-variant target voltage VTGT(I).
• Vcc(t) such as an envelope tracking (ET) modulated voltage or an average power tracking (APT) modulated voltage
• the time-variant modulated voltage Vcc(t) is generated based on the time-variant target voltage VTGT(I) and the time-variant target voltage ViGT(t) is generated according to the time-variant power envelope PENV(I) of the RF signal 14, the time-variant modulated voltage Vcc(t) is thus associated with a time-variant voltage envelope VENV(I) that tracks the time-variant power envelope PENV(I) of the RF signal 14.
• the PMIC 18 is configured to provide the time-variant modulated voltage Vcc(t) to the power amplifier circuit 12 via an external conductive trace 20, which is associated with a respective equivalent inductive impedance LTRACE-PMIC.
• the power amplifier circuit 12 is a multi-stage power amplifier that includes an input-stage 22 (denoted as “PAIN”) and an output-stage 24 (denoted as “PAOUT”).
• the input-stage 22 is configured to receive the timevariant modulated voltage Vcc(t) at an input-stage collector node 26 (also denoted as “VpA-i(t)”) and the output-stage 24 is configured to receive the timevariant modulated voltage Vcc(t) at an output-stage collector node 28 (also denoted as “VpA-o(t)”).
• the output-stage collector node 28 is coupled to the input-stage collector node 26 via an internal conductive trace 30.
• the internal conductive trace 30 is also associated with a respective equivalent inductive impedance.
• the time-variant modulated voltage Vcc(t) received at the input-stage collector node 26 can be different from the time-variant modulated voltage Vcc(t) received at the outputstage collector node 28 in phase and/or amplitude.
• the input-stage 22 is configured to receive the RF signal 14 via an input-stage input node 32 and amplify the RF signal 14 based on the time-variant modulated voltage Vcc(t) received at the input-stage collector node 26 (a.k.a. VpA-i(t)).
• the output-stage 24 is configured to receive the RF signal 14, as already amplified by the input-stage 22, via an output-stage input node 34. Accordingly, the output-stage 24 will further amplify the RF signal 14 based on the time-variant modulated voltage Vcc(t) received at the output-stage collector node 28 (a.k.a. VpA-o(t)).
• the output-stage 24 has a respective parasitic capacitance between the output-stage collector node 28 and the output-stage input node 34, as denoted by a respective equivalent capacitor CBC-O.
• a respective equivalent capacitor CBC-O there also exists an equivalent coupling capacitance CCPL between the input-stage 22 and the output-stage 24.
• the equivalent capacitor CBC-O is the main contributor to the memory distortion in the RF signal 14.
• Figure 1 B is a schematic diagram illustrating an inner structure of the output-stage 24 in the power amplifier circuit 12 in Figure 1 A. Common elements between Figures 1 A and 1 B are shown therein with common element numbers and will not be re-described herein.
• the output-stage 24 can include a transistor 36, such as a bipolar junction transistor (BJT) or a complementary metal-oxide semiconductor (CMOS) transistor.
• CMOS complementary metal-oxide semiconductor
• the transistor 36 can include a base electrode B, a collector electrode C, and an emitter electrode E.
• the collector electrode C is coupled to the output-stage collector node 28 to receive the timevariant modulated voltage VpA-o(t).
• the time-variant modulated voltage VpA-o(t) can include both linear terms and non-linear terms, as expressed in equation (Eq. 1 ) below.
• VpA-o(t) VDC + AxVEN (t) + BxVENv(t) 2 + CXVENV(I) 3 + ... (Eq. 1 )
• VDC represents a constant direct-current (DC) voltage
• AXVENV(I) represents the linear term
• BxVENv(t) 2 + CxVENv(t) 3 + ... represents the non-linear term.
• VpA-o(t) is dominated by the linear term AxVENv(t).
• the time-variant modulated voltage VpA-o(t) can be linearly approximated by equation (Eq. 2).
• Vp -o(t) When the time-variant modulated voltage Vp -o(t) is applied across the equivalent capacitor CBC-O between the output-stage collector node 28 and the output-stage input node 34, a modulated output-stage current Isc-o(t) is injected from the output-stage collector node 28 into the output-stage input node 34.
• the modulated output-stage current iBc-o(t) is also referred to as a “modulated leakage current” hereinafter.
• the modulated output-stage current iBc-o(t) As shown in equation (Eq. 3) below, the modulated output-stage current iBc-o(t) is largely a linearly modulated current.
• the modulated output-stage current iBC-o(t) is converted by an outputstage net impedance Rbb-o presenting at the base electrode B of the output-stage 24 into a voltage Rbb-oxlcB-o(t), which is then added to the RF signal 14 at the base electrode B of the transistor 36 to create a distorted base voltage VBE(I), as shown in equation (Eq. 4) below.
• KRF represents a dimensionless constant (e.g., a constant gain).
• VENv(t) and the RF signal 14 re-modulate through even order (primarily 2 nd order) distortion within the outputstage 24 to generate an output-stage distortion product that can be expressed as:
• the output-stage distortion products inherently have a memory (a.k.a. memory effect), which can be difficult to compensate for by such techniques as isoGain and linear digital predistortion (DPD).
• DPD linear digital predistortion
• the power amplifier circuit 12 can suffer a degraded ACLR performance.
• Figure 2 is a schematic diagram of an exemplary differential power amplifier circuit 38A configured according to an embodiment of the present disclosure to neutralize the output-stage distortion presenting in the power amplifier circuit 12 of the existing wireless transmission circuit 10 of Figure 1 A.
• the differential power amplifier circuit 38A is coupled to a PMIC 40 via a conductive trace 42.
• the conductive trace 42 is also associated with a respective equivalent inductive impedance LTRACE-PMIC.
• the PMIC 40 is configured to generate a modulated voltage Vcc(t) (e.g., an ET modulated voltage or an APT modulated voltage) associated with a voltage envelope VENV(I) and provide the modulated voltage Vcc(t) to a collector node 44 in the differential power amplifier circuit 38A via the conductive trace 42.
• Vcc(t) e.g., an ET modulated voltage or an APT modulated voltage
• the collector node 44 is coupled to a capacitor CLOAD, which defines a portion of the equivalent capacitance CPA of the differential power amplifier circuit 38A.
• the modulated voltage Vcc(t) as received at the collector node 44 may be modified (e.g., in amplitude and/or phase) from the modulated voltage Vcc(t) generated by the PMIC 40.
• the modulated voltage Vcc(t) as received at the collector node 44 is hereinafter referred to as the “received modulated voltage VpA(t).”
• the differential power amplifier circuit 38A includes an input stage 46 and an output stage 48.
• the input stage 46 is configured to amplify an RF signal 50.
• the output stage 48 is coupled to the input stage 46 via an interstage transformer 52 and configured to receive the amplified RF signal 50 from the input stage 46 via the interstage transformer 52.
• the output stage 48 includes a pair of differential amplifiers 54, 56, each coupled to the interstage transformer 52 via a respective blocking capacitor CBLK.
• the differential amplifiers 54, 56 are each configured to further amplify the RF signal 50, which has already been amplified by the input stage 46, based on the received modulated voltage VpA(t).
• the differential amplifiers 54, 56 are each coupled to an output transformer 58 that outputs the RF signal 50 after being further amplified by the differential amplifiers 54, 56.
• each of the differential amplifiers 54, 56 includes a respective heterojunction bipolar transistor (HBT).
• the HBT transistor includes a base electrode (denoted as “B”) coupled to the blocking capacitor CBLK and receives a bias voltage VBIAS, a collector electrode (denoted as “C”) coupled to the output transformer 58, and an emitter electrode (denoted as “E”) coupled to ground.
• the transistor HBT in each of the differential amplifiers 54, 56 can be identical to the transistor 36 illustrated in Figure 1 B.
• the transistor HBT in each of the differential amplifiers 54, 56 can have a respective equivalent capacitor CBC-OI and CBC-02 between the respective collector electrode C and the respective base electrode B.
• VPA(I) when the received modulated voltage VPA(I) is applied across the equivalent capacitor CBC-O, a pair of modulated output-stage currents IBC-OI (t) and lBc-02(t), whose sum is equivalent to the modulated output-stage current iBc-o(t) shown in Figure 1 B and expressed in the equation (Eq.
• the modulated output-stage currents iBc-oi(t) and lBc-02(t) are approximately equal. Understandably from previous discussions, the modulated output-stage currents iBc-oi(t) and lBc-02(t) can cause the voltage envelope VENv(t) and the RF signal 50 to re-modulate through even order (primarily 2 nd order) distortion within the output stage 48 to generate an output-stage distortion product that can degrade the ACLR of the differential power amplifier circuit 38A.
• the output stage 48 is configured to include a neutralization circuit 60.
• the neutralization circuit 60 is configured to generate an output-stage neutralization current iNEu-o(t) and inject the output-stage neutralization current iNEu-o(t) into the base electrode B of the transistor HBT in each of the differential amplifiers 54, 56.
• the output-stage neutralization current iNEu-o(t) is so generated to include a pair of neutralization currents INEU-OI(I) and lNEu-O2(t) approximately equal to the pair of modulated output-stage currents IBC-OI (I) and IBC-02(1), respectively, but flowing in an opposite direction from the pair of modulated output-stage currents iBc-oi(t) and lBC-O2(t).
• each of the neutralization currents INEU-OI (I) and INEU-O2(1) can be approximately equal to one-half ( 1 /2) of the output-stage neutralization current iNEu-o(t).
• the neutralization circuit 60 is configured to generate the output-stage neutralization current iNEu-o(t) at a baseband frequency (e.g., ⁇ 200 MHz), which is substantially lower than a carrier frequency (e.g., > 2 GHz) of the RF signal 50.
• a baseband frequency e.g., ⁇ 200 MHz
• carrier frequency e.g., > 2 GHz
• the neutralization circuit 60 is coupled between a center tap 62 of the interstage transformer 52 and a center tap 64 of the output transformer 58.
• the neutralization circuit 60 is configured to receive the modulated voltage VPA(I) via the center tap 64 of the output transformer 58 and derive the output-stage neutralization current iNEu-o(t) from the received modulated voltage VpA(t). Accordingly, the neutralization circuit 60 injects the output-stage neutralization current INEU-O(I) into the center tap 62 of the interstage transformer 52.
• the center tap 62 and the center tap 64 are virtual earth (a.k.a. virtual ground) points.
• a virtual earth point is a node in an electrical circuit that is maintained at a steady reference potential, without being connected directly to any reference potential.
• the neutralization circuit 60 can be turned on and off without impacting amplitude-amplitude (AMAM) and amplitudephase (AM PM) waterfall curves of the RF signal 50.
• AMAM amplitude-amplitude
• AM PM amplitudephase
• Figures 3A and 3B are schematic diagrams providing exemplary illustrations of the neutralization circuit 60 configured according to various embodiments of the present disclosure. Common elements between Figures 2, 3A, and 3B are shown therein with common element numbers and will not be redescribed herein.
• the neutralization circuit 60 can be configured to include an HBT 66 and a mirroring circuit 68.
• the HBT 66 is configured to derive an emitter neutralization current iNEu-s(t) from the received modulated voltage VPA(I).
• the HBT 66 may be replaced by a capacitor.
• the mirroring circuit 68 (e.g., 1 -to-N mirroring circuit) is configured to amplify the emitter neutralization current INEU-S(I) (e.g., by N times), invert a direction of the output-stage neutralization current iNEu-o(t), and inject the amplified output-stage neutralization current iNEu-o(t) into the center tap 62 of the interstage transformer 52.
• the neutralization circuit 60 can be configured to include the HBT 66 and a common stage circuit 70.
• the common stage circuit 70 is configured to amplify a sum of the interstage neutralization current iNEu-i(t) and the emitter neutralization current iNEu-s(t) to thereby inject the amplified output-stage neutralization current iNEu-o(t) into the center tap 62 of the interstage transformer 52.
• the neutralization circuit 60 may be further configured to derive an interstage neutralization current iNEu-i(t) from the received modulated voltage VPA(I) to help suppress the extra leakage current caused by the equivalent coupling capacitance CCPL.
• the mirroring circuit 68 will amplify a sum of the emitter neutralization current iNEu-s(t) and the interstage neutralization current INEU-I(I) (e.g., by N times) to thereby generate the amplified output-stage neutralization current iNEu-o(t).
• Figure 4 is a schematic diagram of an exemplary differential power amplifier circuit 38B configured according to another embodiment of the present disclosure to further suppress the extra leakage current caused by the equivalent coupling capacitance CC L.
• Common elements between Figures 2, 3A, and 4 are shown therein with common element numbers and will not be re-described herein.
• the input stage 46 includes an input stage HBT 72.
• the neutralization circuit 60 is further configured to derive the interstage neutralization current INEU i(t) from the collector electrode C of the input stage HBT 72 in the input stage 46 to thereby suppress the extra leakage current caused by the coupling capacitance CCPL between the input stage 46 and the output stage 48.
• FIG. 5 is a schematic diagram of an exemplary differential power amplifier circuit 38C configured according to yet another embodiment of the present disclosure. Common elements between Figures 2 and 5 are shown therein with common element numbers and will not be re-described herein.
• the differential power amplifier circuit 38C includes an output stage 48A wherein the neutralization circuit 60 is coupled to the output transformer 58 via a divider network 74. Accordingly, the neutralization circuit 60 is configured to receive the modulated voltage VPA(I) via the divider network 74.
• the divider network 74 is coupled in parallel to the output transformer 58 and configured to divide the received modulated voltage VPA(I).
• the neutralization circuit 60 is coupled between a center point 76 of the divider network 74 and the center tap 62 of the interstage transformer 52.
• the neutralization circuit 60 then derives the output-stage neutralization current iNEu-o(t) from the modulated voltage VPA(I) received via the center point 76 and injects the output-stage neutralization current INEU-O(I) into the center tap 62 of the interstage transformer 52.
• the differential power amplifier circuit 38A of Figure 2, the differential power amplifier circuit 38B of Figure 4, and the differential power amplifier circuit 38C of Figure 5 can be provided in a user element (a.k.a. wireless device) to enable the embodiments described above.
• Figure 6 is a schematic diagram of an exemplary user element 100 wherein the differential power amplifier circuit 38A of Figure 2, the differential power amplifier circuit 38B of Figure 4, and the differential power amplifier circuit 38C of Figure 5 can be provided.
• the user element 100 can be any type of user elements, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications.
• the user element 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 112, and user interface circuitry 1 14.
• the control system 102 can be a field-programmable gate array (FPGA), as an example.
• the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s).
• the receive circuitry 108 receives radio frequency signals via the antennas 1 12 and through the antenna switching circuitry 110 from one or more base stations.
• a low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing.
• Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC).
• ADC analog-to-digital converter
• the baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below.
• the baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).
• the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission.
• the encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies.
• DAC digital-to-analog converter
• a power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 1 12 through the antenna switching circuitry 110.
• the multiple antennas 1 12 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.
• the transmit circuitry 106 can function as a wireless transmission circuit. Accordingly, the transmit circuitry 106 can be configured to include any of the differential power amplifier circuit 38A of Figure 2, the differential power amplifier circuit 38B of Figure 4, and the differential power amplifier circuit 38C of Figure 5.
• FIG. 7 is a flowchart of an exemplary process 200 for neutralizing memory distortion in the differential power amplifier circuit 38A of Figure 2, the differential power amplifier circuit 38B of Figure 4, and the differential power amplifier circuit 38C of Figure 5.
• the process 200 includes receiving the modulated voltage VpA(t) and the RF signal 50 (step 202).
• the process 200 also includes amplifying the RF signal 50 based on the modulated voltage VPA(I) (step 204).
• the process 200 also includes outputting the RF signal 50 amplified by each of the differential amplifiers in the pair of differential amplifiers 54, 56 (step 206).
• the process 200 further includes injecting the output-stage neutralization current hEu-o(t) into each differential amplifier in the pair of differential amplifiers 54, 56 to thereby suppress the modulated leakage current (iBc-o(t)) caused by the modulated voltage VPA(I) in each differential amplifier in the pair of differential amplifiers 54, 56 (step 208).

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• 2023
  • 2023-12-20 WO PCT/US2023/085103 patent/WO2024147930A1/en not_active Ceased
  • 2023-12-20 CN CN202380085810.9A patent/CN120359703A/zh active Pending
  • 2023-12-20 EP EP23848091.7A patent/EP4646784A1/de active Pending
  • 2023-12-20 KR KR1020257019897A patent/KR20250133284A/ko active Pending

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