EP4646784A1 - Memory distortion neutralization in a differential power amplifier circuit - Google Patents

Abstract

Memory distortion neutralization in a differential power amplifier circuit is provided. The differential power amplifier circuit includes a pair of differential amplifiers each configured to amplify a radio frequency (RF) signal based on a modulated voltage. In embodiments disclosed herein, a neutralization circuit is configured to inject a neutralization current into each of the differential amplifiers to thereby neutralize a modulated leakage current that causes an unwanted memory distortion to degrade an adjacent channel leakage ratio (ACLR) of the differential power amplifier circuit. By neutralizing the modulated leakage current, it is possible to prevent the unwanted memory distortion from being generated, thus helping to improve the ACLR of the differential power amplifier circuit.

Description

MEMORY DISTORTION NEUTRALIZATION IN A DIFFERENTIAL POWER AMPLIFIER CIRCUIT

Related Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63/478,750, filed on January 6, 2023, the disclosure of which is hereby incorporated herein by reference in its entirety.

Field of the Disclosure

[0002] The technology of the disclosure relates generally to neutralizing memory distortion in a differential power amplifier circuit.

Background

[0003] Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capability in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0004] The redefined user experience relies on higher data rates offered by advanced fifth generation (5G) and 5G new radio (5G-NR) systems, in which a transmission circuit typically amplifies a radio frequency (RF) signal to a higher power before transmission. In a typical transmission circuit, a transceiver circuit is configured to generate the RF signal, a power management circuit is configured to generate a modulated voltage, a power amplifier circuit is configured to amplify the RF signal based on the modulated voltage, and an antenna circuit is configured to radiate the RF signal in one or more RF frequencies.

[0005] The RF signal transmitted in the 5G and 5G-NR systems is subject to stringent adjacent channel leakage ratio (ACLR) requirements imposed by standard bodies and/or regulatory authorities. The ACLR defines a ratio between a power of the RF signal transmitted on an intended radio channel and the power of the RF signal received in an unintended adjacent radio channel. Given that the ACLR of a wideband RF signal can be largely dominated by a remodulation term(s), such as a third order intermodulation product (IMD3), it is thus desirable to improve IMD3 performance of the transmission circuit to thereby improve the ACLR.

[0006] Embodiments of the disclosure relate to memory distortion neutralization in a differential power amplifier circuit. The differential power amplifier circuit includes a pair of differential amplifiers each configured to amplify a radio frequency (RF) signal based on a modulated voltage. In embodiments disclosed herein, a neutralization circuit is configured to inject a neutralization current into each of the differential amplifiers to thereby neutralize a modulated leakage current that causes an unwanted memory distortion to degrade an adjacent channel leakage ratio (ACLR) of the differential power amplifier circuit. By neutralizing the modulated leakage current, it is possible to prevent the unwanted memory distortion from being generated, thus helping to improve the ACLR of the differential power amplifier circuit.

[0007] In one aspect, a differential power amplifier circuit is provided. The differential power amplifier circuit includes an output stage. The output stage includes a collector node. The collector node is coupled to a power management integrated circuit (PMIC) to receive a modulated voltage. The output stage also includes an interstage transformer. The interstage transformer is configured to receive an RF signal. The output stage also includes a pair of differential amplifiers. Each differential amplifier in the pair of differential amplifiers is coupled to the interstage transformer and configured to amplify the RF signal based on the modulated voltage received via the collector node. The output stage also includes an output transformer. The output transformer is coupled to each differential amplifier in the pair of differential amplifiers. The output transformer includes a center tap coupled to the collector node to receive the modulated voltage. The output transformer is configured to output the RF signal amplified by each differential amplifier in the pair of differential amplifiers. The output stage also includes a neutralization circuit. The neutralization circuit is coupled between the interstage transformer and the output transformer and configured to inject an output-stage neutralization current into each differential amplifier in the pair of differential amplifiers to thereby suppress a modulated leakage current caused by the modulated voltage in each of the differential amplifier in the pair of differential amplifiers.

[0008] In another aspect, a wireless device is provided. The wireless device includes transmit circuitry. The transmit circuitry includes a differential power amplifier circuit. The differential power amplifier circuit includes an output stage. The output stage includes a collector node. The collector node is coupled to a power management integrated circuit (PMIC) to receive a modulated voltage. The output stage also includes an interstage transformer. The interstage transformer is configured to receive an RF signal. The output stage also includes a pair of differential amplifiers. Each differential amplifier in the pair of differential amplifiers is coupled to the interstage transformer and configured to amplify the RF signal based on the modulated voltage received via the collector node. The output stage also includes an output transformer. The output transformer is coupled to each differential amplifier in the pair of differential amplifiers. The output transformer includes a center tap coupled to the collector node to receive the modulated voltage. The output transformer is configured to output the RF signal amplified by each differential amplifier in the pair of differential amplifiers. The output stage also includes a neutralization circuit. The neutralization circuit is coupled between the interstage transformer and the output transformer and configured to inject an output-stage neutralization current into each differential amplifier in the pair of differential amplifiers to thereby suppress a modulated leakage current caused by the modulated voltage in each differential amplifier in the of differential amplifiers.

[0009] In another aspect, a method for neutralizing memory distortion in a differential power amplifier circuit is provided. The method includes receiving a modulated voltage and an RF signal. The method also includes amplifying the RF signal based on the modulated voltage. The method also includes outputting the RF signal amplified by each of the differential amplifiers in the pair of differential amplifiers. The method also includes injecting an output-stage neutralization current into each differential amplifier in the pair of differential amplifiers to thereby suppress a modulated leakage current caused by the modulated voltage in each differential amplifier in the pair of differential amplifiers.

[0010] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

Brief Description of the Drawing Figures

[0011] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0012] Figure 1 A is a schematic diagram of an existing wireless transmission circuit that can suffer degraded adjacent channel leakage ratio (ACLR) performance due to memory distortion caused by a power amplifier circuit in a radio frequency (RF) signal;

[0013] Figure 1 B is a schematic diagram illustrating an inner structure of an output-stage in the power amplifier circuit in Figure 1 A;

[0014] Figure 2 is a schematic diagram of an exemplary differential power amplifier circuit wherein a neutralization circuit is configured according to an embodiment of the present disclosure to neutralize a memory distortion;

[0015] Figures 3A and 3B are schematic diagrams providing exemplary illustrations of the neutralization circuit in the differential power amplifier circuit of Figure 2; [0016] Figure 4 is a schematic diagram of an exemplary differential power amplifier circuit configured according to another embodiment of the present disclosure to neutralize the memory distortion;

[0017] Figure 5 is a schematic diagram of an exemplary differential power amplifier circuit configured according to yet another embodiment of the present disclosure to neutralize the memory distortion;

[0018] Figure 6 is a schematic diagram of an exemplary user element wherein the differential power amplifier circuits of Figures 2, 4, and 5 can be provided; and

[0019] Figure 7 is a flowchart of an exemplary process for neutralizing memory distortion in the differential power amplifier circuits of Figures 2, 4, and 5.

Detailed Description

[0020] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0021] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. [0022] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0023] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0026] Embodiments of the disclosure relate to memory distortion neutralization in a differential power amplifier circuit. The differential power amplifier circuit includes a pair of differential amplifiers each configured to amplify a radio frequency (RF) signal based on a modulated voltage. In embodiments disclosed herein, a neutralization circuit is configured to inject a neutralization current into each of the differential amplifiers to thereby neutralize a modulated leakage current that causes an unwanted memory distortion to degrade an adjacent channel leakage ratio (ACLR) of the differential power amplifier circuit. By neutralizing the modulated leakage current, it is possible to prevent the unwanted memory distortion from being generated, thus helping to improve the ACLR of the differential power amplifier circuit.

[0027] Before discussing the differential power amplifier circuit according to the present disclosure, starting at Figure 2, a brief discussion of an existing power amplifier circuit is first provided with reference to Figures 1 A and 1 B to help understand how a memory distortion may be created at a collector node(s) of a power amplifier circuit.

[0028] Figure 1 A is a schematic diagram of an exemplary existing wireless transmission circuit 10 that can suffer degraded ACLR performance due to memory distortion caused by a power amplifier circuit 12 in an RF signal 14. The existing wireless transmission circuit 10 includes a transceiver circuit 16 and a power management integrated circuit (PMIC) 18. The transceiver circuit 16 is configured to generate and provide the RF signal 14 to the power amplifier circuit 12. The transceiver circuit 16 is also configured to generate a time-variant target voltage VTGT(t) according to a time-variant power envelope PENV(I) of the RF signal 14 and provide the time-variant target voltage VTGT(I) to the PMIC 18. The PMIC 18 is configured to generate a time-variant modulated voltage Vcc(t), such as an envelope tracking (ET) modulated voltage or an average power tracking (APT) modulated voltage, based on (a.k.a. track) the time-variant target voltage VTGT(I). Notably, since the time-variant modulated voltage Vcc(t) is generated based on the time-variant target voltage VTGT(I) and the time-variant target voltage ViGT(t) is generated according to the time-variant power envelope PENV(I) of the RF signal 14, the time-variant modulated voltage Vcc(t) is thus associated with a time-variant voltage envelope VENV(I) that tracks the time-variant power envelope PENV(I) of the RF signal 14. The PMIC 18 is configured to provide the time-variant modulated voltage Vcc(t) to the power amplifier circuit 12 via an external conductive trace 20, which is associated with a respective equivalent inductive impedance LTRACE-PMIC.

[0029] Herein, the power amplifier circuit 12 is a multi-stage power amplifier that includes an input-stage 22 (denoted as “PAIN”) and an output-stage 24 (denoted as “PAOUT”). The input-stage 22 is configured to receive the timevariant modulated voltage Vcc(t) at an input-stage collector node 26 (also denoted as “VpA-i(t)”) and the output-stage 24 is configured to receive the timevariant modulated voltage Vcc(t) at an output-stage collector node 28 (also denoted as “VpA-o(t)”). The output-stage collector node 28 is coupled to the input-stage collector node 26 via an internal conductive trace 30. Like the external conductive trace 20, the internal conductive trace 30 is also associated with a respective equivalent inductive impedance. As such, the time-variant modulated voltage Vcc(t) received at the input-stage collector node 26 can be different from the time-variant modulated voltage Vcc(t) received at the outputstage collector node 28 in phase and/or amplitude.

[0030] The input-stage 22 is configured to receive the RF signal 14 via an input-stage input node 32 and amplify the RF signal 14 based on the time-variant modulated voltage Vcc(t) received at the input-stage collector node 26 (a.k.a. VpA-i(t)). The output-stage 24 is configured to receive the RF signal 14, as already amplified by the input-stage 22, via an output-stage input node 34. Accordingly, the output-stage 24 will further amplify the RF signal 14 based on the time-variant modulated voltage Vcc(t) received at the output-stage collector node 28 (a.k.a. VpA-o(t)).

[0031] The output-stage 24 has a respective parasitic capacitance between the output-stage collector node 28 and the output-stage input node 34, as denoted by a respective equivalent capacitor CBC-O. In addition, there also exists an equivalent coupling capacitance CCPL between the input-stage 22 and the output-stage 24. As discussed in detail in Figure 1 B, the equivalent capacitor CBC-O is the main contributor to the memory distortion in the RF signal 14.

[0032] Figure 1 B is a schematic diagram illustrating an inner structure of the output-stage 24 in the power amplifier circuit 12 in Figure 1 A. Common elements between Figures 1 A and 1 B are shown therein with common element numbers and will not be re-described herein.

[0033] The output-stage 24 can include a transistor 36, such as a bipolar junction transistor (BJT) or a complementary metal-oxide semiconductor (CMOS) transistor. Taking the BJT as an example, the transistor 36 can include a base electrode B, a collector electrode C, and an emitter electrode E. The collector electrode C is coupled to the output-stage collector node 28 to receive the timevariant modulated voltage VpA-o(t).

[0034] The time-variant modulated voltage VpA-o(t) can include both linear terms and non-linear terms, as expressed in equation (Eq. 1 ) below.

VpA-o(t) = VDC + AxVEN (t) + BxVENv(t)² + CXVENV(I)³ + ... (Eq. 1 )

[0035] In the equation (Eq. 1 ), VDC represents a constant direct-current (DC) voltage, AXVENV(I) represents the linear term, and BxVENv(t)² + CxVENv(t)³ + ... represents the non-linear term. Studies have shown that the time-variant modulated voltage VpA-o(t) is dominated by the linear term AxVENv(t). As such, the time-variant modulated voltage VpA-o(t) can be linearly approximated by equation (Eq. 2).

VpA-o(t) VDC + AXVENV(I) (Eq. 2) [0036] When the time-variant modulated voltage Vp -o(t) is applied across the equivalent capacitor CBC-O between the output-stage collector node 28 and the output-stage input node 34, a modulated output-stage current Isc-o(t) is injected from the output-stage collector node 28 into the output-stage input node 34. In this regard, the modulated output-stage current iBc-o(t) is also referred to as a “modulated leakage current” hereinafter. As shown in equation (Eq. 3) below, the modulated output-stage current iBc-o(t) is largely a linearly modulated current. lcB-o(t) CBC-O x AxdVENv(t)/dt (Eq. 3)

[0037] The modulated output-stage current iBC-o(t) is converted by an outputstage net impedance Rbb-o presenting at the base electrode B of the output-stage 24 into a voltage Rbb-oxlcB-o(t), which is then added to the RF signal 14 at the base electrode B of the transistor 36 to create a distorted base voltage VBE(I), as shown in equation (Eq. 4) below.

VBE(t) VENv(t)xKRFxsin(a>ct + <p(t)) + Rbb-oxlcB-o(t) (Eq. 4)

[0038] In the equation (Eq. 4), KRF represents a dimensionless constant (e.g., a constant gain). The time-variant voltage envelope VENv(t) and the RF signal 14 re-modulate through even order (primarily 2^nd order) distortion within the outputstage 24 to generate an output-stage distortion product that can be expressed as:

KoxRbb-OxlcB-O(t) xVENv(t)xKRFxSin( >Ct + <p(t))

[0039] Notably, as a derivative of the time-variant voltage envelope VENV(I), the output-stage distortion products inherently have a memory (a.k.a. memory effect), which can be difficult to compensate for by such techniques as isoGain and linear digital predistortion (DPD). As a result, the power amplifier circuit 12 can suffer a degraded ACLR performance. Hence, it is desirable to prevent the output-stage distortion products from being generated to thereby help improve ACLR performance of the power amplifier circuit 12.

[0040] In this regard, Figure 2 is a schematic diagram of an exemplary differential power amplifier circuit 38A configured according to an embodiment of the present disclosure to neutralize the output-stage distortion presenting in the power amplifier circuit 12 of the existing wireless transmission circuit 10 of Figure 1 A. In an embodiment, the differential power amplifier circuit 38A is coupled to a PMIC 40 via a conductive trace 42. Like the external conductive trace 20 in Figure 1 A, the conductive trace 42 is also associated with a respective equivalent inductive impedance LTRACE-PMIC. Like the PMIC 18 in Figure 1A, the PMIC 40 is configured to generate a modulated voltage Vcc(t) (e.g., an ET modulated voltage or an APT modulated voltage) associated with a voltage envelope VENV(I) and provide the modulated voltage Vcc(t) to a collector node 44 in the differential power amplifier circuit 38A via the conductive trace 42. Typically, the collector node 44 is coupled to a capacitor CLOAD, which defines a portion of the equivalent capacitance CPA of the differential power amplifier circuit 38A.

[0041] Given the influence of the respective equivalent inductive impedance LTRACE-PMIC, the modulated voltage Vcc(t) as received at the collector node 44 may be modified (e.g., in amplitude and/or phase) from the modulated voltage Vcc(t) generated by the PMIC 40. For the purpose of distinction, the modulated voltage Vcc(t) as received at the collector node 44 is hereinafter referred to as the “received modulated voltage VpA(t).”

[0042] The differential power amplifier circuit 38A includes an input stage 46 and an output stage 48. The input stage 46 is configured to amplify an RF signal 50. The output stage 48 is coupled to the input stage 46 via an interstage transformer 52 and configured to receive the amplified RF signal 50 from the input stage 46 via the interstage transformer 52.

[0043] The output stage 48 includes a pair of differential amplifiers 54, 56, each coupled to the interstage transformer 52 via a respective blocking capacitor CBLK. The differential amplifiers 54, 56 are each configured to further amplify the RF signal 50, which has already been amplified by the input stage 46, based on the received modulated voltage VpA(t). The differential amplifiers 54, 56 are each coupled to an output transformer 58 that outputs the RF signal 50 after being further amplified by the differential amplifiers 54, 56.

[0044] In a non-limiting example, each of the differential amplifiers 54, 56 includes a respective heterojunction bipolar transistor (HBT). Specifically, the HBT transistor includes a base electrode (denoted as “B”) coupled to the blocking capacitor CBLK and receives a bias voltage VBIAS, a collector electrode (denoted as “C”) coupled to the output transformer 58, and an emitter electrode (denoted as “E”) coupled to ground.

[0045] The transistor HBT in each of the differential amplifiers 54, 56 can be identical to the transistor 36 illustrated in Figure 1 B. In this regard, like the transistor 36 in Figure 1 B, the transistor HBT in each of the differential amplifiers 54, 56 can have a respective equivalent capacitor CBC-OI and CBC-02 between the respective collector electrode C and the respective base electrode B. As such, when the received modulated voltage VPA(I) is applied across the equivalent capacitor CBC-O, a pair of modulated output-stage currents IBC-OI (t) and lBc-02(t), whose sum is equivalent to the modulated output-stage current iBc-o(t) shown in Figure 1 B and expressed in the equation (Eq. 3) above, can each be injected from the collector electrode C into the base collector B. In a non-limiting example, the modulated output-stage currents iBc-oi(t) and lBc-02(t) are approximately equal. Understandably from previous discussions, the modulated output-stage currents iBc-oi(t) and lBc-02(t) can cause the voltage envelope VENv(t) and the RF signal 50 to re-modulate through even order (primarily 2^nd order) distortion within the output stage 48 to generate an output-stage distortion product that can degrade the ACLR of the differential power amplifier circuit 38A. [0046] In this regard, the output stage 48 is configured to include a neutralization circuit 60. The neutralization circuit 60 is configured to generate an output-stage neutralization current iNEu-o(t) and inject the output-stage neutralization current iNEu-o(t) into the base electrode B of the transistor HBT in each of the differential amplifiers 54, 56. Specifically, the output-stage neutralization current iNEu-o(t) is so generated to include a pair of neutralization currents INEU-OI(I) and lNEu-O2(t) approximately equal to the pair of modulated output-stage currents IBC-OI (I) and IBC-02(1), respectively, but flowing in an opposite direction from the pair of modulated output-stage currents iBc-oi(t) and lBC-O2(t). In other words, INEU-OI (I) ~ iBC-oi(t) and INEU-O2(1) » lBC-02(t). Herein, each of the neutralization currents INEU-OI (I) and INEU-O2(1) can be approximately equal to one-half (¹/2) of the output-stage neutralization current iNEu-o(t). According to embodiments described herein, the neutralization circuit 60 is configured to generate the output-stage neutralization current iNEu-o(t) at a baseband frequency (e.g., < 200 MHz), which is substantially lower than a carrier frequency (e.g., > 2 GHz) of the RF signal 50. By neutralizing the pair of modulated output-stage currents iBc-oi(t) and lBc-02(t), it is possible to prevent the unwanted memory distortion from being generated, thus helping to improve the ACLR of the differential power amplifier circuit 38A.

[0047] According to an embodiment of the present disclosure, the neutralization circuit 60 is coupled between a center tap 62 of the interstage transformer 52 and a center tap 64 of the output transformer 58. The neutralization circuit 60 is configured to receive the modulated voltage VPA(I) via the center tap 64 of the output transformer 58 and derive the output-stage neutralization current iNEu-o(t) from the received modulated voltage VpA(t). Accordingly, the neutralization circuit 60 injects the output-stage neutralization current INEU-O(I) into the center tap 62 of the interstage transformer 52.

[0048] Notably, the center tap 62 and the center tap 64 are virtual earth (a.k.a. virtual ground) points. Herein, a virtual earth point is a node in an electrical circuit that is maintained at a steady reference potential, without being connected directly to any reference potential. As such, the neutralization circuit 60 can be turned on and off without impacting amplitude-amplitude (AMAM) and amplitudephase (AM PM) waterfall curves of the RF signal 50. Moreover, it is possible to retrofit the neutralization circuit 60 into an existing differential power amplifier circuit. [0049] Figures 3A and 3B are schematic diagrams providing exemplary illustrations of the neutralization circuit 60 configured according to various embodiments of the present disclosure. Common elements between Figures 2, 3A, and 3B are shown therein with common element numbers and will not be redescribed herein.

[0050] With reference to Figure 3A, in one embodiment, the neutralization circuit 60 can be configured to include an HBT 66 and a mirroring circuit 68. The HBT 66 is configured to derive an emitter neutralization current iNEu-s(t) from the received modulated voltage VPA(I). In an alternative embodiment, the HBT 66 may be replaced by a capacitor. The mirroring circuit 68 (e.g., 1 -to-N mirroring circuit) is configured to amplify the emitter neutralization current INEU-S(I) (e.g., by N times), invert a direction of the output-stage neutralization current iNEu-o(t), and inject the amplified output-stage neutralization current iNEu-o(t) into the center tap 62 of the interstage transformer 52.

[0051] With reference to Figure 3B, in an alternative embodiment, the neutralization circuit 60 can be configured to include the HBT 66 and a common stage circuit 70. Herein, the common stage circuit 70 is configured to amplify a sum of the interstage neutralization current iNEu-i(t) and the emitter neutralization current iNEu-s(t) to thereby inject the amplified output-stage neutralization current iNEu-o(t) into the center tap 62 of the interstage transformer 52.

[0052] With reference back to Figure 2, like in the power amplifier circuit 12 in Figure 1 A, there also exists an equivalent coupling capacitance CCPL between the input stage 46 and the output stage 48 in the differential power amplifier circuit 38A. The equivalent coupling capacitance CCPL can also cause a second leakage current (not shown) being added to the pair of modulated output-stage currents lec oi(t) and Iec o2(t). This extra leakage current, although much smaller (e.g., 10X smaller) than the pair of modulated output-stage currents IBC-OI (t) and lBc-02(t), can nevertheless worsen the output-stage distortion product in the output stage 48. In this regard, it may be desirable to further suppress the extra leakage current caused by the equivalent coupling capacitance CCPL. [0053] With reference to Figure 3A, the neutralization circuit 60 may be further configured to derive an interstage neutralization current iNEu-i(t) from the received modulated voltage VPA(I) to help suppress the extra leakage current caused by the equivalent coupling capacitance CCPL. Accordingly, the mirroring circuit 68 will amplify a sum of the emitter neutralization current iNEu-s(t) and the interstage neutralization current INEU-I(I) (e.g., by N times) to thereby generate the amplified output-stage neutralization current iNEu-o(t). Accordingly, Figure 4 is a schematic diagram of an exemplary differential power amplifier circuit 38B configured according to another embodiment of the present disclosure to further suppress the extra leakage current caused by the equivalent coupling capacitance CC L. Common elements between Figures 2, 3A, and 4 are shown therein with common element numbers and will not be re-described herein.

[0054] Herein, the input stage 46 includes an input stage HBT 72. The neutralization circuit 60 is further configured to derive the interstage neutralization current INEU i(t) from the collector electrode C of the input stage HBT 72 in the input stage 46 to thereby suppress the extra leakage current caused by the coupling capacitance CCPL between the input stage 46 and the output stage 48.

[0055] Alternative to coupling the neutralization circuit 60 to the center tap 64 of the output transformer 58, it is also possible to couple the neutralization circuit to a divider network. Figure 5 is a schematic diagram of an exemplary differential power amplifier circuit 38C configured according to yet another embodiment of the present disclosure. Common elements between Figures 2 and 5 are shown therein with common element numbers and will not be re-described herein.

[0056] The differential power amplifier circuit 38C includes an output stage 48A wherein the neutralization circuit 60 is coupled to the output transformer 58 via a divider network 74. Accordingly, the neutralization circuit 60 is configured to receive the modulated voltage VPA(I) via the divider network 74. In a nonlimiting example, the divider network 74 is coupled in parallel to the output transformer 58 and configured to divide the received modulated voltage VPA(I). Specifically, the neutralization circuit 60 is coupled between a center point 76 of the divider network 74 and the center tap 62 of the interstage transformer 52. The neutralization circuit 60 then derives the output-stage neutralization current iNEu-o(t) from the modulated voltage VPA(I) received via the center point 76 and injects the output-stage neutralization current INEU-O(I) into the center tap 62 of the interstage transformer 52.

[0057] The differential power amplifier circuit 38A of Figure 2, the differential power amplifier circuit 38B of Figure 4, and the differential power amplifier circuit 38C of Figure 5 can be provided in a user element (a.k.a. wireless device) to enable the embodiments described above. In this regard, Figure 6 is a schematic diagram of an exemplary user element 100 wherein the differential power amplifier circuit 38A of Figure 2, the differential power amplifier circuit 38B of Figure 4, and the differential power amplifier circuit 38C of Figure 5 can be provided.

[0058] Herein, the user element 100 can be any type of user elements, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user element 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 112, and user interface circuitry 1 14. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 1 12 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC). [0059] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0060] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 1 12 through the antenna switching circuitry 110. The multiple antennas 1 12 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0061] In an embodiment, the transmit circuitry 106 can function as a wireless transmission circuit. Accordingly, the transmit circuitry 106 can be configured to include any of the differential power amplifier circuit 38A of Figure 2, the differential power amplifier circuit 38B of Figure 4, and the differential power amplifier circuit 38C of Figure 5.

[0062] In an embodiment, it is possible to neutralize memory distortion in the differential power amplifier circuit 38A of Figure 2, the differential power amplifier circuit 38B of Figure 4, and/or the differential power amplifier circuit 38C of Figure 5 based on a process. In this regard, Figure 7 is a flowchart of an exemplary process 200 for neutralizing memory distortion in the differential power amplifier circuit 38A of Figure 2, the differential power amplifier circuit 38B of Figure 4, and the differential power amplifier circuit 38C of Figure 5. [0063] Herein, the process 200 includes receiving the modulated voltage VpA(t) and the RF signal 50 (step 202). The process 200 also includes amplifying the RF signal 50 based on the modulated voltage VPA(I) (step 204). The process 200 also includes outputting the RF signal 50 amplified by each of the differential amplifiers in the pair of differential amplifiers 54, 56 (step 206). The process 200 further includes injecting the output-stage neutralization current hEu-o(t) into each differential amplifier in the pair of differential amplifiers 54, 56 to thereby suppress the modulated leakage current (iBc-o(t)) caused by the modulated voltage VPA(I) in each differential amplifier in the pair of differential amplifiers 54, 56 (step 208).

[0064] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

Claims What is claimed is:

1 . A differential power amplifier circuit (38A, 38B, 38C) comprising an output stage (48, 48A) comprising: a collector node (44) coupled to a power management integrated circuit, PMIC, (40) to receive a modulated voltage; an interstage transformer (52) configured to receive a radio frequency, RF, signal (50); a pair of differential amplifiers (54, 56) each coupled to the interstage transformer (52) and configured to amplify the RF signal (50) based on the modulated voltage received via the collector node (44); an output transformer (58) coupled to each of the differential amplifiers in the pair of differential amplifiers (54, 56) and having a center tap (64) coupled to the collector node (44) to receive the modulated voltage, the output transformer (58) is configured to output the RF signal (50) amplified by each of the differential amplifiers in the pair of differential amplifiers (54, 56); and a neutralization circuit (60) coupled between the interstage transformer (52) and the output transformer (58) and configured to inject an output-stage neutralization current (iNEu-o(t)) into each differential amplifiers in the pair of differential amplifiers (54, 56) to thereby suppress a modulated leakage current (iBc-o(t)) caused by the modulated voltage in each differential amplifier in the pair of differential amplifiers (54, 56).

2. The differential power amplifier circuit of claim 1 , wherein: the pair of differential amplifiers each comprises a heterojunction bipolar transistor, HBT, having a base electrode coupled to the interstage transformer via a blocking capacitor, a collector electrode coupled to the output transformer to receive the modulated voltage, and an emitter electrode coupled to a ground; and the neutralization circuit is further configured to inject the output-stage neutralization current into the base electrode of the HBT in each differential amplifier in the pair of differential amplifiers to thereby suppress the modulated leakage current collectively caused by the modulated voltage and an equivalent capacitance of the HBT in each differential amplifier in the pair of differential amplifiers.

3. The differential power amplifier circuit of claim 2, wherein the neutralization circuit is further configured to inject the output-stage neutralization current in an opposite direction from the modulated leakage current flowing through the HBT in each differential amplifier in the pair of differential amplifiers.

4. The differential power amplifier circuit of claim 3, wherein the output-stage neutralization current comprises a pair of neutralization currents each equal to one-half of the output-stage neutralization current.

5. The differential power amplifier circuit (38A, 38B) of claim 1 , wherein the neutralization circuit (60) is coupled between a center tap (62) of the interstage transformer (52) and the center tap (64) of the output transformer (58) and configured to: receive the modulated voltage via the center tap (64) of the output transformer (58); derive the output-stage neutralization current from the modulated voltage; and inject the output-stage neutralization current into the center tap (62) of the interstage transformer (52).

6. The differential power amplifier circuit (38A, 38B) of claim 5, wherein the neutralization circuit (60) comprises: one of a heterojunction bipolar transistor, HBT, (66) and a capacitor configured to derive an emitter neutralization current (iNEu-s(t)) from the modulated voltage; and a mirroring circuit (68) configured to amplify at least the emitter neutralization current (iNEu-s(t)) to thereby generate and inject the amplified output-stage neutralization current into the center tap of the interstage transformer.

7. The differential power amplifier circuit (38A, 38B) of claim 5, wherein the neutralization circuit (60) comprises: a heterojunction bipolar transistor, HBT, (66) configured to derive an emitter neutralization current (INEU-S( ) from the modulated voltage; and a common stage circuit (70) configured to amplify at least the emitter neutralization current (INEU s(t)) to thereby generate and inject the amplified output-stage neutralization current into the center tap of the interstage transformer.

8. The differential power amplifier circuit (38A, 38B, 38C) of claim 6 or 7, further comprising an input stage (46) coupled to the interstage transformer (52), wherein the neutralization circuit (60) is further configured to: derive an interstage neutralization current (INEU-I(I)) from the modulated voltage; and amplify a sum of the emitter neutralization current (INEU-S(I)) and the interstage neutralization current (INEU-I(I)) to thereby generate and inject the interstage neutralization current (INEU i(t)) into the center tap (62) of the interstage transformer (52) to thereby suppress an extra leakage current caused by a coupling capacitance between the input stage (46) and the output stage (48, 48A).

9. The differential power amplifier circuit (38C) of claim 1 , wherein: the output stage (48A) further comprises a divider network (74) coupled in parallel to the output transformer (58) and configured to divide the modulated voltage received via the collector node (44); and the neutralization circuit (60) is coupled between a center point (76) of the divider network (74) and a center tap (62) of the interstage transformer (52), the neutralization circuit (60) is configured to: receive the modulated voltage via the center point (76) of the divider network (74); derive the output-stage neutralization current from the modulated voltage; and inject the output-stage neutralization current into the center tap (62) of the interstage transformer (52).

10. The differential power amplifier circuit of claim 1 , wherein the neutralization circuit is further configured to generate the output-stage neutralization current at a baseband frequency.

1 1. A wireless device (100) comprising transmit circuitry (106), the transmit circuitry (106) comprises a differential power amplifier circuit (38A, 38B, 38C) that comprises an output stage (48, 48A) comprising: a collector node (44) coupled to a power management integrated circuit, PMIC, (40) to receive a modulated voltage; an interstage transformer (52) configured to receive a radio frequency, RF, signal (50); a pair of differential amplifiers (54, 56) each coupled to the interstage transformer (52) and configured to amplify the RF signal (50) based on the modulated voltage received via the collector node (44); an output transformer (58) coupled to each differential amplifier in the pair of differential amplifiers (54, 56) and having a center tap (64) coupled to the collector node (44) to receive the modulated voltage, the output transformer (58) is configured to output the RF signal (50) amplified by each differential amplifier in the pair of differential amplifiers (54, 56); and a neutralization circuit (60) coupled between the interstage transformer (52) and the output transformer (58) and configured to inject an output-stage neutralization current (INEU-O(I)) into each differential amplifier in the pair of differential amplifiers (54, 56) to thereby suppress a modulated leakage current (iBc-o(t)) caused by the modulated voltage in each differential amplifier in the pair of differential amplifiers (54, 56).

12. The wireless device of claim 11 , wherein: the pair of differential amplifiers each comprises a heterojunction bipolar transistor, HBT, having a base electrode coupled to the interstage transformer via a blocking capacitor, a collector electrode coupled to the output transformer to receive the modulated voltage, and an emitter electrode coupled to a ground; and the neutralization circuit is further configured to inject the output-stage neutralization current into the base electrode of the HBT in each differential amplifier in the pair of differential amplifiers to thereby suppress the modulated leakage current collectively caused by the modulated voltage and an equivalent capacitance of the HBT in each differential amplifier in the pair of differential amplifiers.

13. The wireless device of claim 12, wherein the neutralization circuit is further configured to inject the output-stage neutralization current in an opposite direction from the modulated leakage current flowing through the HBT in each differential amplifier in the pair of differential amplifiers.

14. The wireless device (100) of claim 1 1 , wherein the neutralization circuit (60) is coupled between a center tap (62) of the interstage transformer (52) and the center tap (64) of the output transformer (58) and configured to: receive the modulated voltage via the center tap (64) of the output transformer (58); derive the output-stage neutralization current from the modulated voltage; and inject the output-stage neutralization current into the center tap (62) of the interstage transformer (52).

15. The wireless device (100) of claim 14, wherein the neutralization circuit (60) comprises: one of a heterojunction bipolar transistor, HBT, (66) and a capacitor configured to derive an emitter neutralization current (INEU-S(I)) from the modulated voltage; and a mirroring circuit (68) configured to amplify at least the emitter neutralization current (iNEu-s(t)) to thereby generate and inject the amplified output-stage neutralization current into the center tap of the interstage transformer.

16. The wireless device (100) of claim 14, wherein the neutralization circuit (60) comprises: a heterojunction bipolar transistor, HBT, (66) configured to derive an emitter neutralization current (INEU-S( ) from the modulated voltage; and a common stage circuit (70) configured to amplify at least the emitter neutralization current (iNEu-s(t)) to thereby generate and inject the amplified output-stage neutralization current into the center tap of the interstage transformer.

17. The wireless device (100) of claim 15 or 16, wherein the differential power amplifier circuit (38A, 38B, 38C) further comprises an input stage (46) coupled to the interstage transformer (52), wherein the neutralization circuit (60) is further configured to: derive an interstage neutralization current (INEU-I(I)) from the modulated voltage; and amplify a sum of the emitter neutralization current (iNEu-s(t)) and the interstage neutralization current (INEU-I(I)) to thereby generate and inject the interstage neutralization current (INEU-I(I)) into the center tap (62) of the interstage transformer (52) to thereby suppress an extra leakage current caused by a coupling capacitance between the input stage (46) and the output stage (48, 48A).

18. The wireless device (100) of claim 1 1 , wherein: the output stage (48A) further comprises a divider network (74) coupled in parallel to the output transformer (58) and configured to divide the modulated voltage received via the collector node (44); and the neutralization circuit (60) is coupled between a center point (76) of the divider network (74) and a center tap (62) of the interstage transformer (52), the neutralization circuit (60) is configured to: receive the modulated voltage via the center point (76) of the divider network (74); derive the output-stage neutralization current from the modulated voltage; and inject the output-stage neutralization current into the center tap (62) of the interstage transformer (52).

19. A method for neutralizing memory distortion in a differential power amplifier circuit (38A, 38B, 38C) comprising: receiving a modulated voltage (VPA(I)) and a radio frequency, RF, signal (50); amplifying the RF signal (50) based on the modulated voltage; outputting the RF signal (50) amplified by each of the differential amplifiers in the pair of differential amplifiers (54, 56); and injecting an output-stage neutralization current (iNEu-o(t)) into each differential amplifier in the pair of differential amplifiers (54, 56) to thereby suppress a modulated leakage current (iBc-o(t)) caused by the modulated voltage in each differential amplifier in the pair of differential amplifiers (54, 56).

20. The method of claim 19, wherein: receiving the modulated voltage comprises receiving the modulated voltage via a collector node (44) coupled to a power management integrated circuit, PMIC, (40); receiving the RF signal (50) comprises receiving the RF signal (50) via an interstage transformer (52); amplifying the RF signal (50) comprises amplifying the RF signal (50) using a pair of differential amplifiers (54, 56) each coupled to the interstage transformer (52); outputting the RF signal (50) comprises outputting the RF signal (50) from an output transformer (58) coupled to each differential amplifier in the pair of differential amplifiers (54, 56) and having a center tap (64) coupled to the collector node (44) to receive the modulated voltage; and injecting the output-stage neutralization current (iNEu-o(t)) into each differential amplifier in the pair of differential amplifiers (54, 56) comprises injecting the output-stage neutralization current (INEU -o(t)) using a neutralization circuit (60) coupled between the interstage transformer (52) and the output transformer (58).