EP4646719A1

EP4646719A1 - Scan circuit and display apparatus

Info

Publication number: EP4646719A1
Application number: EP23957082.3A
Authority: EP
Inventors: Lu Bai; Junxiu DAI; Weishu WEN; Lei He; Daiying ZHANG; Guowei Zhao; Bo Zhang; Yi Qu; Yang Zhou; Haigang Qing
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2023-10-31
Filing date: 2023-10-31
Publication date: 2025-11-12
Also published as: CN120239879A; WO2025091202A1; EP4646719A4

Abstract

A scan circuit includes a first clock signal line (CKL); a second clock signal line (CBL); and in a region including multiple scan units and one or more dummy scan units (DSU), a first scan unit(SU1), a first dummy scan unit (DSU1), and a second scan unit (SU2) sequentially arranged. A respective scan unit includes a first pad(PAD1) and a second pad (PAD2). The first pad (PAD1) includes a gate electrode (G7) of a seventh transisto r(T7). The second pad (PAD2) includes a gate electrode (G1) of a first transistor (T1) and a gate electrode (G3) of a third transistor (T3). A first dummy scan unit (DSU1) includes a first dummy extension (DE1). The first dummy extension (DE1) is connected to the second pad (PAD2) in the second scan unit (SU2), configured to transmit one of a first clock signal (CK) or a second clock signal (CB) to the gate electrode (G1) of the first transistor (T1) and the gate electrode (G3) of the third transistor (T3) in the second scan unit (SU2).

Description

SCAN CIRCUIT AND DISPLAY APPARATUS

TECHNICAL FIELD

The present invention relates to display technology, more particularly, to a scan circuit and a display apparatus.

BACKGROUND

Image display apparatuses include a driver for controlling image display in each of a plurality of pixels. The driver is a transistor-based circuit including a gate driving circuit and a data driving circuit. The gate driving circuit is formed by cascading multiple units of shift register units. Each shift register unit outputs a gate driving signal to one of a plurality of gate lines. The gate driving signals from the gate driving circuit scan through gate lines row by row, controlling each row of transistors to be in on/off states. The gate drive circuit can be integrated into a gate-on-array (GOA) circuit, which can be formed directly in the array substrate of the display panel.

SUMMARY

In one aspect, the present disclosure provides a scan circuit, comprising a first clock signal line; a second clock signal line; and in a region comprising multiple scan units and one or more dummy scan units, a first scan unit, a first dummy scan unit, and a second scan unit sequentially arranged; wherein a respective scan unit comprises a first pad and a second pad; the first pad comprises a gate electrode of a seventh transistor; the second pad comprises a gate electrode of a first transistor and a gate electrode of a third transistor; the first dummy scan unit comprises a first dummy extension; the first dummy extension is connected to the second pad in the second scan unit, configured to transmit one of a first clock signal or a second clock signal to the gate electrode of the first transistor and the gate electrode of the third transistor in the second scan unit; and an orthographic projection of the first dummy extension on a base substrate at least partially overlaps with at least one of an orthographic projection of the first clock signal line on the base substrate or an orthographic projection of the second clock signal line on the base substrate.
Optionally, the first dummy extension is connected to one of the first clock signal line or the second clock signal line at a position in an area having the first dummy scan unit.
Optionally, the first dummy extension in the first dummy scan unit is further connected to a first electrode of a second transistor in the second scan unit, configured to transmit the one of the first clock signal or the second clock signal to the first electrode of the second transistor in the second scan unit.
Optionally, the second scan unit comprises a second extension connected to the first pad in the second scan unit; wherein the first pad in the second scan unit comprises the gate electrode of the seventh transistor in the second scan unit; and the second extension in the second scan unit is connected to another of the first clock signal line or the second clock signal line, configured to transmit another of the first clock signal or the second clock signal to the gate electrode of the seventh transistor in the second scan unit.
Optionally, the first pad in the second scan unit is connected to a first electrode of a fifth transistor in the second scan unit; and the second extension in the second scan unit is configured to transmit the another of the first clock signal or the second clock signal to the first electrode of the fifth transistor in the second scan unit through the first pad in the second scan unit.
Optionally, the second extension in the second scan unit is connected to a first electrode of a fourth transistor and a first electrode of a sixth transistor in the second scan unit, configured to transmit the another of the first clock signal or the second clock signal to the first electrode of the fourth transistor and the first electrode of the sixth transistor in the second scan unit.
Optionally, the first scan unit comprises a first extension connected to the first pad in the first scan unit; wherein the first pad in the first scan unit comprises the gate electrode of the seventh transistor in the first scan unit; the first pad in the first scan unit is connected to a first electrode of a fifth transistor in the first scan unit; and the first extension in the first scan unit is connected to the one of the first clock signal line or the second clock signal line, configured to transmit the one of the first clock signal or the second clock signal to the gate electrode of the seventh transistor and the first electrode of the fifth transistor in the first scan unit.
Optionally, the first pad in the first scan unit is connected to the first electrode of the fifth transistor in the first scan unit; and the first extension in the first scan unit is configured to transmit the one of the first clock signal or the second clock signal to the first electrode of the fifth transistor in the first scan unit through the first pad in the first scan unit.
Optionally, the first extension in the first scan unit is connected to a first electrode of a fourth transistor and a first electrode of a sixth transistor in the first scan unit, configured to transmit another of the first clock signal or the second clock signal to the first electrode of the fourth transistor and the first electrode of the sixth transistor in the first scan unit.
Optionally, the first dummy scan unit further comprises a first dummy pad; the first dummy pad in the first dummy scan unit comprises a dummy gate electrode of a seventh dummy transistor; and the first dummy extension is connected to the first dummy pad.
Optionally, the first dummy pad in the first dummy scan unit is disconnected from a dummy first electrode of a fifth dummy transistor in the first dummy scan unit; the dummy first electrode and a dummy second electrode of the fifth dummy transistor, and a dummy first electrode and a dummy second electrode of a fourth dummy transistor, in the first dummy scan unit, are parts of a unitary structure; and the unitary structure is configured to be provided with a second power supply signal.
Optionally, the first dummy extension in the first dummy scan unit is disconnected from a dummy second electrode of a ninth dummy transistor in the first dummy scan unit; a dummy first electrode and the dummy second electrode of the ninth dummy transistor in the first dummy scan unit are parts of a unitary structure; and the unitary structure is configured to be provided with a second power supply signal.
Optionally, the first extension in the first scan unit is not connected to any component of dummy transistors or dummy capacitors in any dummy scan units; and the first extension in the first scan unit is not connected to any component of transistors or capacitors in the second scan unit.
Optionally, in the region comprising multiple scan units and one or more dummy scan units, the scan circuit further comprises a second dummy scan unit; wherein the first scan unit, the second dummy scan unit, the first dummy scan unit, and the second scan unit are sequentially arranged.
Optionally, the second dummy scan unit is electrically isolated from the first clock signal line and electrically isolated from the second clock signal line.
Optionally, the second dummy scan unit comprises a second dummy extension in the second dummy scan unit; and the second dummy extension in the second dummy scan unit is electrically isolated from the first clock signal line and electrically isolated from the second clock signal line.
Optionally, the second dummy scan unit further comprises a first dummy pad connected to the second dummy extension in the second dummy scan unit; and the first dummy pad and the second dummy extension in the second dummy scan unit is electrically isolated from the first clock signal line and electrically isolated from the second clock signal line.
Optionally, the second dummy extension in the second dummy scan unit is not connected to any component of dummy transistors or dummy capacitors in the first dummy scan unit; and the second dummy extension in the second dummy scan unit is not connected to any components of transistors or capacitors in the first scan unit or the second scan unit.
Optionally, the first dummy pad in the second dummy scan unit is connected to a dummy first electrode of a fifth dummy transistor in the second dummy scan unit; the dummy first electrode and a dummy second electrode of the fifth dummy transistor, and a dummy first electrode and a dummy second electrode of a fourth dummy transistor, in the second dummy scan unit, are parts of a unitary structure; and the unitary structure is configured to be provided with a second power supply signal.
In another aspect, the present disclosure provides a scan circuit, comprising a first clock signal line; a second clock signal line; and in a region comprising multiple scan units and one or more dummy scan units, a first scan unit, a first dummy scan unit, and a second scan unit sequentially arranged; wherein a respective scan unit comprises a first pad; the first pad comprises a gate electrode of a seventh transistor; the scan circuit further comprises a second extension; the second extension is connected to one of the first clock signal line or the second clock signal line at a position in an area having the first dummy scan unit; and the second extension is connected to the first pad in a second scan circuit, configured to transmit one of a first clock signal or a second clock signal to the gate electrode of the seventh transistor.
In another aspect, the present disclosure provides a display apparatus, comprising the scan circuit described herein, and a display panel connected to the scan circuit.
BRIEF DESCRIPTION OF THE FIGURES
The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present invention.
FIG. 1 is a circuit diagram of a respective scan unit of a scan circuit in some embodiments according to the present disclosure.
FIG. 2 is a timing diagram illustrating an operation of the respective scan unit illustrated in FIG. 1.
FIG. 3 is a circuit diagram of a respective scan unit of a scan circuit in some embodiments according to the present disclosure.
FIG. 4 is a timing diagram illustrating an operation of the respective scan unit illustrated in FIG. 3.
FIG. 5 is a circuit diagram of a respective scan unit of a scan circuit in some embodiments according to the present disclosure.
FIG. 6 is a circuit diagram of a respective scan unit of a scan circuit in some embodiments according to the present disclosure.
FIG. 7 is a circuit diagram of a respective scan unit of a scan circuit in some embodiments according to the present disclosure.
FIG. 8 is a circuit diagram of a respective scan unit of a scan circuit in some embodiments according to the present disclosure.
FIG. 9 is a plan view of an array substrate in some embodiments according to the present disclosure.
FIG. 10A is a circuit diagram illustrating the structure of a pixel driving circuit in some embodiments according to the present disclosure.
FIG. 10B is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.
FIG. 11 is a diagram illustrating one or more scan circuits in a display apparatus in some embodiments according to the present disclosure.
FIG. 12 is a diagram illustrating a first scan circuit in a display apparatus in some embodiments according to the present disclosure.
FIG. 13 is a diagram illustrating a second scan circuit in a display apparatus in some embodiments according to the present disclosure.
FIG. 14A is a diagram illustrating the structure of multiple scan units in multiple rows of a scan circuit in some embodiments according to the present disclosure.
FIG. 14B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 14A.
FIG. 14C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 14A.
FIG. 14D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 14A.
FIG. 14E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 14A.
FIG. 14F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 14A.
FIG. 14G is a diagram illustrating the connectivity of a first connecting line and a second connecting line in the scan circuit depicted in FIG. 14A.
FIG. 15A is a diagram illustrating the structure of multiple scan units in multiple rows of a scan circuit in some embodiments according to the present disclosure.
FIG. 15B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 15A.
FIG. 15C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 15A.
FIG. 15D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 15A.
FIG. 15E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 15A.
FIG. 15F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 15A.
FIG. 15G is a diagram illustrating the structure of a third signal line layer in the scan circuit depicted in FIG. 15A.
FIG. 15H is a diagram illustrating the connectivity of a first connecting line and a second connecting line in the scan circuit depicted in FIG. 15A.
FIG. 16A is a diagram illustrating the structure of multiple scan units in multiple rows of a scan circuit in some embodiments according to the present disclosure.
FIG. 16B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 16A.
FIG. 16C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 16A.
FIG. 16D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 16A.
FIG. 16E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 16A.
FIG. 16F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 16A.
FIG. 16G is a diagram illustrating the structure of a third signal line layer in the scan circuit depicted in FIG. 16A.
FIG. 17A is a diagram illustrating the structure of multiple scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scan circuit in some embodiments according to the present disclosure.
FIG. 17B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 17A.
FIG. 17C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 17A.
FIG. 17D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 17A.
FIG. 17E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 17A.
FIG. 17F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 17A.
FIG. 17G is a diagram illustrating the connectivity of a first connecting line in the scan circuit depicted in FIG. 17A.
FIG. 18A is a diagram illustrating the structure of multiple scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scan circuit in some embodiments according to the present disclosure.
FIG. 18B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 18A.
FIG. 18C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 18A.
FIG. 18D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 18A.
FIG. 18E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 18A.
FIG. 18F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 18A.
FIG. 18G is a diagram illustrating the structure of a third signal line layer in the scan circuit depicted in FIG. 18A.
FIG. 18H is a diagram illustrating the connectivity of a first connecting line in the scan circuit depicted in FIG. 18A.
FIG. 19A is a diagram illustrating the structure of multiple scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scan circuit in some embodiments according to the present disclosure.
FIG. 19B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 19A.
FIG. 19C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 19A.
FIG. 19D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 19A.
FIG. 19E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 19A.
FIG. 19F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 19A.
FIG. 19G is a diagram illustrating the structure of a third signal line layer in the scan circuit depicted in FIG. 19A.
FIG. 20 is a diagram illustrating the structure of a portion of one or more scan circuits in some embodiments according to the present disclosure.
FIG. 21A is a diagram illustrating the structure of multiple scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scan circuit in some embodiments according to the present disclosure.
FIG. 21B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 21A.
FIG. 21C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 21A.
FIG. 21D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 21A.
FIG. 21E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 21A.
FIG. 21F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 21A.
FIG. 21G is a diagram illustrating the connectivity of a first clock signal line and a second clock signal line in the scan circuit depicted in FIG. 21A.
FIG. 22A is a diagram illustrating the structure of multiple scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scan circuit in some embodiments according to the present disclosure.
FIG. 22B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 22A.
FIG. 22C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 22A.
FIG. 22D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 22A.
FIG. 22E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 22A.
FIG. 22F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 22A.
FIG. 22G is a diagram illustrating the structure of a third signal line layer in the scan circuit depicted in FIG. 22A.
FIG. 22H is a diagram illustrating the connectivity of a first clock signal line and a second clock signal line in the scan circuit depicted FIG. 22A.
FIG. 23A is a diagram illustrating the structure of multiple scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scan circuit in some embodiments according to the present disclosure.
FIG. 23B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 23A.
FIG. 23C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 23A.
FIG. 23D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 23A.
FIG. 23E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 23A.
FIG. 23F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 23A.
FIG. 23G is a diagram illustrating the structure of a third signal line layer in the scan circuit depicted in FIG. 23A.
FIG. 23H is a diagram illustrating the connectivity of a first clock signal line in the scan circuit depicted FIG. 23A.

DETAILED DESCRIPTION

The disclosure will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of some embodiments are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
The present disclosure provides, inter alia, a scan circuit and a display apparatus that substantially obviate one or more of the problems due to limitations and disadvantages of the related art. In one aspect, the present disclosure provides a scan circuit. In some embodiments, the scan circuit includes a first clock signal line; a second clock signal line; and in a region comprising multiple scan units and one or more dummy scan units, a first scan unit, a first dummy scan unit, and a second scan unit sequentially arranged. Optionally, a respective scan unit comprises a first pad and a second pad. Optionally, the first pad comprises a gate electrode of a seventh transistor. Optionally, the second pad comprises a gate electrode of a first transistor and a gate electrode of a third transistor. Optionally, a first dummy scan unit comprises a first dummy extension. Optionally, the first dummy extension is connected to the second pad in the second scan unit, configured to transmit one of a first clock signal or a second clock signal to the gate electrode of the first transistor and the gate electrode of the third transistor in the second scan unit. Optionally, an orthographic projection of the first dummy extension on a base substrate at least partially overlaps with at least one of an orthographic projection of the first clock signal line on the base substrate or an orthographic projection of the second clock signal line on the base substrate.
In some embodiments, the present disclosure provides one or more scan circuits. A respective scan circuit of the one or more scan circuits includes a plurality of stages of cascaded scan units. Optionally, the plurality of stages of cascaded scan units are configured to provide a plurality of control signals (e.g., gate scanning signals, reset control signals, or light emission control signals) to a plurality of rows of subpixels. Examples of scan circuits include a light emitting control signal generating circuit configured to generate light emitting control signals for subpixels in the array substrate, a reset control signal generating circuit configured to generate reset control signals for subpixels in the array substrate, and a gate scanning signal generating circuit configured to generate gate scanning signals for subpixels in the array substrate.
FIG. 1 is a circuit diagram of a respective scan unit of a scan circuit in some embodiments according to the present disclosure. Referring to FIG. 1, the respective scan unit in some embodiments includes a first transistor T1 to an eighth transistor T8, a first capacitor C1 and a second capacitor C2. In some embodiments, a gate electrode of the first transistor T1 is electrically connected to a second terminal TM2 configured to provide a first clock signal CK, a first electrode of the first transistor T1 is electrically connected to an input terminal TM1 configured to provide a start signal STV or an output signal Outp from an output terminal of a previous scan unit, a second electrode of the first transistor T1 is electrically connected to a first node N1; a gate electrode of the second transistor T2 is electrically connected to the first node N1, a first electrode of the second transistor T2 is electrically connected to the second terminal TM2 configured to provide the first clock signal CK, the second electrode of the second transistor T2 is electrically connected to a second node N2; a gate electrode of the third transistor T3 is electrically connected to the second terminal TM2 configured to provide the first clock signal CK, a first electrode of the third transistor T3 is electrically connected to a first power supply signal VGL, a second electrode of the third transistor T3 is electrically connected to the second node N2; a gate electrode of the fourth transistor T4 is electrically connected to the second node N2, a first electrode of the fourth transistor T4 is electrically connected to a second power supply signal VGH, a second electrode of the fourth transistor T4 is electrically connected to an output terminal TM4 configured to output an output signal Outc; a gate electrode of the fifth transistor T5 is electrically connected to a third node N3, a first electrode of the fifth transistor T5 is electrically connected to a third terminal TM3 configured to provide a second clock signal CB, a second electrode of the fifth transistor T5 is electrically connected to the output terminal TM4 configured to output the output signal Outc; a gate electrode of the sixth transistor T6 is electrically connected to the second node N2, a first electrode of the sixth transistor T6 is electrically connected to the second power supply signal VGH, a second electrode of the sixth transistor T6 is electrically connected to a first electrode of a seventh transistor T7; a gate electrode of the seventh transistor T7 is electrically connected to the third terminal TM3 configured to provide the second clock signal CB, a second electrode of the seventh transistor T7 is electrically connected to the first node N1; a gate electrode of the eighth transistor T8 is electrically connected to a first power supply signal VGL, a first electrode of the eighth transistor T8 is electrically connected to the first node N1, a second electrode of the eighth transistor T8 is electrically connected to the third node N3; a first capacitor electrode C11 of a first capacitor C1 is electrically connected to the second node N2, a second capacitor electrode C12 of the first capacitor C1 is electrically connected to the second power supply signal VGH; and a first capacitor electrode C21 of a second capacitor C2 is electrically connected to the third node N3, and a second capacitor electrode C22 of the second capacitor C2 is electrically connected to the output terminal TM4 configured to output the output signal Outc. In one example, the first transistor T1 to the eighth transistor T8 may be a p-type transistor or may be an n-type transistor. In another example, the second power supply signal VGH provides a continuous high level signal and the first power supply signal VGL provides a continuous low level signal.
FIG. 2 is a timing diagram illustrating an operation of the respective scan unit illustrated in FIG. 1. Referring to FIG. 2, the operation of the respective scan unit in some embodiments includes a first period p1, a second period p2, a third period p3, a fourth period p4, and a fifth period p5.
In some embodiments, during a first period p1, the first clock signal CK is provided to the second input terminal TM2. The first transistor T1 and the third transistor T3 are turned on.Furthermore, during the first period p1, the second clock signal CB is not provided to the third input terminal TM3, the seventh transistor T7 is turned off.
In some embodiments, during the first period p1, the first transistor T1 is turned on, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is provided to the input terminal TM1, and passes from a first electrode of the first transistor T1 to a second electrode of the first transistor T1. The start signal STV or the output signal Outp from the output terminal of the previous scan unit is applied to the first node N1. When the first node N1 is set to the voltage level of the start signal STV or the output signal Outp from the output terminal of the previous scan unit, the second transistor T2 is turned on.
In some embodiments, when the second transistor T2 is turned on, the voltage of the first clock signal CK is provided to the second node N2. The fourth transistor T4 and the sixth transistor T6 are turned on.
In some embodiments, when the third transistor T3 is turned on, the voltage of the first power supply signal VGL is provided to the second node N2. The fourth transistor T4 and the sixth transistor T6 are turned on.
In some embodiments, when the fourth transistor T4 is turned on, the voltage of the second power supply signal VGH is provided to the output terminal TM4. The voltage of the second power supply signal VGH is an ineffective voltage. During the first period p1, an ineffective voltage of the gate driving signal is provided to the n-th stage gate line of N number of stages of gate lines, n and N being positive integers, 1 ≤ n ≤ N.
In some embodiments, when the first transistor T1 is turned on, the start signal STV or the output signal Outp from the output terminal of the previous scan unit passes through the first transistor T1 and the eighth transistor T8, and the fifth transistor T5 is turned on. During the first period p1, the second clock signal CB is not provided to the third input terminal TM3, and is not provided to the output terminal TM4. During the first period p1, an effective voltage of the gate driving signal is not provided to the n-th stage gate line.
In some embodiments, during a second period p2, the supply of the first clock signal CK to the second input terminal TM2 is interrupted. The first transistor T1 and the third transistor T3 are turned off. The first node N1 maintains the voltage of the preceding period. Since the first node N1 remains in the effective voltage level (e.g., a low voltage level) , the second transistor T2 remains turned on. Although the second transistor T2 is turned on, during the second period p2, the supply of the first clock signal CK to the second input terminal TM2 is interrupted. Thus, the fourth transistor T4 and the sixth transistor T6 are turned off. When the fourth transistor T4 is turned off, the voltage of the second power supply signal VGH is not provided to the output terminal TM4.
In some embodiments, during the second period p2, the second clock signal CB is provided to the third input terminal TM3. The seventh transistor T7 is turned on by the second clock signal CB provided to the third input terminal TM3. During the second period p2, the first node N1 maintains the voltage of the preceding period. The voltage (e.g., an effective voltage) at the first node N1 turns on the fifth transistor T5. During the second period p2, the second clock signal CB passes through the fifth transistor T5, is provided to the output terminal TM4, and is provided to the n-th stage gate line as the gate driving signal.
In some embodiments, during a third period p3, the supply of the second clock signal CB to the third input terminal TM3 is interrupted. When the supply of the second clock signal CB is interrupted, the seventh transistor T7 is turned off.
In some embodiments, during the third period p3, the first clock signal CK is provided to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the first transistor T1 and the third transistor T3 are turned on. During the third period p3, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is interrupted.
In some embodiments, when the third transistor T3 is turned on, the voltage of the first power supply signal VGL is provided to the second node N2. The fourth transistor T4 and the sixth transistor T6 are turned on. When the fourth transistor T4 is turned on, the voltage of the second power supply signal VGH is provided to the output terminal TM4. The voltage of the second power supply signal VGH is an ineffective voltage. During the third period p3, an ineffective voltage of the gate driving signal is provided to the n-th stage gate line.
During the third period p3, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is interrupted. In some embodiments, when the first transistor T1 is turned on, the first node N1 maintains an ineffective voltage level (e.g., a high voltage level) . The fifth transistor T5 is turned off. During the third period p3, the second clock signal CB is not provided to the output terminal TM4, and is not provided to the n-th stage gate line as the gate driving signal.
In some embodiments, during a fourth period p4, the second clock signal CB may be provided to the third input terminal TM3. When the second clock signal CB is provided to the third input terminal TM3, the seventh transistor T7 is turned on. During the fourth period p4, the supply of the first clock signal CK to the second input terminal TM2 is interrupted, the first transistor T1 and the third transistor T3 are turned off. During the fourth period p4, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is interrupted. In some embodiments, when the first transistor T1 is turned off, the first node N1 maintains the voltage of the preceding period. An ineffective voltage at the first node N1 turns off the fifth transistor T5. During the fourth period p4, the second clock signal CB is not provided to the output terminal TM4, and is not provided to the n-th stage gate line as the gate driving signal.
In some embodiments, during a fifth period p5, the supply of the second clock signal CB to the third input terminal TM3 is interrupted, the first clock signal CK is provided to the second terminal TM2. During the fifth period p5, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is interrupted. In some embodiments, when the first transistor T1 is turned on, the first node N1 maintains an ineffective voltage level (e.g., a high voltage level) . The fifth transistor T5 is turned off. During the fifth period p5, the second clock signal CB is not provided to the output terminal TM4, and is not provided to the n-th stage gate line as the gate driving signal.
In some embodiments, during the fifth period p5, when the third transistor T3 is turned on, the voltage of the first power supply signal VGL is provided to the second node N2. The fourth transistor T4 and the sixth transistor T6 are turned on. When the fourth transistor T4 is turned on, the voltage of the second power supply signal VGH is provided to the output terminal TM4. The voltage of the second power supply signal VGH is an ineffective voltage. During the fifth period p5, an ineffective voltage of the gate driving signal is provided to the n-th stage gate line.
FIG. 3 is a circuit diagram of a respective scan unit of a scan circuit in some embodiments according to the present disclosure. Referring to FIG. 3, the respective scan unit in some embodiments includes a first transistor T1 to an eighth transistor T8, a first capacitor C1 and a second capacitor C2. In some embodiments, a gate electrode of the first transistor T1 is electrically connected to a second terminal TM2 configured to provide a second clock signal CB, a first electrode of the first transistor T1 is electrically connected to an input terminal TM1 configured to provide a start signal STV or an output signal Outp from an output terminal of a previous scan unit, a second electrode of the first transistor T1 is electrically connected to a first node N1; a gate electrode of the second transistor T2 is electrically connected to the first node N1, a first electrode of the second transistor T2 is electrically connected to the second terminal TM2 configured to provide the second clock signal CB, the second electrode of the second transistor T2 is electrically connected to a second node N2; a gate electrode of the third transistor T3 is electrically connected to the second terminal TM2 configured to provide the second clock signal CB, a first electrode of the third transistor T3 is electrically connected to a first power supply signal VGL, a second electrode of the third transistor T3 is electrically connected to the second node N2; a gate electrode of the fourth transistor T4 is electrically connected to the second node N2, a first electrode of the fourth transistor T4 is electrically connected to a second power supply signal VGH, a second electrode of the fourth transistor T4 is electrically connected to an output terminal TM4 configured to output an output signal Outc; a gate electrode of the fifth transistor T5 is electrically connected to a third node N3, a first electrode of the fifth transistor T5 is electrically connected to a third terminal TM3 configured to provide a first clock signal CK, a second electrode of the fifth transistor T5 is electrically connected to the output terminal TM4 configured to output the output signal Outc; a gate electrode of the sixth transistor T6 is electrically connected to the second node N2, a first electrode of the sixth transistor T6 is electrically connected to the second power supply signal VGH, a second electrode of the sixth transistor T6 is electrically connected to a first electrode of a seventh transistor T7; a gate electrode of the seventh transistor T7 is electrically connected to the third terminal TM3 configured to provide the first clock signal CK, a second electrode of the seventh transistor T7 is electrically connected to the first node N1; a gate electrode of the eighth transistor T8 is electrically connected to a first power supply signal VGL, a first electrode of the eighth transistor T8 is electrically connected to the first node N1, a second electrode of the eighth transistor T8 is electrically connected to the third node N3; a first capacitor electrode C11 of a first capacitor C1 is electrically connected to the second node N2, a second capacitor electrode C12 of the first capacitor C1 is electrically connected to the second power supply signal VGH; and a first capacitor electrode C21 of a second capacitor C2 is electrically connected to the third node N3, and a second capacitor electrode C22 of the second capacitor C2 is electrically connected to the output terminal TM4 configured to output the output signal Outc. In one example, the first transistor T1 to the eighth transistor T8 may be a p-type transistor or may be an n-type transistor. In another example, the second power supply signal VGH provides a continuous high level signal and the first power supply signal VGL provides a continuous low level signal.
FIG. 4 is a timing diagram illustrating an operation of the respective scan unit illustrated in FIG. 3. Referring to FIG. 4, the operation of the respective scan unit in some embodiments includes a first period p1, a second period p2, a third period p3, a fourth period p4, and a fifth period p5.
In some embodiments, during a first period p1, the second clock signal CB is not provided to the second input terminal TM2. The first transistor T1 and the third transistor T3 are turned off. Furthermore, during the first period p1, the first clock signal CK is provided to the third input terminal TM3, the seventh transistor T7 is turned on.
In some embodiments, during a first period p1, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is not provided to the input terminal TM1. The fifth transistor T5 is turned off. The first clock signal CK does not pass through the fifth transistor T5, an effective voltage of the gate driving signal is not provided to the n-th stage gate line.
In some embodiments, during a first period p1, the third transistor T3 is turned off. The first power supply signal VGL does not pass through the third transistor T3. The fourth transistor T4 is turned off.
In some embodiments, during the second period p2, the supply of the first clock signal CK to the third input terminal TM3 is interrupted. The second clock signal CB is provided to the second input terminal TM2, the first transistor T1 and the third transistor T3 are turned on. The start signal STV or the output signal Outp from the output terminal of the previous scan unit is provided to the input terminal TM1, and passes from a first electrode of the first transistor T1 to a second electrode of the first transistor T1. The start signal STV or the output signal Outp from the output terminal of the previous scan unit is applied to the first node N1. When the first node N1 is set to the voltage level of the start signal STV or the output signal Outp from the output terminal of the previous scan unit, the second transistor T2 is turned on.
In some embodiments, when the second transistor T2 is turned on, the voltage of the second clock signal CB is provided to the second node N2. The fourth transistor T4 and the sixth transistor T6 are turned on.
In some embodiments, when the third transistor T3 is turned on, the voltage of the first power supply signal VGL is provided to the second node N2. The fourth transistor T4 and the sixth transistor T6 are turned on.
In some embodiments, when the fourth transistor T4 is turned on, the voltage of the second power supply signal VGH is provided to the output terminal TM4. The voltage of the second power supply signal VGH is an ineffective voltage. During the second period p2, an ineffective voltage of the gate driving signal is provided to the n-th stage gate line.
In some embodiments, when the first transistor T1 is turned on, the start signal STV or the output signal Outp from the output terminal of the previous scan unit passes through the first transistor T1 and the eighth transistor T8, and the fifth transistor T5 is turned on. During the second period p2, the first clock signal CK is not provided to the third input terminal TM3, and is not provided to the output terminal TM4. During the second period p2, an effective voltage of the gate driving signal is not provided to the n-th stage gate line.
In some embodiments, during a third period p3, the supply of the second clock signal CB to the second input terminal TM2 is interrupted. The first transistor T1 and the third transistor T3 are turned off. The first node N1 maintains the voltage of the preceding period. Since the first node N1 remains in the effective voltage level (e.g., a low voltage level) , the second transistor T2 remains turned on. Although the second transistor T2 is turned on, during the third period p3, the supply of the second clock signal CB to the second input terminal TM2 is interrupted. Thus, the fourth transistor T4 and the sixth transistor T6 are turned off. When the fourth transistor T4 is turned off, the voltage of the second power supply signal VGH is not provided to the output terminal TM4.
In some embodiments, during the third period p3, the first clock signal CK is provided to the third input terminal TM3. The seventh transistor T7 is turned on by the first clock signal CK provided to the third input terminal TM3. During the third period p3, the first node N1 maintains the voltage of the preceding period. The voltage (e.g., an effective voltage) at the first node N1 turns on the fifth transistor T5. During the third period p3, the first clock signal CK passes through the fifth transistor T5, is provided to the output terminal TM4, and is provided to the n-th stage gate line as the gate driving signal.
In some embodiments, during a fourth period p4, the supply of the first clock signal CK to the third input terminal TM3 is interrupted. When the supply of the first clock signal CK is interrupted, the seventh transistor T7 is turned off.
In some embodiments, during the fourth period p4, the second clock signal CB is provided to the second input terminal TM2. When the second clock signal CB is provided to the second input terminal TM2, the first transistor T1 and the third transistor T3 are turned on. During the fourth period p4, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is interrupted.
In some embodiments, when the third transistor T3 is turned on, the voltage of the first power supply signal VGL is provided to the second node N2. The fourth transistor T4 and the sixth transistor T6 are turned on. When the fourth transistor T4 is turned on, the voltage of the second power supply signal VGH is provided to the output terminal TM4. The voltage of the second power supply signal VGH is an ineffective voltage. During the fourth period p4, an ineffective voltage of the gate driving signal is provided to the n-th stage gate line.
During the fourth period p4, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is interrupted. In some embodiments, when the first transistor T1 is turned on, the first node N1 maintains an ineffective voltage level (e.g., a high voltage level) . The fifth transistor T5 is turned off. During the fourth period p4, the first clock signal CK is not provided to the output terminal TM4, and is not provided to the n-th stage gate line as the gate driving signal.
In some embodiments, during a fifth period p5, the first clock signal CK may be provided to the third input terminal TM3. When the first clock signal CK is provided to the third input terminal TM3, the seventh transistor T7 is turned on. During the fifth period p5, the supply of the second clock signal CB to the second input terminal TM2 is interrupted, the first transistor T1 and the third transistor T3 are turned off. During the fifth period p5, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is interrupted. In some embodiments, when the first transistor T1 is turned off, the first node N1 maintains the voltage of the preceding period. An ineffective voltage at the first node N1 turns off the fifth transistor T5. During the fifth period p5, the first clock signal CK is not provided to the output terminal TM4, and is not provided to the n-th stage gate line as the gate driving signal.
Comparing the respective scan unit depicted in FIG. 1 and FIG. 2 with the respective scan unit depicted in FIG. 3 and FIG. 4, the gate driving signal output from the respective scan unit depicted in FIG. 3 and FIG. 4 is out of phase with respect to the gate driving signal output from the respective scan unit depicted in FIG. 1 and FIG. 2.
The present disclosure may be implemented in scan circuit having transistors of various types, including a scan circuit having p-type transistors, a scan circuit having n-type transistors, and a scan circuit having one or more p-type transistors and one or more n-type transistors. For a p-type transistor, an effective control signal (e.g., a turn-on control signal) is a low voltage signal, and an ineffective control signal (e.g., a turn-off control signal) is a high voltage signal. For an n-type transistor, an effective control signal (e.g., a turn-on control signal) is a high voltage signal, and an ineffective control signal (e.g., a turn-off control signal) is a low voltage signal. Referring to FIG. 1 and FIG. 3, in some embodiments, all transistors in the respective scan unit of the scan circuit are p-type transistors such as polysilicon transistors.
Various alternative scan circuits may be used in the present disclosure. FIG. 5 is a circuit diagram of a respective scan unit of a scan circuit in some embodiments according to the present disclosure. FIG. 6 is a circuit diagram of a respective scan unit of a scan circuit in some embodiments according to the present disclosure. The respective scan unit depicted in FIG. 5 corresponds to the respective scan unit depicted in FIG. 1 and FIG. 2. The respective scan unit depicted in FIG. 6 corresponds to the respective scan unit depicted in FIG. 3 and FIG. 4. The gate driving signal output from the respective scan unit depicted in FIG. 6 is out of phase with respect to the gate driving signal output from the respective scan unit depicted in FIG. 5.
Referring to FIG. 5, the respective scan unit in some embodiments includes an input subcircuit ISC, an output subcircuit OSC, a first processing subcircuit PSC1, a second processing subcircuit PSC2, a third processing subcircuit PSC3, a first stabilizing subcircuit SSC1, and a second stabilizing subcircuit SSC2.
In some embodiments, the output subcircuit OSC is configured to supply the voltage of a second power supply signal VGH or a first power supply signal VGL to an output terminal TM4 in response to the voltage of a fourth node N4 and the voltage of the first node N1. Optionally, the output subcircuit OSC includes a ninth transistor T9 and a tenth transistor T10.
The ninth transistor T9 is coupled between a second power supply signal VGH and the output terminal TM4. A gate electrode of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 may be turned on or off depending on the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the second power supply signal VGH is provided to the output terminal TM4, which (annotated as Outc in FIG. 5) may be transmitted to an n-th stage gate line and used as a gate driving signal having a gate-on level.
The tenth transistor T10 is coupled between the output terminal TM4 and a first power supply signal VGL. A gate electrode of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 may be turned on or off depending on the voltage of the first node N1. Optionally, when the tenth transistor T10 is turned on, the voltage of the first power supply signal VGL is provided to the output terminal TM4, which (annotated as Outc in FIG. 5) may be provided to an n-th stage gate line and used as a gate driving signal having a gate-off level. In one example, when the gate driving signal has a gate-off level, it may be understood that the gate driving signal is not provided.
In some embodiments, the input subcircuit ISC is configured to control the voltages of the first node N1 in response to signals provided to the first input terminal TM1 and the second input terminal TM2, respectively. Optionally, the input subcircuit ISC includes a first transistor T1.
The first transistor T1 is coupled between the first input terminal TM1 and the first node N1. A gate electrode of the first transistor T1 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the first transistor T1 is turned on to electrically couple the first input terminal TM1 with the first node N1.
In some embodiments, the first processing subcircuit PSC1 is configured to control the voltage of the fourth node N4 in response to the voltage of the first node N1. Optionally, the first processing subcircuit PSC1 includes an eighth transistor T8 and a second capacitor C2.
The eighth transistor T8 is coupled between the second power supply signal VGH and the fourth node N4. A gate electrode of the eighth transistor T8 is coupled to the first node N1. The eighth transistor T8 may be turned on or off depending on the voltage of the first node N1. Optionally, when the eighth transistor T8 is turned on, the voltage of the second power supply signal VGH may be provided to the fourth node N4.
The second capacitor C2 is coupled between the second power supply signal VGH and the fourth node N4. Optionally, the second capacitor C2 is configured to charge a voltage to be applied to the fourth node N4. Optionally, the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.
In some embodiments, the second processing subcircuit PSC2 is coupled to a fifth node N5, and is configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing subcircuit PSC2 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.
A first terminal of the first capacitor C1 is coupled to the fifth node N5, and a second terminal of the first capacitor C1 is coupled to a third node N3 that is a common node between the sixth transistor T6 and the seventh transistor T7.
The sixth transistor T6 is coupled between the third node N3 and the fifth node N5. A gate electrode of the sixth transistor T6 is coupled to the fifth node N5. The sixth transistor T6 may be turned on depending on the voltage of the fifth node N5 so that a voltage corresponding to the second clock signal CB provided to the third input terminal TM3 may be applied to the third node N3.
The seventh transistor T7 is coupled between the fourth node N4 and the third node N3. A gate electrode of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 may be turned on in response to the second clock signal CB provided to the third input terminal TM3, and thus, applies the voltage of the second power supply signal VGH to the third node N3.
In some embodiments, the third processing subcircuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing subcircuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a third capacitor C3.
The fifth transistor T5 is coupled between the second power supply signal VGH and the fourth transistor T4. A gate electrode of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 may be turned on or off depending on the voltage of the second node N2.
The fourth transistor T4 is coupled between the fifth transistor T5 and the third input terminal TM3. A first electrode of the fourth transistor T4 is configured to be provided with the second clock signal CB provided to the third input terminal TM3. A gate electrode of the fourth transistor T4 is coupled to the gate electrode of the tenth transistor T10. A second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5.
The second transistor T2 is coupled between the second node N2 and the second input terminal TM2. A gate electrode of the second transistor T2 is coupled to the first node N1.
The third transistor T3 is coupled between the second node N2 and the first power supply signal VGL. A gate electrode of the third transistor T3 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the third transistor T3 may be turned on so that the voltage of the first power supply signal VGL may be provided to the second node N2.
The third capacitor C3 is coupled between the tenth transistor T10 and the fifth transistor T5. A first capacitor electrode of the third capacitor C3 is coupled to the second electrode of the fifth transistor T5 and the first electrode of the fourth transistor T4. A second capacitor electrode of the third capacitor C3 is coupled to the gate electrode of the fourth transistor T4 and the gate electrode of the tenth transistor T10.
In some embodiments, the first stabilizing subcircuit SSC1 is coupled between the second processing subcircuit PSC2 and the third processing subcircuit PSC3. Optionally, the first stabilizing subcircuit SSC1 is configured to limit a voltage drop width of the second node N2. Optionally, the first stabilizing subcircuit SSC1 includes an eleventh transistor T11.
The eleventh transistor T11 is coupled between the second node N2 and the fifth node N5. A gate electrode of the eleventh transistor T11 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate-on level voltage, the eleventh transistor T11 may always remain turned on. Therefore, the second node N2 and the fifth node N5 may be maintained at the same voltage, and operated as substantially the same node. As used herein, the term “substantially the same” refers to a difference between two values not exceeding 10%of a base value (e.g., one of the two values) , e.g., not exceeding 8%, not exceeding 6%, not exceeding 4%, not exceeding 2%, not exceeding 1%, not exceeding 0.5%, not exceeding 0.1%, not exceeding 0.05%, and not exceeding 0.01%, of the base value.
In some embodiments, the second stabilizing subcircuit SSC2 is coupled between the first node N1 and the output subcircuit OSC. Optionally, the second stabilizing subcircuit SSC2 is configured to limit a voltage drop width of the first node N1. Optionally, the second stabilizing subcircuit SSC2 includes a twelfth transistor T12.
The twelfth transistor T12 is coupled between the first node N1 and a gate electrode of the tenth transistor T10. A gate electrode of the twelfth transistor T12 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate-on level voltage, the twelfth transistor T12 may always remain turned on. Therefore, the first node N1 and the gate electrode of the tenth transistor T10 may be maintained at the same voltage.
In some embodiments, referring to FIG. 5, each of the first to twelfth transistors T1 to T12 may be formed of a p-type transistor. In some embodiments, the gate-on voltage of the first to twelfth transistors T1 to T12 may be set to a low level, and the gate-off voltage thereof may be set to a high level.
In alternative embodiments, each of the first to twelfth transistors T1 to T12 may be formed of an n-type transistor. In some embodiments, the gate-on voltage of the first to twelfth transistors T1 to T12 may be set to a high level, and the gate-off voltage thereof may be set to a low level.
Referring to FIG. 6, the respective scan unit in some embodiments includes an input subcircuit ISC, an output subcircuit OSC, a first processing subcircuit PSC1, a second processing subcircuit PSC2, a third processing subcircuit PSC3, a first stabilizing subcircuit SSC1, and a second stabilizing subcircuit SSC2.
In some embodiments, the output subcircuit OSC is configured to supply the voltage of a second power supply signal VGH or a first power supply signal VGL to an output terminal TM4 in response to voltages of a fourth node N4. Optionally, the output subcircuit OSC includes a ninth transistor T9 and a tenth transistor T10.
The ninth transistor T9 is coupled between a second power supply signal VGH and the output terminal TM4. A gate electrode of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 may be turned on or off depending on the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the second power supply signal VGH is provided to the output terminal TM4, which (annotated as Outc in FIG. 6) may be transmitted to an n-th stage gate line and used as a gate driving signal having a gate-on level.
The tenth transistor T10 is coupled between the output terminal TM4 and a first power supply signal VGL. A gate electrode of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 may be turned on or off depending on the voltage of the first node N1. Optionally, when the tenth transistor T10 is turned on, the voltage of the first power supply signal VGL is provided to the output terminal TM4, which (annotated as Outc in FIG. 6) may be provided to an n-th stage gate line and used as a gate driving signal having a gate-off level. In one example, when the gate driving signal has a gate-off level, it may be understood that the gate driving signal is not provided.
In some embodiments, the input subcircuit ISC is configured to control the voltages of the first node N1 in response to signals provided to the first input terminal TM1 and the second input terminal TM2, respectively. Optionally, the input subcircuit ISC includes a first transistor T1.
The first transistor T1 is coupled between the first input terminal TM1 and the first node N1. A gate electrode of the first transistor T1 is coupled to the second input terminal TM2. When the second clock signal CB is provided to the second input terminal TM2, the first transistor T1 is turned on to electrically couple the first input terminal TM1 with the first node N1.
In some embodiments, the first processing subcircuit PSC1 is configured to control the voltage of the fourth node N4 in response to the voltages of the first node N1. Optionally, the first processing subcircuit PSC1 includes an eighth transistor T8 and a second capacitor C2.
The eighth transistor T8 is coupled between the second power supply signal VGH and the fourth node N4. A gate electrode of the eighth transistor T8 is coupled to the first node N1. The eighth transistor T8 may be turned on or off depending on the voltage of the first node N1. Optionally, when the eighth transistor T8 is turned on, the voltage of the second power supply signal VGH may be provided to the fourth node N4.
The second capacitor C2 is coupled between the second power supply signal VGH and the fourth node N4. Optionally, the second capacitor C2 is configured to charge a voltage to be applied to the fourth node N4. Optionally, the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.
In some embodiments, the second processing subcircuit PSC2 is coupled to a fifth node N5, and is configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing subcircuit PSC2 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.
A first terminal of the first capacitor C1 is coupled to the fifth node N5, and a second terminal of the first capacitor C1 is coupled to a third node N3 that is a common node between the sixth transistor T6 and the seventh transistor T7.
The sixth transistor T6 is coupled between the third node N3 and the fifth node N5. A gate electrode of the sixth transistor T6 is coupled to the fifth node N5. The sixth transistor T6 may be turned on depending on the voltage of the fifth node N5 so that a voltage corresponding to the first clock signal CK provided to the third input terminal TM3 may be applied to the third node N3.
The seventh transistor T7 is coupled between the fourth node N4 and the third node N3. A gate electrode of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 may be turned on in response to the first clock signal CK provided to the third input terminal TM3, and thus, applies the voltage of the second power supply signal VGH to the third node N3.
In some embodiments, the third processing subcircuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing subcircuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a third capacitor C3.
The fifth transistor T5 is coupled between the second power supply signal VGH and the fourth transistor T4. A gate electrode of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 may be turned on or off depending on the voltage of the second node N2.
The fourth transistor T4 is coupled between the fifth transistor T5 and the third input terminal TM3. A first electrode of the fourth transistor T4 is configured to be provided with the first clock signal CK provided to the third input terminal TM3. A gate electrode of the fourth transistor T4 is coupled to the gate electrode of the tenth transistor T10. A second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5.
The second transistor T2 is coupled between the second node N2 and the second input terminal TM2. A gate electrode of the second transistor T2 is coupled to the first node N1.
The third transistor T3 is coupled between the second node N2 and the first power supply signal VGL. A gate electrode of the third transistor T3 is coupled to the second input terminal TM2. When the second clock signal CB is provided to the second input terminal TM2, the third transistor T3 may be turned on so that the voltage of the first power supply signal VGL may be provided to the second node N2.
The third capacitor C3 is coupled between the tenth transistor T10 and the fifth transistor T5. A first capacitor electrode of the third capacitor C3 is coupled to the second electrode of the fifth transistor T5 and the second electrode of the fourth transistor T4. A second capacitor electrode of the third capacitor C3 is coupled to the gate electrode of the fourth transistor T4 and the gate electrode of the tenth transistor T10.
In some embodiments, the first stabilizing subcircuit SSC1 is coupled between the second processing subcircuit PSC2 and the third processing subcircuit PSC3. Optionally, the first stabilizing subcircuit SSC1 is configured to limit a voltage drop width of the second node N2. Optionally, the first stabilizing subcircuit SSC1 includes an eleventh transistor T11.
The eleventh transistor T11 is coupled between the second node N2 and the fifth node N5. A gate electrode of the eleventh transistor T11 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate-on level voltage, the eleventh transistor T11 may always remain turned on. Therefore, the second node N2 and the fifth node N5 may be maintained at the same voltage, and operated as substantially the same node.
In some embodiments, the second stabilizing subcircuit SSC2 is coupled between the first node N1 and the output subcircuit OSC. Optionally, the second stabilizing subcircuit SSC2 is configured to limit a voltage drop width of the first node N1. Optionally, the second stabilizing subcircuit SSC2 includes a twelfth transistor T12.
The twelfth transistor T12 is coupled between the first node N1 and a gate electrode of the tenth transistor T10. A gate electrode of the twelfth transistor T12 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate-on level voltage, the twelfth transistor T12 may always remain turned on. Therefore, the first node N1 and the gate electrode of the tenth transistor T10 may be maintained at the same voltage.
In some embodiments, referring to FIG. 6, each of the first to twelfth transistors T1 to T12 may be formed of a p-type transistor. In some embodiments, the gate-on voltage of the first to twelfth transistors T1 to T12 may be set to a low level, and the gate-off voltage thereof may be set to a high level.
In alternative embodiments, each of the first to twelfth transistors T1 to T12 may be formed of an n-type transistor. In some embodiments, the gate-on voltage of the first to twelfth transistors T1 to T12 may be set to a high level, and the gate-off voltage thereof may be set to a low level.
Various alternative scan circuits may be used in the present disclosure. FIG. 7 is a circuit diagram of a respective scan unit of a scan circuit in some embodiments according to the present disclosure. FIG. 8 is a circuit diagram of a respective scan unit of a scan circuit in some embodiments according to the present disclosure. The respective scan unit depicted in FIG. 7 corresponds to the respective scan unit depicted in FIG. 1 and FIG. 2. The respective scan unit depicted in FIG. 8 corresponds to the respective scan unit depicted in FIG. 3 and FIG. 4. The gate driving signal output from the respective scan unit depicted in FIG. 8 is out of phase with respect to the gate driving signal output from the respective scan unit depicted in FIG. 7.
Referring to FIG. 7, the respective scan unit in some embodiments includes an input subcircuit ISC, an output subcircuit OSC, a first processing subcircuit PSC1, a second processing subcircuit PSC2, a third processing subcircuit PSC3, a first stabilizing subcircuit SSC1, and a second stabilizing subcircuit SSC2.
In some embodiments, the output subcircuit OSC is configured to supply the voltage of a second power supply signal VGH or a first power supply signal VGL to an output terminal TM4 in response to voltages of a fourth node N4. Optionally, the output subcircuit OSC includes a ninth transistor T9 and a tenth transistor T10.
The ninth transistor T9 is coupled between a second power supply signal VGH and the output terminal TM4. A gate electrode of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 may be turned on or off depending on the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the second power supply signal VGH is provided to the output terminal TM4, which (annotated as Outc in FIG. 7) may be transmitted to an n-th stage gate line and used as a gate driving signal having a gate-on level.
The tenth transistor T10 is coupled between the output terminal TM4 and a first power supply signal VGL. A gate electrode of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 may be turned on or off depending on the voltage of the first node N1. Optionally, when the tenth transistor T10 is turned on, the voltage of the first power supply signal VGL is provided to the output terminal TM4, which (annotated as Outc in FIG. 7) may be provided to an n-th stage gate line and used as a gate driving signal having a gate-off level. In one example, when the gate driving signal has a gate-off level, it may be understood that the gate driving signal is not provided.
In some embodiments, the input subcircuit ISC is configured to control the voltages of the first node N1 in response to signals provided to the first input terminal TM1 and the second input terminal TM2, respectively. Optionally, the input subcircuit ISC includes a first transistor T1.
The first transistor T1 is coupled between the first input terminal TM1 and the first node N1. A gate electrode of the first transistor T1 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the first transistor T1 is turned on to electrically couple the first input terminal TM1 with the first node N1.
In some embodiments, the first processing subcircuit PSC1 includes an eighth transistor T8, a thirteenth transistor T13, and a second capacitor C2.
The eighth transistor T8 is coupled between the second power supply signal VGH and the fourth node N4. A gate electrode of the eighth transistor T8 is coupled to the second electrode of the thirteenth transistor T13. The eighth transistor T8 may be turned on or off depending on the voltage of the second electrode of the thirteenth transistor T13. Optionally, when the eighth transistor T8 is turned on, the voltage of the second power supply signal VGH may be provided to the fourth node N4.
The thirteenth transistor T13 is coupled between the second power supply signal VGH and the eighth transistor T8. A gate electrode of the thirteenth transistor T13 is coupled to a signal terminal ECX. A first electrode of the thirteenth transistor T13 is coupled to the second power supply signal VGH. A second electrode of the thirteenth transistor T13 is coupled to the gate electrode of the eighth transistor T8. The thirteenth transistor T13 may be turned on or off depending on the voltage of the signal terminal ECX. Optionally, when the thirteenth transistor T13 is turned on, the voltage of the first power supply VGH may be provided to the gate electrode of the eighth transistor T8.
The second capacitor C2 is coupled between the second power supply signal VGH and the fourth node N4. Optionally, the second capacitor C2 is configured to charge a voltage to be applied to the fourth node N4. Optionally, the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.
In some embodiments, the second processing subcircuit PSC2 is coupled to a fifth node N5, and is configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing subcircuit PSC2 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.
A first terminal of the first capacitor C1 is coupled to the fifth node N5, and a second terminal of the first capacitor C1 is coupled to a third node N3 that is a common node between the sixth transistor T6 and the seventh transistor T7.
The sixth transistor T6 is coupled between the third node N3 and the fifth node N5. A gate electrode of the sixth transistor T6 is coupled to the fifth node N5. The sixth transistor T6 may be turned on depending on the voltage of the fifth node N5 so that a voltage corresponding to the second clock signal CB provided to the third input terminal TM3 may be applied to the third node N3.
The seventh transistor T7 is coupled between the fourth node N4 and the third node N3. A gate electrode of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 may be turned on in response to the second clock signal CB provided to the third input terminal TM3, and thus, applies the voltage of the second power supply signal VGH to the third node N3.
In some embodiments, the third processing subcircuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing subcircuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a third capacitor C3.
The fifth transistor T5 is coupled between the second power supply signal VGH and the fourth transistor T4. A gate electrode of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 may be turned on or off depending on the voltage of the second node N2.
The fourth transistor T4 is coupled between the fifth transistor T5 and the third input terminal TM3. A first electrode of the fourth transistor T4 is configured to be provided with the second clock signal CB provided to the third input terminal TM3. A gate electrode of the fourth transistor T4 is coupled to the gate electrode of the tenth transistor T10. A second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5.
The second transistor T2 is coupled between the second node N2 and the second input terminal TM2. A gate electrode of the second transistor T2 is coupled to the first node N1.
The third transistor T3 is coupled between the second node N2 and the first power supply signal VGL. A gate electrode of the third transistor T3 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the third transistor T3 may be turned on so that the voltage of the first power supply signal VGL may be provided to the second node N2.
The third capacitor C3 is coupled between the tenth transistor T10 and the fifth transistor T5. A first capacitor electrode of the third capacitor C3 is coupled to the second electrode of the fifth transistor T5 and the first electrode of the fourth transistor T4. A second capacitor electrode of the third capacitor C3 is coupled to the gate electrode of the fourth transistor T4 and the gate electrode of the tenth transistor T10.
In some embodiments, the first stabilizing subcircuit SSC1 is coupled between the second processing subcircuit PSC2 and the third processing subcircuit PSC3. Optionally, the first stabilizing subcircuit SSC1 is configured to limit a voltage drop width of the second node N2. Optionally, the first stabilizing subcircuit SSC1 includes an eleventh transistor T11.
The eleventh transistor T11 is coupled between the second node N2 and the fifth node N5. A gate electrode of the eleventh transistor T11 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate-on level voltage, the eleventh transistor T11 may always remain turned on. Therefore, the second node N2 and the fifth node N5 may be maintained at the same voltage, and operated as substantially the same node. As used herein, the term “substantially the same” refers to a difference between two values not exceeding 10%of a base value (e.g., one of the two values) , e.g., not exceeding 8%, not exceeding 6%, not exceeding 4%, not exceeding 2%, not exceeding 1%, not exceeding 0.5%, not exceeding 0.1%, not exceeding 0.05%, and not exceeding 0.01%, of the base value.
In some embodiments, the second stabilizing subcircuit SSC2 is coupled between the first node N1 and the output subcircuit OSC. Optionally, the second stabilizing subcircuit SSC2 is configured to limit a voltage drop width of the first node N1. Optionally, the second stabilizing subcircuit SSC2 includes a twelfth transistor T12.
The twelfth transistor T12 is coupled between the first node N1 and a gate electrode of the tenth transistor T10. A gate electrode of the twelfth transistor T12 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate-on level voltage, the twelfth transistor T12 may always remain turned on. Therefore, the first node N1 and the gate electrode of the tenth transistor T10 may be maintained at the same voltage.
In some embodiments, referring to FIG. 7, each of the first to twelfth transistors T1 to T12 may be formed of a p-type transistor. In some embodiments, the gate-on voltage of the first to twelfth transistors T1 to T12 may be set to a low level, and the gate-off voltage thereof may be set to a high level.
In alternative embodiments, each of the first to twelfth transistors T1 to T12 may be formed of an n-type transistor. In some embodiments, the gate-on voltage of the first to twelfth transistors T1 to T12 may be set to a high level, and the gate-off voltage thereof may be set to a low level.
Referring to FIG. 8, the respective scan unit in some embodiments includes an input subcircuit ISC, an output subcircuit OSC, a first processing subcircuit PSC1, a second processing subcircuit PSC2, a third processing subcircuit PSC3, a first stabilizing subcircuit SSC1, and a second stabilizing subcircuit SSC2.
In some embodiments, the output subcircuit OSC is configured to supply the voltage of a second power supply signal VGH or a first power supply signal VGL to an output terminal TM4 in response to voltages of a fourth node N4. Optionally, the output subcircuit OSC includes a ninth transistor T9 and a tenth transistor T10.
The ninth transistor T9 is coupled between a second power supply signal VGH and the output terminal TM4. A gate electrode of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 may be turned on or off depending on the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the second power supply signal VGH is provided to the output terminal TM4, which (annotated as Outc in FIG. 8) may be transmitted to an n-th stage gate line and used as a gate driving signal having a gate-on level.
The tenth transistor T10 is coupled between the output terminal TM4 and a first power supply signal VGL. A gate electrode of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 may be turned on or off depending on the voltage of the first node N1. Optionally, when the tenth transistor T10 is turned on, the voltage of the first power supply signal VGL is provided to the output terminal TM4, which (annotated as Outc in FIG. 8) may be provided to an n-th stage gate line and used as a gate driving signal having a gate-off level. In one example, when the gate driving signal has a gate-off level, it may be understood that the gate driving signal is not provided.
In some embodiments, the input subcircuit ISC is configured to control the voltages of the first node N1 in response to signals provided to the first input terminal TM1 and the second input terminal TM2, respectively. Optionally, the input subcircuit ISC includes a first transistor T1.
The first transistor T1 is coupled between the first input terminal TM1 and the first node N1. A gate electrode of the first transistor T1 is coupled to the second input terminal TM2. When the second clock signal CB is provided to the second input terminal TM2, the first transistor T1 is turned on to electrically couple the first input terminal TM1 with the first node N1.
In some embodiments, the first processing subcircuit PSC1 includes an eighth transistor T8, a thirteenth transistor T13, and a second capacitor C2.
The eighth transistor T8 is coupled between the second power supply signal VGH and the fourth node N4. A gate electrode of the eighth transistor T8 is coupled to the second electrode of the thirteenth transistor T13. The eighth transistor T8 may be turned on or off depending on the voltage of the second electrode of the thirteenth transistor T13. Optionally, when the eighth transistor T8 is turned on, the voltage of the second power supply signal VGH may be provided to the fourth node N4.
The thirteenth transistor T13 is coupled between the second power supply signal VGH and the eighth transistor T8. A gate electrode of the thirteenth transistor T13 is coupled to a signal terminal ECX. A first electrode of the thirteenth transistor T13 is coupled to the second power supply signal VGH. A second electrode of the thirteenth transistor T13 is coupled to the gate electrode of the eighth transistor T8. The thirteenth transistor T13 may be turned on or off depending on the voltage of the signal terminal ECX. Optionally, when the thirteenth transistor T13 is turned on, the voltage of the first power supply VGH may be provided to the gate electrode of the eighth transistor T8.
The second capacitor C2 is coupled between the second power supply signal VGH and the fourth node N4. Optionally, the second capacitor C2 is configured to charge a voltage to be applied to the fourth node N4. Optionally, the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.
In some embodiments, the second processing subcircuit PSC2 is coupled to a fifth node N5, and is configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing subcircuit PSC2 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.
A first terminal of the first capacitor C1 is coupled to the fifth node N5, and a second terminal of the first capacitor C1 is coupled to a third node N3 that is a common node between the sixth transistor T6 and the seventh transistor T7.
The sixth transistor T6 is coupled between the third node N3 and the fifth node N5. A gate electrode of the sixth transistor T6 is coupled to the fifth node N5. The sixth transistor T6 may be turned on depending on the voltage of the fifth node N5 so that a voltage corresponding to the first clock signal CK provided to the third input terminal TM3 may be applied to the third node N3.
The seventh transistor T7 is coupled between the fourth node N4 and the third node N3. A gate electrode of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 may be turned on in response to the first clock signal CK provided to the third input terminal TM3, and thus, applies the voltage of the second power supply signal VGH to the third node N3.
In some embodiments, the third processing subcircuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing subcircuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a third capacitor C3.
The fifth transistor T5 is coupled between the second power supply signal VGH and the fourth transistor T4. A gate electrode of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 may be turned on or off depending on the voltage of the second node N2.
The fourth transistor T4 is coupled between the fifth transistor T5 and the third input terminal TM3. A first electrode of the fourth transistor T4 is configured to be provided with the first clock signal CK provided to the third input terminal TM3. A gate electrode of the fourth transistor T4 is coupled to the gate electrode of the tenth transistor T10. A second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5.
The second transistor T2 is coupled between the second node N2 and the second input terminal TM2. A gate electrode of the second transistor T2 is coupled to the first node N1.
The third transistor T3 is coupled between the second node N2 and the first power supply signal VGL. A gate electrode of the third transistor T3 is coupled to the second input terminal TM2. When the second clock signal CB is provided to the second input terminal TM2, the third transistor T3 may be turned on so that the voltage of the first power supply signal VGL may be provided to the second node N2.
The third capacitor C3 is coupled between the tenth transistor T10 and the fifth transistor T5. A first capacitor electrode of the third capacitor C3 is coupled to the second electrode of the fifth transistor T5 and the second electrode of the fourth transistor T4. A second capacitor electrode of the third capacitor C3 is coupled to the gate electrode of the fourth transistor T4 and the gate electrode of the tenth transistor T10.
In some embodiments, the first stabilizing subcircuit SSC1 is coupled between the second processing subcircuit PSC2 and the third processing subcircuit PSC3. Optionally, the first stabilizing subcircuit SSC1 is configured to limit a voltage drop width of the second node N2. Optionally, the first stabilizing subcircuit SSC1 includes an eleventh transistor T11.
The eleventh transistor T11 is coupled between the second node N2 and the fifth node N5. A gate electrode of the eleventh transistor T11 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate-on level voltage, the eleventh transistor T11 may always remain turned on. Therefore, the second node N2 and the fifth node N5 may be maintained at the same voltage, and operated as substantially the same node.
In some embodiments, the second stabilizing subcircuit SSC2 is coupled between the first node N1 and the output subcircuit OSC. Optionally, the second stabilizing subcircuit SSC2 is configured to limit a voltage drop width of the first node N1. Optionally, the second stabilizing subcircuit SSC2 includes a twelfth transistor T12.
The twelfth transistor T12 is coupled between the first node N1 and a gate electrode of the tenth transistor T10. A gate electrode of the twelfth transistor T12 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate-on level voltage, the twelfth transistor T12 may always remain turned on. Therefore, the first node N1 and the gate electrode of the tenth transistor T10 may be maintained at the same voltage.
In some embodiments, referring to FIG. 8, each of the first to twelfth transistors T1 to T12 may be formed of a p-type transistor. In some embodiments, the gate-on voltage of the first to twelfth transistors T1 to T12 may be set to a low level, and the gate-off voltage thereof may be set to a high level.
In alternative embodiments, each of the first to twelfth transistors T1 to T12 may be formed of an n-type transistor. In some embodiments, the gate-on voltage of the first to twelfth transistors T1 to T12 may be set to a high level, and the gate-off voltage thereof may be set to a low level.
In some embodiments, the present disclosure provides an array substrate having a plurality of pixel driving circuits and a plurality of light emitting elements. A respective scan circuit of the one or more scan circuits are configured to provide a plurality of control signals (e.g., gate scanning signals, reset control signals, or light emission control signals) to a plurality of rows of pixel driving circuits. Various appropriate pixel driving circuits may be used in the present array substrate. Examples of appropriate driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, the respective one of the plurality of pixel driving circuits is an 8T1C driving circuit. Various appropriate light emitting elements may be used in the present array substrate. Examples of appropriate light emitting elements include organic light emitting diodes, quantum dots light emitting diodes, and micro light emitting diodes. Optionally, the light emitting element is micro light emitting diode. Optionally, the light emitting element is an organic light emitting diode including an organic light emitting layer.
FIG. 9 is a plan view of an array substrate in some embodiments according to the present disclosure. Referring to FIG. 9, the array substrate includes an array of subpixels Sp. Each subpixel includes an electronic component, e.g., a light emitting element. In one example, the light emitting element is driven by a respective pixel driving circuit PDC. The array substrate includes a plurality of first gate lines (e.g., a respective first gate line GL1) , a plurality of second gate lines (e.g., a respective second gate line GL2) , a plurality of data lines (e.g., a respective data line DL) , a plurality of high voltage supply lines (e.g., a respective high voltage supply line Vdd) , and a plurality of low voltage supply lines (e.g., a respective low voltage supply line) . Light emission in a respective subpixel Sp is driven by a respective pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input, through the respective high voltage supply line Vdd of the plurality of high voltage supply line, to the respective pixel driving circuit PDC connected to an anode of the light emitting element; a low voltage signal (e.g., a VSS signal) is input, through a low voltage supply line, to a cathode of the light emitting element. A voltage difference between the high voltage signal (e.g., the VDD signal) and the low voltage signal (e.g., the VSS signal) is a driving voltage ΔV that drives light emission in the light emitting element.
FIG. 10A is a circuit diagram illustrating the structure of a pixel driving circuit in some embodiments according to the present disclosure. Referring to FIG. 10A, in some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate electrode connected to a respective second reset control signal line rst2 of a plurality of second reset control signal lines, a first electrode connected to a respective second reset signal line Vint2 of a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate electrode connected to a respective first gate line GL1 of a plurality of first gate lines, a first electrode connected to a respective data line DL of a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate electrode connected to a respective first reset control signal line rst1 of a plurality of first reset control signal lines, a first electrode connected to a respective third reset signal line Vint3 of a plurality of third reset signal lines, and a second electrode connected to the first electrode of the driving transistor Td; a second transistor T2 having a gate electrode connected to a respective second gate line GL2 of a plurality of second gate lines, a first electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate electrode of the driving transistor Td, and a second electrode connected to the second electrode of the driving transistor Td; a third transistor T3 having a gate electrode connected to a respective light emitting control signal line em of a plurality of light emitting control signal lines, a first electrode connected to a respective voltage supply line Vdd of a plurality of voltage supply lines, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1; a fourth transistor T4 having a gate electrode connected to the respective light emitting control signal line em of the plurality of light emitting control signal lines, a first electrode connected to second electrodes of the driving transistor Td and the second transistor T2, and a second electrode connected to an anode of a light emitting element LE; and a first reset transistor Tr1 having a gate electrode connected to the respective first reset control signal line rst1 of a plurality of first reset control signal lines, a first electrode connected to a respective first reset signal line Vint1 of a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to the respective voltage supply line and the first electrode of the third transistor T3.
In some embodiments, the pixel driving circuit includes a driving transistor Td, a data write transistor (e.g., the first transistor T1) , a compensating transistor (e.g., the second transistor T2) , two light emitting control transistors (e.g., the third transistor T3 and the fourth transistor T4) , and three reset transistors (e.g., the first reset transistor Tr1, the second reset transistor Tr2, and the third reset transistor Tr3) .
As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, the first terminal and the second terminal being connected to an active layer of the transistor. A direction of a current flowing through the transistor may be configured to be from a first electrode to a second electrode, or from a second electrode to a first electrode. Accordingly, depending on the direction of the current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.
The pixel driving circuit further include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate electrode of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light emitting element LE.
The array substrate in some embodiments includes a plurality of subpixels. In some embodiments, the plurality of subpixels includes a respective first subpixel, a respective second subpixel, and a respective third subpixel. Optionally, a respective pixel of the array substrate includes the respective first subpixel, the respective second subpixel, and the respective third subpixel. The plurality of subpixels in the array substrate are arranged in an array. In one example, the array of the plurality of subpixels includes a S1-S2-S3 format repeating array, in which S1 stands for the respective first subpixel, S2 stands for the respective second subpixel, and S3 stands for the respective third subpixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, in which C1 stands for the respective first subpixel of a first color, C2 stands for the respective second subpixel of a second color, and C3 stands for the respective third subpixel of a third color. In another example, the C1-C2-C3 format is an R-G-B format, in which the respective first subpixel is a red subpixel, the respective second subpixel is a green subpixel, and the respective third subpixel is a blue subpixel.
In another example, the array of the plurality of subpixels includes a S1-S2-S3-S4 format repeating array, in which S1 stands for the respective first subpixel, S2 stands for the respective second subpixel, S3 stands for the respective third subpixel, and S4 stands for the respective fourth subpixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, in which C1 stands for the respective first subpixel of a first color, C2 stands for the respective second subpixel of a second color, C3 stands for the respective third subpixel of a third color, and C4 stands for the respective fourth subpixel of a fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2’ format, in which C1 stands for the respective first subpixel of a first color, C2 stands for the respective second subpixel of a second color, C3 stands for the respective third subpixel of a third color, and C2’ stands for the respective fourth subpixel of the second color. In another example, the C1-C2-C3-C2’ format is a R-G-B-G format, in which the respective first subpixel is a red subpixel, the respective second subpixel is a green subpixel, the respective third subpixel is a blue subpixel, and the respective fourth subpixel is a green subpixel.
In some embodiments, a minimum repeating unit of the plurality of subpixels of the array substrate includes the respective first subpixel, the respective second subpixel, and the respective third subpixel. Optionally, each of the respective first subpixel, the respective second subpixel, and the respective third subpixel, includes the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, the driving transistor Td, and the storage capacitor Cst.
In alternative embodiments, a minimum repeating unit of the plurality of subpixels of the array substrate includes a respective first subpixel, a respective second subpixel, a respective third subpixel, and a respective fourth subpixel. Optionally, each of the respective first subpixel, the respective second subpixel, the respective third subpixel, and the respective fourth subpixel, includes the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, the driving transistor Td, and the storage capacitor Cst.
The present disclosure may be implemented in pixel driving circuit having transistors of various types, including a pixel driving circuit having p-type transistors, a pixel driving circuit having n-type transistors, and a pixel driving circuit having one or more p-type transistors and one or more n-type transistors. Referring to FIG. 10A, the second transistor T2 is an n-type transistor such as a metal oxide transistor, and other transistors are p-type transistors such as polysilicon transistors. For a p-type transistor, an effective control signal (e.g., a turn-on control signal) is a low voltage signal, and an ineffective control signal (e.g., a turn-off control signal) is a high voltage signal. For an n-type transistor, an effective control signal (e.g., a turn-on control signal) is a high voltage signal, and an ineffective control signal (e.g., a turn-off control signal) is a low voltage signal.
FIG. 10B is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure. Referring to FIG. 10A and FIG. 10B, during one frame of image, the operation of the pixel driving circuit includes a reset sub-phase t1, a data write sub-phase t2, and a light emitting sub-phase t3. In the initial sub-phase t0, a turning-off reset control signal is provided through the respective second reset control signal line rst2 to the gate electrode of the second reset transistor Tr2 to turn off the second reset transistor Tr2. A turning-off reset control signal is provided through the respective first reset control signal line rst1 to the gate electrode of the first reset transistor Tr1 and the gate electrode of the third reset transistor Tr3 to turn off the first reset transistor Tr1 and the third reset transistor Tr3. In the initial sub-phase t0, the respective first gate line GL1 is provided with a turning-off signal, thus the first transistor T1 is turned off.
In the reset sub-phase t1, a turning-on reset control signal is provided through the respective first reset control signal line rst1 to the gate electrode of the first reset transistor Tr1 to turn on the first reset transistor Tr1; allowing an initialization voltage signal from the respective first reset signal line Vint1 to pass from a first electrode of the first reset transistor Tr1 to a second electrode of the first reset transistor Tr1; and in turn to the node N4. The anode of the light emitting element LE is initialized. A turning-on reset control signal is provided through the respective first reset control signal line rst1 to the gate electrode of the third reset transistor Tr3 to turn on the third reset transistor Tr3; allowing an initialization voltage signal from the respective third reset signal line Vint3 to pass from a first electrode of the third reset transistor Tr3 to a second electrode of the third reset transistor Tr3; and in turn to the node N2. The node N2 is initialized. In the reset sub-phase t1, the respective first gate line GL1 is provided with a turning-off signal, thus the first transistor T1 is turned off. The respective light emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.
In the data write sub-phase t2, a turning-on reset control signal is provided through the second reset control signal line rst2 to the gate electrode of the second reset transistor Tr2 to turn on the second reset transistor Tr2; allowing an initialization voltage signal from the respective second reset signal line Vint2 to pass from a first electrode of the second reset transistor Tr2 to a second electrode of the second reset transistor Tr2, and in turn to the first capacitor electrode Ce1 and the gate electrode of the driving transistor Td. The gate electrode of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the respective voltage supply line Vdd. The first capacitor electrode Ce1 is charged in the data write sub-phase t2 due to an increasing voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2.
In the data write sub-phase t2, the turning-off reset control signal is again provided through the respective first reset control signal line rst1 to the gate electrode of the first reset transistor Tr1 and the gate electrode of the third reset transistor Tr3 to turn off the first reset transistor Tr1 and the third reset transistor Tr3. The respective first gate line GL1 and the respective second gate line GL2 are provided with a turning-on signal, thus the first transistor T1 and the second transistor T2 are turned on. A second electrode of the driving transistor Td is connected with the second electrode of the second transistor T2. A gate electrode of the driving transistor Td is electrically connected with the first electrode of the second transistor T2. Because the second transistor T2 is turned on in the data write sub-phase t2, the gate electrode and the second electrode of the driving transistor Td are connected and short circuited, and only the PN junction between the gate electrode and a first electrode of the driving transistor Td is effective, thus rendering the driving transistor Td in a diode connecting mode. The first transistor T1 is turned on in the data write sub-phase t2. The data voltage signal transmitted through the respective data line DL is received by a first electrode of the first transistor T1, and in turn transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. A node N2 connecting to the first electrode of the driving transistor Td has a voltage level of the data voltage signal. Because only the PN junction between the gate electrode and a first electrode of the driving transistor Td is effective, the voltage level at the node N1 in the data write sub-phase t2 increase gradually to (Vdata + Vth) , wherein the Vdata is the voltage level of the data voltage signal, and the Vth is the voltage level of the threshold voltage Th of the PN junction. The storage capacitor Cst is discharged because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 is reduced to a relatively small value. The respective light emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.
In the light emitting sub-phase t3, a turning-off reset control signal is provided through the respective second reset control signal line rst2 to the gate electrode of the second reset transistor Tr2 to turn off the second reset transistor Tr2. A turning-off reset control signal is provided through the respective first reset control signal line rst1 to the gate electrode of the first reset transistor Tr1 and the gate electrode of the third reset transistor Tr3 to turn off the first reset transistor Tr1 and the third reset transistor Tr3. The respective first gate line GL1 and the respective second gate line GL2 are provided with a turning-off signal, the first transistor T1 and the second transistor T2 are turned off. The respective light emitting control signal line em is provided with a low voltage signal to turn on the third transistor T3 and the fourth transistor T4. The voltage level at the node N1 in the light emitting sub-phase t3 is maintained at (Vdata + Vth) , the driving transistor Td is turned on by the voltage level, and working in the saturation area. A path is formed through the third transistor T3, the driving transistor Td, the fourth transistor T4, to the light emitting element LE. The driving transistor Td generates a driving current for driving the light emitting element LE to emit light. A voltage level at a node N3 connected to the second electrode of the driving transistor Td equals to a light emitting voltage of the light emitting element LE.
FIG. 11 is a diagram illustrating one or more scan circuits in a display apparatus in some embodiments according to the present disclosure. Referring to FIG. 11, the display apparatus in some embodiments includes a plurality of rows of subpixels and one or more scan circuits configured to provide control signals to the plurality of rows of subpixels. As shown in FIG. 11, the display apparatus in some embodiments includes a first scan circuit SC1 and a second scan circuit SC2.
In some embodiments, the first scan circuit SC1 includes a plurality of stages of cascaded scan units. Optionally, the plurality of stages of cascaded scan units of the first scan circuit SC1 are configured to provide a plurality of control signals (e.g., gate scanning signals, reset control signals, or light emission control signals) to a plurality of rows of subpixels. Optionally, as shown in FIG. 11, a respective stage of cascaded scan unit of the plurality of stages of cascaded scan units of the first scan circuit SC1 is configured to provide control signals to a single row of subpixels. In some embodiments, the first scan circuit SC1 is a first gate scanning signal generating circuit configured to generate gate scanning signals for subpixels in the array substrate. In one example, the first scan circuit SC1 is a first gate scanning signal generating circuit configured to generate gate scanning signals for the plurality of first gate lines (a respective first gate line GL1 is denoted in FIG. 10A) . The plurality of first gate lines are configured to provide gate scanning signals to the first transistor T1 (e.g., a p-type transistor) in the respective pixel driving circuit.
In some embodiments, the first scan circuits SC1 includes scan units on both sides of the display panel. A respective stage of the first scan circuit SC1 includes scan units on both sides of the display panel, and the scan units of a same stage on both sides of the display panel are configured to provide control signals to a same row of subpixels.
In some embodiments, the second scan circuit SC2 includes a plurality of stages of cascaded scan units. Optionally, the plurality of stages of cascaded scan units of the second scan circuit SC2 are configured to provide a plurality of control signals (e.g., gate scanning signals, reset control signals, or light emission control signals) to a plurality of rows of subpixels. Optionally, as shown in FIG. 11, a respective stage of cascaded scan unit of the plurality of stages of cascaded scan units of the second scan circuit SC2 is configured to provide control signals to multiple rows (e.g., two rows) of subpixels. In some embodiments, the second scan circuit SC2 is a second gate scanning signal generating circuit configured to generate gate scanning signals for subpixels in the array substrate. In one example, the second scan circuit SC2 is a second gate scanning signal generating circuit configured to generate gate scanning signals for the plurality of second gate lines (a respective second gate line GL2 is denoted in FIG. 10A) . The plurality of second gate lines are configured to provide gate scanning signals to the second transistor T2 (e.g., an n-type transistor) in the respective pixel driving circuit.
In some embodiments, the display apparatus further includes a third scan circuit SC3, a fourth scan circuit SC4, and a fifth scan circuit SC5. In some embodiments, the third scan circuit SC3 includes a plurality of stages of cascaded scan units. Optionally, the plurality of stages of cascaded scan units of the third scan circuit SC3 are configured to provide a plurality of control signals (e.g., gate scanning signals, reset control signals, or light emission control signals) to a plurality of rows of subpixels. Optionally, as shown in FIG. 11, a respective stage of cascaded scan unit of the plurality of stages of cascaded scan units of the third scan circuit SC3 is configured to provide control signals to multiple rows (e.g., two rows) of subpixels. In some embodiments, the third scan circuit SC3 is a second reset control signal generating circuit configured to generate reset control signals for subpixels in the array substrate. In one example, the third scan circuit SC3 is a second reset control signal generating circuit configured to generate second reset control signals for the plurality of second reset control signal lines (a respective second reset control signal line rst2 is denoted in FIG. 10A) . The plurality of second reset control signal lines are configured to provide second reset control signals to the second reset transistor Tr2 (e.g., a p-type transistor) in the respective pixel driving circuit.
In some embodiments, the fourth scan circuit SC4 includes a plurality of stages of cascaded scan units. Optionally, the plurality of stages of cascaded scan units of the fourth scan circuit SC4 are configured to provide a plurality of control signals (e.g., gate scanning signals, reset control signals, or light emission control signals) to a plurality of rows of subpixels. Optionally, as shown in FIG. 11, a respective stage of cascaded scan unit of the plurality of stages of cascaded scan units of the fourth scan circuit SC4 is configured to provide control signals to multiple rows (e.g., two rows) of subpixels. In some embodiments, the fourth scan circuit SC4 is a first reset control signal generating circuit configured to generate reset control signals for subpixels in the array substrate. In one example, the fourth scan circuit SC4 is a first reset control signal generating circuit configured to generate first reset control signals for the plurality of first reset control signal lines (a respective first reset control signal line rst1 is denoted in FIG. 10A) . The plurality of first reset control signal lines are configured to provide first reset control signals to the first reset transistor Tr1 and the third reset transistor Tr3 (e.g., p-type transistors) in the respective pixel driving circuit.
In some embodiments, the fifth scan circuit SC5 includes a plurality of stages of cascaded scan units. Optionally, the plurality of stages of cascaded scan units of the fifth scan circuit SC5 are configured to provide a plurality of control signals (e.g., gate scanning signals, reset control signals, or light emission control signals) to a plurality of rows of subpixels. Optionally, as shown in FIG. 11, a respective stage of cascaded scan unit of the plurality of stages of cascaded scan units of the fifth scan circuit SC5 is configured to provide control signals to multiple rows (e.g., two rows) of subpixels. In some embodiments, the fifth scan circuit SC5 is a light emitting control signal generating circuit configured to generate light emitting control signals for subpixels in the array substrate. In one example, the fifth scan circuit SC5 is a light emitting control signal generating circuit configured to generate light emitting control signals for the plurality of light emitting control signal lines (a respective light emitting control signal line em is denoted in FIG. 10A) . The plurality of light emitting control signal lines are configured to provide light emitting control signals to the third transistor T3 and the fourth transistor T4 (e.g., p-type transistors) in the respective pixel driving circuit.
FIG. 12 is a diagram illustrating a first scan circuit in a display apparatus in some embodiments according to the present disclosure. Referring to FIG. 12, the first scan circuit in some embodiments includes a plurality of first scan units and a plurality of second scan units. Optionally, the plurality of first scan units and the plurality of second scan units are alternately arranged. Optionally, a respective first scan unit RSU1 and a respective second scan unit RSU2 are configured to provide control signals to two adjacent rows of subpixels, respectively. In one example, the respective first scan unit RSU1 and the respective second scan unit RSU2 are configured to provide first gate scanning signals to data write transistors in pixel driving circuits in the two adjacent rows of subpixels, respectively.
In some embodiments, control signals output from the respective first scan unit RSU1 and provided to a first adjacent row of subpixels are out of phase with respect to control signals output from the respective second scan unit RSU2 and provided to a second adjacent row of subpixels. In one example, first gate scanning signals output from the respective first scan unit RSU1 and provided to the first adjacent row of subpixels are out of phase with respect to first gate scanning signals output from the respective second scan unit RSU2 and provided to the second adjacent row of subpixels.
FIG. 13 is a diagram illustrating a second scan circuit in a display apparatus in some embodiments according to the present disclosure. Referring to FIG. 13, the second scan circuit SC2 in some embodiments includes a plurality of third scan units. Optionally, a respective third scan unit RSU3 of the plurality of third scan units is configured to provide control signals to two adjacent rows of subpixels. In one example, the respective third scan unit RSU3 of the plurality of third scan units is configured to provide second gate scanning signals to compensating transistors in pixel driving circuits in the two adjacent rows of subpixels.
In some embodiments, control signals output from the respective third scan unit RSU3 and provided to a first adjacent row of subpixels are in-phase with respect to control signals output from the respective third scan unit RSU3 and provided to a second adjacent row of subpixels. In one example, second gate scanning signals output from the respective third scan unit RSU3 and provided to the first adjacent row of subpixels are in-phase with respect to second gate scanning signals output from the respective third scan unit RSU3 and provided to the second adjacent row of subpixels.
In some embodiments, the display apparatus includes K number of rows of subpixels, K being an integer greater than 1. The K number of rows of subpixels includes a (2k-1) -th row of subpixels and a (2k) -th row of subpixels, 1 ≤ k ≤ (K/2) , k being an integer. Referring to FIG. 12 and FIG. 13, the first scan circuit in some embodiments includes a plurality of first scan units and a plurality of second scan units. Optionally, the plurality of first scan units and the plurality of second scan units are alternately arranged. Optionally, a respective first scan unit RSU1 is configured to provide control signals to a (2k-1) -th row of subpixels, and a respective second scan unit RSU2 is configured to provide control signals to a (2k) -th row of subpixels. In one example, the respective first scan unit RSU1 is configured to provide first gate scanning signals to data write transistors in pixel driving circuits in the (2k-1) -th row of subpixels, and the respective second scan unit RSU2 is configured to provide first gate scanning signals to data write transistors in pixel driving circuits in the (2k) -th row of subpixels.
In some embodiments, control signals output from the respective first scan unit RSU1 and provided to the (2k-1) -th row of subpixels are out of phase with respect to control signals output from the respective second scan unit RSU2 and provided to the (2k) -th row of subpixels. In one example, first gate scanning signals output from the respective first scan unit RSU1 and provided to the (2k-1) -th row of subpixels are out of phase with respect to first gate scanning signals output from the respective second scan unit RSU2 and provided to the (2k) -th row of subpixels.
In some embodiments, the second scan circuit SC2 includes a plurality of third scan units. Optionally, a respective third scan unit RSU3 of the plurality of third scan units is configured to provide control signals to the (2k-1) -th row of subpixels and the (2k) -th row of subpixels. In one example, the respective third scan unit RSU3 of the plurality of third scan units is configured to provide second gate scanning signals to compensating transistors in pixel driving circuits in the (2k-1) -th row of subpixels and the (2k) -th row of subpixels.
In some embodiments, control signals output from the respective third scan unit RSU3 and provided to the (2k-1) -th row of subpixels are in-phase with respect to control signals output from the respective third scan unit RSU3 and provided to the (2k) -th row of subpixels. In one example, second gate scanning signals output from the respective third scan unit RSU3 and provided to the (2k-1) -th row of subpixels are in-phase with respect to second gate scanning signals output from the respective third scan unit RSU3 and provided to the (2k) -th row of subpixels.
As used herein, the term “ (2k-1) -th row” and the term “ (2k) -th row” are used in the context of the K rows. The array substrate may or may not include additional row (s) before the first row of the K rows and/or additional rows after the last row of the K number of rows. In the context of the array substrate, the term “ (2k-1) -th row” does not necessarily denote an odd-numbered row, and the term “ (2k) -th row does not necessarily denote an even-numbered row. In one example, the (2k-1) -th row is an odd-numbered row in the context of the K number of rows, but may be an even-numbered row in the context of the array substrate. In another example, the (2k-1) -th row is an odd-numbered row in the context of the K number of rows, and also an odd-numbered row in the context of the array substrate. In one example, the (2k) -th row is an even-numbered row in the context of the K rows, but may be an odd-numbered row in the context of the array substrate. In another example, the (2k) -th row is an even-numbered row in the context of the K rows, and also an even-numbered row in the context of the array substrate.
FIG. 14A is a diagram illustrating the structure of multiple scan units in multiple rows of a scan circuit in some embodiments according to the present disclosure. FIG. 14B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 14A. FIG. 14C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 14A. FIG. 14D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 14A. FIG. 14E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 14A. FIG. 14F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 14A. FIG. 14A is annotated with labels indicating transistors (T1, T2, T3, T4, T5, T6, T7, and T8) and capacitors (C1 and C2) , and signal lines (CBL, CKL, VGLL, VGHL, STVL, Vint1, Vint2, and Vint3) in the respective scan unit.
Referring to FIG. 14A and FIG. 14B, in some embodiments, the semiconductor material layer includes active layers of transistors in the respective scan unit. FIG. 14B is annotated with labels indicating the active layers of the transistors in the respective scan unit, for example, an active layer ACT1 of the first transistor T1, an active layer ACT2 of the second transistor T2, an active layer ACT3 of the third transistor T3, an active layer ACT4 of the fourth transistor T4, an active layer ACT5 of the fifth transistor T5, an active layer ACT6 of the sixth transistor T6, an active layer ACT7 of the seventh transistor T7, and an active layer ACT8 of the eighth transistor T8. FIG. 14B is further annotated with labels indicating first electrodes and second electrodes of certain transistors in the respective scan unit. For example, the first transistor T1 includes a first electrode S1 and a second electrode D1, the second transistor T2 includes a first electrode S2 and a second electrode D2, the third transistor T3 includes a first electrode S3 and a second electrode D3, the sixth transistor T6 includes a first electrode S6 and a second electrode D6, the seventh transistor T7 includes a first electrode S7 and a second electrode D7, and the eighth transistor T8 includes a first electrode S8 and a second electrode D8. Various appropriate semiconductor materials may be used for making the semiconductor material layer. Examples of the semiconductor materials for making the semiconductor material layer include metal oxide-based semiconductor material such as indium gallium zinc oxide and metal oxynitride-based semiconductor materials such as zinc oxynitride.
Referring to FIG. 14A and FIG. 14C, in some embodiments, the first conductive layer includes a first capacitor electrode Ce1 of the first capacitor C1, a third capacitor electrode Ce3 of the second capacitor C2, a gate electrode G1 of the first transistor T1, a gate electrode G2 of the second transistor T2, a gate electrode G3 of the third transistor T3, a gate electrode G4 of the fourth transistor T4, a gate electrode G5 of the fifth transistor T5, a gate electrode G6 of the sixth transistor T6, a gate electrode G7 of the seventh transistor T7, and a gate electrode G8 of the eighth transistor T8. Various appropriate electrode materials and various appropriate fabricating methods may be used to make the first conductive layer. For example, a conductive material may be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of appropriate conductive materials for making the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum copper alloy, copper molybdenum alloy, molybdenum aluminum alloy, aluminum chromium alloy, copper chromium alloy, molybdenum chromium alloy, copper molybdenum aluminum alloy, and the like.
Referring to FIG. 14A and FIG. 14D, in some embodiments, the second conductive layer includes a first electrode S4 of the fourth transistor T4, a second electrode D4 of the fourth transistor T4, a first electrode S5 of the fifth transistor T5, a second electrode D5 of the fifth transistor T5, and multiple connecting lines. Various appropriate electrode materials and various appropriate fabricating methods may be used to make the second conductive layer. For example, a conductive material may be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of appropriate conductive materials for making the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum copper alloy, copper molybdenum alloy, molybdenum aluminum alloy, aluminum chromium alloy, copper chromium alloy, molybdenum chromium alloy, copper molybdenum aluminum alloy, and the like.
Referring to FIG. 14A and FIG. 14E, in some embodiments, the first signal line layer includes a second capacitor electrode Ce2 of the first capacitor C1 and a fourth capacitor electrode Ce4 of the second capacitor C2. Various appropriate conductive materials and various appropriate fabricating methods may be used to make the first signal line layer. For example, a conductive material may be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of appropriate conductive materials for making the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum copper alloy, copper molybdenum alloy, molybdenum aluminum alloy, aluminum chromium alloy, copper chromium alloy, molybdenum chromium alloy, copper molybdenum aluminum alloy, and the like. In some embodiments, the first signal line layer includes a plurality of sub-layers stacked together. In one example, the first signal line layer includes a stacked titanium/aluminum/titanium multi-layer structure. In another example, the first signal line layer includes a stacked molybdenum/aluminum/molybdenum multi-layer structure.
Referring to FIG. 14A and FIG. 14F, in some embodiments, the second signal line layer includes a first power supply signal line VGLL configured to provide a first power supply signal, a second power supply signal line VGHL configured to provide a second power supply signal, a first clock signal line CKL configured to provide a first clock signal, a second clock signal line CBL configured to provide a second clock signal, a start signal line STVL configured to provide a start signal, a first reset signal supply line Vint1 configured to provide a first reset signal, a second reset signal supply line Vint2 configured to provide a second reset signal, and a third reset signal supply line Vint3 configured to provide a third reset signal. Various appropriate conductive materials and various appropriate fabricating methods may be used to make the second signal line layer. For example, a conductive material may be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of appropriate conductive materials for making the second signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum copper alloy, copper molybdenum alloy, molybdenum aluminum alloy, aluminum chromium alloy, copper chromium alloy, molybdenum chromium alloy, copper molybdenum aluminum alloy, and the like. In some embodiments, the second signal line layer includes a plurality of sub-layers stacked together. In one example, the second signal line layer includes a stacked titanium/aluminum/titanium multi-layer structure. In another example, the second signal line layer includes a stacked molybdenum/aluminum/molybdenum multi-layer structure.
Referring to FIG. 14A to FIG. 14F, a respective scan unit of the scan circuit in some embodiments includes a first pad PAD1 and a second pad PAD2. Optionally, the first pad PAD1 and the second pad PAD2 are in the first conductive layer. In some embodiments, the first pad PAD1 includes the gate electrode G7 of the seventh transistor T7. In some embodiments, the second pad PAD2 includes the gate electrode G1 of the first transistor T1 and the gate electrode G3 of the third transistor T3. Optionally, the first pad PAD1 is a unitary structure. Optionally, the second pad PAD2 is a unitary structure.
In some embodiments, the first pad PAD1 in a scan unit in a (2k-1) -th row is connected to the first electrode S5 of the fifth transistor T5 in the scan unit in the (2k-1) -th row. In some embodiments, the first pad PAD1 in a scan unit in a (2k) -th row is connected to the first electrode S5 of the fifth transistor T5 in the scan unit in the (2k) -th row.
FIG. 14G is a diagram illustrating the connectivity of a first connecting line and a second connecting line in the scan circuit depicted in FIG. 14A. Referring to FIG. 14A to FIG. 14G, the scan circuit in some embodiments includes a plurality of first connecting lines CL1. Optionally, the plurality of first connecting lines CL1 are in the second conductive layer. Optionally, a respective first connecting line of the plurality of first connecting lines CL1 is in a scan unit in a (2k-1) -th row, and absent in a scan unit in a (2k) -th row.
In some embodiments, a respective first connecting line of the plurality of first connecting lines CL1 in a scan unit in a (2k-1) -th row is electrically connected to the gate electrode G7 of the seventh transistor T7 in the scan unit in the (2k-1) -th row, is electrically connected to the first electrode S5 of the fifth transistor T5 in the scan unit in the (2k-1) -th row, is electrically connected to the gate electrode G1 of the first transistor T1 and the gate electrode G3 of the third transistor T3 in a scan unit in a (2k) -th row, is electrically connected to the first electrode S2 of the second transistor T2 in the scan unit in the (2k) -th row, and is electrically connected to the first clock signal line CKL.
In some embodiments, the respective first connecting line is connected to the first pad PAD1 in the scan unit in the (2k-1) -th row, is connected to the second pad PAD2 in the scan unit in the (2k) -th row, is connected to the first electrode S2 of the second transistor T2 in the scan unit in the (2k) -th row, and is connected to the first clock signal line CKL.
Referring to FIG. 14A to FIG. 14F, the scan circuit in some embodiments includes a plurality of second connecting lines CL2. Optionally, the plurality of second connecting lines CL2 are in the second conductive layer. Optionally, a respective second connecting line of the plurality of second connecting lines CL2 is in a scan unit in a (2k) -th row, and absent in a scan unit in a (2k-1) -th row.
In some embodiments, a respective second connecting line of the plurality of second connecting lines CL2 in a scan unit in a (2k) -th row is electrically connected to the gate electrode G7 of the seventh transistor T7 in the scan unit in the (2k) -th row, is electrically connected to the first electrode S5 of the fifth transistor T5 in the scan unit in the (2k) -th row, is electrically connected to the gate electrode G1 of the first transistor T1 and the gate electrode G3 of the third transistor T3 in a scan unit in a (2k+1) -th row, is electrically connected to the first electrode S2 of the second transistor T2 in the scan unit in the (2k+1) -th row, and is electrically connected to the second clock signal line CBL.
In some embodiments, the respective second connecting line is connected to the first pad PAD1 in the scan unit in the (2k) -th row, is connected to the second pad PAD2 in the scan unit in the (2k+1) -th row, is connected to the first electrode S2 of the second transistor T2 in the scan unit in the (2k+1) -th row, and is connected to the first clock signal line CBL.
The scan units of the scan circuit depicted in FIG. 14A to FIG. 14F correspond to the scan units depicted in FIG. 1 and FIG. 3. The scan unit in the (2k) -th row in the scan circuit depicted in FIG. 14A to FIG. 14F corresponds to the scan unit depicted in FIG. 1. The scan units in the (2k-1) -th row and the (2k+1) -th row in the scan circuit depicted in FIG. 14A to FIG. 14F corresponds to the scan unit depicted in FIG. 3.
FIG. 15A is a diagram illustrating the structure of multiple scan units in multiple rows of a scan circuit in some embodiments according to the present disclosure. FIG. 15B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 15A. FIG. 15C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 15A. FIG. 15D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 15A. FIG. 15E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 15A. FIG. 15F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 15A. FIG. 15G is a diagram illustrating the structure of a third signal line layer in the scan circuit depicted in FIG. 15A. FIG. 15A is annotated with labels indicating transistors (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, and T13) and capacitors (C1, C2, and C3) , and signal lines (CBL, CKL, VGLL, VGHL, and STVL) in the respective scan unit.
Referring to FIG. 15A and FIG. 15B, in some embodiments, the semiconductor material layer includes active layers of transistors in the respective scan unit. FIG. 15B is annotated with labels indicating the active layers of the transistors in the respective scan unit, for example, an active layer ACT1 of the first transistor T1, an active layer ACT2 of the second transistor T2, an active layer ACT3 of the third transistor T3, an active layer ACT4 of the fourth transistor T4, an active layer ACT5 of the fifth transistor T5, an active layer ACT6 of the sixth transistor T6, an active layer ACT7 of the seventh transistor T7, an active layer ACT8 of the eighth transistor T8, an active layer ACT9 of the ninth transistor T9, an active layer ACT10 of the tenth transistor T10, an active layer ACT11 of the eleventh transistor T11, an active layer ACT12 of the twelfth transistor T12, and an active layer ACT13 of the thirteenth transistor T13. FIG. 15B is further annotated with labels indicating first electrodes and second electrodes of certain transistors in the respective scan unit. For example, the first transistor T1 includes a first electrode S1 and a second electrode D1, the second transistor T2 includes a first electrode S2 and a second electrode D2, the third transistor T3 includes a first electrode S3 and a second electrode D3, the fourth transistor T4 includes a first electrode S4 and a second electrode D4, the fifth transistor T5 includes a first electrode S5 and a second electrode D5, the sixth transistor T6 includes a first electrode S6 and a second electrode D6, the seventh transistor T7 includes a first electrode S7 and a second electrode D7, the eighth transistor T8 includes a first electrode S8 and a second electrode D8, the eleventh transistor T11 includes a first electrode S11 and a second electrode D11, the twelfth transistor T12 includes a first electrode S12 and a second electrode D12, and the thirteenth transistor T13 includes a first electrode S13 and a second electrode D13.
Referring to FIG. 15A and FIG. 15C, in some embodiments, the first conductive layer includes a first capacitor electrode Ce1 of the first capacitor C1, a third capacitor electrode Ce3 of the second capacitor C2, a fifth capacitor electrode Ce5 of the third capacitor C3, a gate electrode G1 of the first transistor T1, a gate electrode G2 of the second transistor T2, a gate electrode G3 of the third transistor T3, a gate electrode G4 of the fourth transistor T4, a gate electrode G5 of the fifth transistor T5, a gate electrode G6 of the sixth transistor T6, a gate electrode G7 of the seventh transistor T7, a gate electrode G8 of the eighth transistor T8, a gate electrode G9 of the ninth transistor T9, a gate electrode G10 of the tenth transistor T10, a gate electrode G11 of the eleventh transistor T11, a gate electrode G12 of the twelfth transistor T12, and a gate electrode G13 of the thirteenth transistor T13.
Referring to FIG. 15A and FIG. 15D, in some embodiments, the second conductive layer includes a first electrode S9 of the ninth transistor T9, a second electrode D9 of the ninth transistor T9, a first electrode S10 of the tenth transistor T10, a second electrode D10 of the tenth transistor T10, a first power supply signal line VGLL configured to provide a first power supply signal, and multiple connecting lines.
Referring to FIG. 15A and FIG. 15E, in some embodiments, the first signal line layer includes a second capacitor electrode Ce2 of the first capacitor C1, a fourth capacitor electrode Ce4 of the second capacitor C2, and a sixth capacitor electrode Ce6 of the third capacitor C3.
Referring to FIG. 15A and FIG. 15F, in some embodiments, the second signal line layer includes a second power supply signal line VGHL configured to provide a second power supply signal, a first clock signal line CKL configured to provide a first clock signal, a second clock signal line CBL configured to provide a second clock signal, a control signal line CXL configured to provide a control signal to the gate electrode of the thirteenth transistor T13, and a start signal line STVL configured to provide a start signal.
Referring to FIG. 15A and FIG. 15G, in some embodiments, the third signal line layer includes a plurality of output connecting lines OUTCL. A respective output connecting line of the plurality of output connecting lines OUTCL is connected to the second electrode of the ninth transistor T9, and connected to the second electrode of the tenth transistor T10.
Referring to FIG. 15A to FIG. 15F, a respective scan unit of the scan circuit in some embodiments includes a first pad PAD1 and a second pad PAD2. Optionally, the first pad PAD1 and the second pad PAD2 are in the first conductive layer. In some embodiments, the first pad PAD1 includes the gate electrode G7 of the seventh transistor T7. In some embodiments, the second pad PAD2 includes the gate electrode G1 of the first transistor T1 and the gate electrode G3 of the third transistor T3. Optionally, the first pad PAD1 is a unitary structure. Optionally, the second pad PAD2 is a unitary structure.
FIG. 15H is a diagram illustrating the connectivity of a first connecting line and a second connecting line in the scan circuit depicted in FIG. 15A. Referring to FIG. 15A to FIG. 15H, the scan circuit in some embodiments includes a plurality of first connecting lines CL1. Optionally, the plurality of first connecting lines CL1 are in the second conductive layer. Optionally, a respective first connecting line of the plurality of first connecting lines CL1 is in a scan unit in a (2k-1) -th row, and absent in a scan unit in a (2k) -th row.
In some embodiments, a respective first connecting line of the plurality of first connecting lines CL1 in a scan unit in a (2k-1) -th row is electrically connected to the gate electrode G7 of the seventh transistor T7 in the scan unit in the (2k-1) -th row, is electrically connected to the first electrode S4 of the fourth transistor T4 in the scan unit in the (2k-1) -th row, is electrically connected to the first electrode S6 of the sixth transistor T6 in the scan unit in the (2k-1) -th row, is electrically connected to the gate electrode G1 of the first transistor T1 and the gate electrode G3 of the third transistor T3 in a scan unit in a (2k) -th row, and is electrically connected to the first clock signal line CBL.
In some embodiments, the respective first connecting line is connected to the first pad PAD1 in the scan unit in the (2k-1) -th row, is connected to the second pad PAD2 in the scan unit in the (2k) -th row, is connected to the first electrode S4 of the fourth transistor T4 in the scan unit in the (2k-1) -th row, is connected to the first electrode S6 of the sixth transistor T6 in the scan unit in the (2k-1) -th row, and is connected to the first clock signal line CBL.
Referring to FIG. 15A to FIG. 15F, the scan circuit in some embodiments includes a plurality of second connecting lines CL2. Optionally, the plurality of second connecting lines CL2 are in the second conductive layer. Optionally, a respective second connecting line of the plurality of second connecting lines CL2 is in a scan unit in a (2k) -th row, and absent in a scan unit in a (2k-1) -th row.
In some embodiments, a respective second connecting line of the plurality of second connecting lines CL2 in a scan unit in a (2k) -th row is electrically connected to the gate electrode G7 of the seventh transistor T7 in the scan unit in the (2k) -th row, is electrically connected to the first electrode S4 of the fourth transistor T4 in the scan unit in the (2k) -th row, is electrically connected to the first electrode S6 of the sixth transistor T6 in the scan unit in the (2k) -th row, is electrically connected to the gate electrode G1 of the first transistor T1 and the gate electrode G3 of the third transistor T3 in a scan unit in a (2k+1) -th row, and is electrically connected to the second clock signal line CKL.
In some embodiments, the respective second connecting line is connected to the first pad PAD1 in the scan unit in the (2k) -th row, is connected to the second pad PAD2 in the scan unit in the (2k+1) -th row, is connected to the first electrode S4 of the fourth transistor T4 in the scan unit in the (2k) -th row, is connected to the first electrode S6 of the sixth transistor T6 in the scan unit in the (2k) -th row, and is connected to the first clock signal line CKL.
The scan units of the scan circuit depicted in FIG. 15A to FIG. 15G correspond to the scan units depicted in FIG. 7 and FIG. 8. The scan unit in the (2k) -th row in the scan circuit depicted in FIG. 15A to FIG. 15F corresponds to the scan unit depicted in FIG. 8. The scan units in the (2k-1) -th row and the (2k+1) -th row in the scan circuit depicted in FIG. 15A to FIG. 15F corresponds to the scan unit depicted in FIG. 7.
FIG. 16A is a diagram illustrating the structure of multiple scan units in multiple rows of a scan circuit in some embodiments according to the present disclosure. FIG. 16B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 16A. FIG. 16C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 16A. FIG. 16D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 16A. FIG. 16E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 16A. FIG. 16F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 16A. FIG. 16G is a diagram illustrating the structure of a third signal line layer in the scan circuit depicted in FIG. 16A. FIG. 16A is annotated with labels indicating transistors (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, and T15) and capacitors (C1, C2, and C3) , and signal lines (CBL, CKL, CXL, VGLL, STVL1, STVL2, VGLL1, VGLL2, VGLL3, VGHL1, VGHL2, and VGHL3) in the respective scan unit.
Referring to FIG. 16A and FIG. 16B, in some embodiments, the semiconductor material layer includes active layers of transistors in the respective scan unit. FIG. 16B is annotated with labels indicating the active layers of the transistors in the respective scan unit, for example, an active layer ACT1 of the first transistor T1, an active layer ACT2 of the second transistor T2, an active layer ACT3 of the third transistor T3, an active layer ACT4 of the fourth transistor T4, an active layer ACT5 of the fifth transistor T5, an active layer ACT6 of the sixth transistor T6, an active layer ACT7 of the seventh transistor T7, an active layer ACT8 of the eighth transistor T8, an active layer ACT9 of the ninth transistor T9, an active layer ACT10 of the tenth transistor T10, an active layer ACT11 of the eleventh transistor T11, an active layer ACT12 of the twelfth transistor T12, an active layer ACT13 of the thirteenth transistor T13, an active layer ACT14 of the fourteenth transistor T14, an active layer ACT15 of the fifteenth transistor T15, and an active layer ACT16 of the sixteenth transistor T16. FIG. 16B is further annotated with labels indicating first electrodes and second electrodes of certain transistors in the respective scan unit. For example, the first transistor T1 includes a first electrode S1 and a second electrode D1, the second transistor T2 includes a first electrode S2 and a second electrode D2, the third transistor T3 includes a first electrode S3 and a second electrode D3, the fourth transistor T4 includes a first electrode S4 and a second electrode D4, the fifth transistor T5 includes a first electrode S5 and a second electrode D5, the sixth transistor T6 includes a first electrode S6 and a second electrode D6, the seventh transistor T7 includes a first electrode S7 and a second electrode D7, the eighth transistor T8 includes a first electrode S8 and a second electrode D8, the eleventh transistor T11 includes a first electrode S11 and a second electrode D11, the twelfth transistor T12 includes a first electrode S12 and a second electrode D12, the thirteenth transistor T13 includes a first electrode S13 and a second electrode D13, the fourteenth transistor T14 includes a first electrode S14 and a second electrode D14, the fifteenth transistor T15 includes a first electrode S15 and a second electrode D15, and the sixteenth transistor T16 includes a first electrode S16 and a second electrode D16.
Referring to FIG. 16A and FIG. 16C, in some embodiments, the first conductive layer includes a first capacitor electrode Ce1 of the first capacitor C1, a third capacitor electrode Ce3 of the second capacitor C2, a fifth capacitor electrode Ce5 of the third capacitor C3, a gate electrode G1 of the first transistor T1, a gate electrode G2 of the second transistor T2, a gate electrode G3 of the third transistor T3, a gate electrode G4 of the fourth transistor T4, a gate electrode G5 of the fifth transistor T5, a gate electrode G6 of the sixth transistor T6, a gate electrode G7 of the seventh transistor T7, a gate electrode G8 of the eighth transistor T8, a gate electrode G9 of the ninth transistor T9, a gate electrode G10 of the tenth transistor T10, a gate electrode G11 of the eleventh transistor T11, a gate electrode G12 of the twelfth transistor T12, a gate electrode G13 of the thirteenth transistor T13, a gate electrode G14 of the fourteenth transistor T14, a gate electrode G15 of the fifteenth transistor T15, and a gate electrode G16 of the sixteenth transistor T16.
Referring to FIG. 16A and FIG. 16D, in some embodiments, the second conductive layer includes a first electrode S9 of the ninth transistor T9, a second electrode D9 of the ninth transistor T9, a first electrode S10 of the tenth transistor T10, a second electrode D10 of the tenth transistor T10.
Referring to FIG. 16A and FIG. 16E, in some embodiments, the first signal line layer includes a second capacitor electrode Ce2 of the first capacitor C1, a fourth capacitor electrode Ce4 of the second capacitor C2, and a sixth capacitor electrode Ce6 of the third capacitor C3.
Referring to FIG. 16A and FIG. 16F, in some embodiments, the second signal line layer includes a first clock signal line CKL configured to provide a first clock signal, a second clock signal line CBL configured to provide a second clock signal, a first start signal line STVL1 configured to provide a start signal, a second start signal line STVL2 configured to provide a start signal, a control signal line CXL configured to provide a control signal to the gate electrode of the thirteenth transistor T13, a plurality of first power supply signal lines (e.g., VGLL1, VGLL2, and VGLL3) configured to provide a first power supply signal, and a plurality of second power supply signal lines (e.g., VGHL1 and VGHL2) configured to provide a second power supply signal.
Referring to FIG. 16A and FIG. 16G, in some embodiments, the third signal line layer includes a plurality of first power supply connecting lines VGLCL configured to connect at least two of the plurality of first power supply lines.
Referring to FIG. 16A to FIG. 16G, the scan circuit in some embodiments includes a first pad PAD1. Optionally, the first pad PAD1 is in the first conductive layer. Optionally, the first pad PAD1 includes the gate electrode G7 of the seventh transistor T7 in a scan unit in a (2k) -th row. The first pad PAD1 extends from an area having a scan unit in the (2k-1) -th row into an area having a scan unit in the (2k) -th row, and is connected to the second power supply line CKL at the position.
FIG. 17A is a diagram illustrating the structure of multiple scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scan circuit in some embodiments according to the present disclosure. FIG. 17B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 17A. FIG. 17C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 17A. FIG. 17D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 17A. FIG. 17E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 17A. FIG. 17F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 17A. FIG. 17G is a diagram illustrating the connectivity of a first connecting line in the scan circuit depicted in FIG. 17A. FIG. 17A is annotated with labels indicating transistors (T1, T2, T3, T4, T5, T6, T7, and T8) and capacitors (C1 and C2) of the scan unit, dummy transistors (DT1, DT2, DT3, DT4, DT5, DT6, DT7, and DT8) and dummy capacitors (DC1 and DC2) of the dummy scan unit, and signal lines (CBL, CKL, VGLL, VGHL, STVL, Vint1, Vint2, and Vint3) in the respective scan unit.
As used herein, the term “dummy” refers to a unit that has a structure that is the same as or similar to a scan unit, but the structure is only used for a configuration existing as a pattern, without actually performing a function in the scan circuit. Thus, an electrical signal may not be applied to a “dummy” scan unit or even in a case in which an electrical signal is applied thereto, the “dummy” scan unit may not perform an electrically equivalent function.
Referring to FIG. 17A to FIG. 17G, an area encircled by dotted lines indicates an area having the one or more dummy scan units. In some embodiments, the scan circuit includes a scan unit in the (2k-1) -th row and a scan unit in the (2k) -th row, and one or more dummy scan units spacing apart the scan unit in the (2k-1) -th row and the scan unit in the (2k) -th row.
Referring to FIG. 17A and FIG. 17B, in some embodiments, the semiconductor material layer includes active layers of transistors in the respective scan unit. FIG. 17B is annotated with labels indicating the active layers of the transistors in the respective scan unit, for example, an active layer ACT1 of the first transistor T1, an active layer ACT2 of the second transistor T2, an active layer ACT3 of the third transistor T3, an active layer ACT4 of the fourth transistor T4, an active layer ACT5 of the fifth transistor T5, an active layer ACT6 of the sixth transistor T6, an active layer ACT7 of the seventh transistor T7, and an active layer ACT8 of the eighth transistor T8. FIG. 17B is further annotated with labels indicating dummy active layers of the dummy transistors in the respective dummy scan unit, for example, a dummy active layer DACT1 of the first dummy transistor DT1, a dummy active layer DACT2 of the second dummy transistor DT2, a dummy active layer DACT3 of the third dummy transistor DT3, a dummy active layer DACT4 of the fourth dummy transistor DT4, a dummy active layer DACT5 of the fifth dummy transistor DT5, a dummy active layer DACT6 of the sixth dummy transistor DT6, a dummy active layer DACT7 of the seventh dummy transistor DT7, and a dummy active layer DACT8 of the eighth dummy transistor DT8. FIG. 17B is further annotated with labels indicating first electrodes and second electrodes of certain transistors in the respective scan unit. For example, the first transistor T1 includes a first electrode S1 and a second electrode D1, the second transistor T2 includes a first electrode S2 and a second electrode D2, the third transistor T3 includes a first electrode S3 and a second electrode D3, the sixth transistor T6 includes a first electrode S6 and a second electrode D6, the seventh transistor T7 includes a first electrode S7 and a second electrode D7, and the eighth transistor T8 includes a first electrode S8 and a second electrode D8. FIG. 17B is further annotated with labels indicating dummy first electrodes and dummy second electrodes of certain dummy transistors in the respective scan unit. For example, the first dummy transistor DT1 includes a dummy first electrode DS1 and a dummy second electrode DD1, the second dummy transistor DT2 includes a dummy first electrode DS2 and a dummy second electrode DD2, the third dummy transistor DT3 includes a dummy first electrode DS3 and a dummy second electrode DD3, the sixth dummy transistor DT6 includes a dummy first electrode DS6 and a dummy second electrode DD6, the seventh dummy transistor DT7 includes a dummy first electrode DS7 and a dummy second electrode DD7, and the eighth dummy transistor DT8 includes a dummy first electrode DS8 and a dummy second electrode DD8.
Referring to FIG. 17A and FIG. 17C, in some embodiments, the first conductive layer includes, with respect to the scan unit, a first capacitor electrode Ce1 of the first capacitor C1, a third capacitor electrode Ce3 of the second capacitor C2, a gate electrode G1 of the first transistor T1, a gate electrode G2 of the second transistor T2, a gate electrode G3 of the third transistor T3, a gate electrode G4 of the fourth transistor T4, a gate electrode G5 of the fifth transistor T5, a gate electrode G6 of the sixth transistor T6, a gate electrode G7 of the seventh transistor T7, and a gate electrode G8 of the eighth transistor T8. In some embodiments, the first conductive layer further includes, with respect to the dummy scan unit, a dummy first capacitor electrode DCe1 of a first dummy capacitor DC1, a dummy third capacitor electrode DCe3 of a second dummy capacitor DC2, a dummy gate electrode DG1 of the first dummy transistor DT1, a dummy gate electrode DG2 of the second dummy transistor DT2, a dummy gate electrode DG3 of the third dummy transistor DT3, a dummy gate electrode DG4 of the fourth dummy transistor DT4, a dummy gate electrode DG5 of the fifth dummy transistor DT5, a dummy gate electrode DG6 of the sixth dummy transistor DT6, a dummy gate electrode DG7 of the seventh dummy transistor DT7, and a dummy gate electrode DG8 of the eighth dummy transistor DT8.
Referring to FIG. 17A and FIG. 17D, in some embodiments, the second conductive layer includes, with respect to the scan unit, a first electrode S4 of the fourth transistor T4, a second electrode D4 of the fourth transistor T4, a first electrode S5 of the fifth transistor T5, a second electrode D5 of the fifth transistor T5, and multiple connecting lines. In some embodiments, the second conductive layer further includes, with respect to the dummy scan unit, a dummy first electrode DS4 of the fourth dummy transistor DT4, a dummy second electrode DD4 of the fourth dummy transistor DT4, a dummy first electrode DS5 of the fifth dummy transistor DT5, a dummy second electrode DD5 of the fifth dummy transistor DT5.
Referring to FIG. 17A and FIG. 17E, in some embodiments, the first signal line layer includes, with respect to the scan unit, a second capacitor electrode Ce2 of the first capacitor C1 and a fourth capacitor electrode Ce4 of the second capacitor C2. In some embodiments, the first signal line layer further includes, with respect to the dummy scan unit, a dummy second capacitor electrode DCe2 of the first dummy capacitor DC1 and a dummy fourth capacitor electrode DCe4 of the second dummy capacitor DC2.
Referring to FIG. 17A and FIG. 17F, in some embodiments, the second signal line layer includes a first power supply signal line VGLL configured to provide a first power supply signal, a second power supply signal line VGHL configured to provide a second power supply signal, a first clock signal line CKL configured to provide a first clock signal, a second clock signal line CBL configured to provide a second clock signal, a start signal line STVL configured to provide a start signal, a first reset signal supply line Vint1 configured to provide a first reset signal, a second reset signal supply line Vint2 configured to provide a second reset signal, and a third reset signal supply line Vint3 configured to provide a third reset signal.
Referring to FIG. 17A to FIG. 17F, a respective scan unit of the scan circuit in some embodiments includes a first pad PAD1 and a second pad PAD2. Optionally, the first pad PAD1 and the second pad PAD2 are in the first conductive layer. In some embodiments, the first pad PAD1 includes the gate electrode G7 of the seventh transistor T7. In some embodiments, the second pad PAD2 includes the gate electrode G1 of the first transistor T1 and the gate electrode G3 of the third transistor T3. Optionally, the first pad PAD1 is a unitary structure. Optionally, the second pad PAD2 is a unitary structure.
In some embodiments, the first pad PAD1 in a scan unit in a (2k-1) -th row is connected to the first electrode S5 of the fifth transistor T5 in the scan unit in the (2k-1) -th row. In some embodiments, the first pad PAD1 in a scan unit in a (2k) -th row is connected to the first electrode S5 of the fifth transistor T5 in the scan unit in the (2k) -th row.
FIG. 17G is a diagram illustrating the connectivity of a first connecting line and a second connecting line in the scan circuit depicted in FIG. 17A. Referring to FIG. 17A to FIG. 17G, the scan circuit in some embodiments includes a plurality of first connecting lines CL1. Optionally, the plurality of first connecting lines CL1 are in the second conductive layer.
In some embodiments, an individual first connecting line of the plurality of first connecting lines CL1 extends from the scan unit in a (2k-1) -th row, through an area having the one or more dummy scan units, and into the scan unit in a (2k) -th row.
In some embodiments, a respective first connecting line of the plurality of first connecting lines CL1 in a scan unit in a (2k-1) -th row is electrically connected to the gate electrode G7 of the seventh transistor T7 in the scan unit in the (2k-1) -th row, is electrically connected to the first electrode S5 of the fifth transistor T5 in the scan unit in the (2k-1) -th row, is electrically connected to the gate electrode G1 of the first transistor T1 and the gate electrode G3 of the third transistor T3 in a scan unit in a (2k) -th row, is electrically connected to the first electrode S2 of the second transistor T2 in the scan unit in the (2k) -th row, and is electrically connected to the first clock signal line CKL.
In some embodiments, the individual first connecting line is connected to the first pad PAD1 in the scan unit in the (2k-1) -th row, extends through the area having the one or more dummy scan units, is connected to the second pad PAD2 in the scan unit in the (2k) -th row, is connected to the first electrode S2 of the second transistor T2 in the scan unit in the (2k) -th row, and is connected to the first clock signal line CKL.
Referring to FIG. 14A to FIG. 14G, and FIG. 17A to FIG. 17F, the scan circuit in some embodiments includes a plurality of second connecting lines CL2. Optionally, the plurality of second connecting lines CL2 are in the second conductive layer.
In some embodiments, a respective second connecting line of the plurality of second connecting lines CL2 in a scan unit in a (2k) -th row is electrically connected to the gate electrode G7 of the seventh transistor T7 in the scan unit in the (2k) -th row, is electrically connected to the first electrode S5 of the fifth transistor T5 in the scan unit in the (2k) -th row, is electrically connected to the gate electrode G1 of the first transistor T1 and the gate electrode G3 of the third transistor T3 in a scan unit in a (2k+1) -th row, is electrically connected to the first electrode S2 of the second transistor T2 in the scan unit in the (2k+1) -th row, and is electrically connected to the second clock signal line CBL.
In some embodiments, the respective second connecting line is connected to the first pad PAD1 in the scan unit in the (2k) -th row, is connected to the second pad PAD2 in the scan unit in the (2k+1) -th row, is connected to the first electrode S2 of the second transistor T2 in the scan unit in the (2k+1) -th row, and is connected to the first clock signal line CBL.
The scan units of the scan circuit depicted in FIG. 17A to FIG. 17F correspond to the scan units depicted in FIG. 1 and FIG. 3. The scan unit in the (2k) -th row in the scan circuit depicted in FIG. 17A to FIG. 17F corresponds to the scan unit depicted in FIG. 1. The scan units in the (2k-1) -th row and the (2k+1) -th row in the scan circuit depicted in FIG. 17A to FIG. 17F corresponds to the scan unit depicted in FIG. 3.
In the scan circuit depicted in FIG. 17A to FIG. 17G, because the individual first connecting line extends through the area having the one or more dummy scan units, and the respective first connecting line is connected to the first clock signal line CKL. In comparison, the respective second connecting line does not have to extend through the area having the one or more dummy scan units, the respective second connecting line is connected to the second clock signal line CBL. The respective first connecting line has an increased length as compared to the respective second connecting line. The difference results in different loading between the first clock signal line CKL and the second clock signal line CBL. In some embodiments, the loading on the first clock signal line CKL is significantly larger than the loading on the second clock signal line CBL due to this difference. As shown in FIG. 1 and FIG. 3, the output of the respective scan unit in the (2k-1) -th row is the second clock signal line CBL, and the output of the respective scan unit in the (2k) -th row is the first clock signal line CKL. The difference in the loading on the first clock signal line CKL and the loading on the second clock signal line CBL directly affects the output waveform of the scan circuit. Moreover, even in regions distant from the one or more dummy scan unit, the output signals from a scan unit in an odd-numbered row and a scan unit in an even-numbered row differ from each other due to the disparity between the loading on the first clock signal line CKL and the loading on the second clock signal line CBL, leading to display non-uniformity in a display panel connected to the scan circuit depicted in FIG. 17A to FIG. 17G.
FIG. 18A is a diagram illustrating the structure of multiple scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scan circuit in some embodiments according to the present disclosure. FIG. 18B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 18A. FIG. 18C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 18A. FIG. 18D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 18A. FIG. 18E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 18A. FIG. 18F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 18A. FIG. 18G is a diagram illustrating the structure of a third signal line layer in the scan circuit depicted in FIG. 18A. FIG. 18H is a diagram illustrating the connectivity of a first connecting line in the scan circuit depicted in FIG. 18A.
Referring to FIG. 18A to FIG. 18H, an area encircled by dotted lines indicates an area having the one or more dummy scan units DSU. In some embodiments, the scan circuit includes a scan unit in the (2k-1) -th row and a scan unit in the (2k) -th row, and one or more dummy scan units DSU spacing apart the scan unit in the (2k-1) -th row and the scan unit in the (2k) -th row.
In some embodiments, the scan circuit includes a plurality of first connecting lines CL1. Optionally, the plurality of first connecting lines CL1 are in the second conductive layer. In some embodiments, an individual first connecting line of the plurality of first connecting lines CL1 extends from the scan unit in a (2k-1) -th row, through an area having the one or more dummy scan units DSU, and into the scan unit in a (2k) -th row.
In some embodiments, referring to FIG. 15A to FIG. 15G, and FIG. 18A to FIG. 18H, a respective first connecting line of the plurality of first connecting lines CL1 in a scan unit in a (2k-1) -th row is electrically connected to the gate electrode G7 of the seventh transistor T7 in the scan unit in the (2k-1) -th row, is electrically connected to the first electrode S4 of the fourth transistor T4 in the scan unit in the (2k-1) -th row, is electrically connected to the first electrode S6 of the sixth transistor T6 in the scan unit in the (2k-1) -th row, is electrically connected to the gate electrode G1 of the first transistor T1 and the gate electrode G3 of the third transistor T3 in a scan unit in a (2k) -th row, and is electrically connected to the first clock signal line CBL.
In some embodiments, referring to FIG. 15A to FIG. 15G, and FIG. 18A to FIG. 18H, the individual first connecting line is connected to the first pad PAD1 in the scan unit in the (2k-1) -th row, is connected to the first electrode S4 of the fourth transistor T4 in the scan unit in the (2k-1) -th row, is connected to the first electrode S6 of the sixth transistor T6 in the scan unit in the (2k-1) -th row, extends through the area having the one or more dummy scan units DSU, is connected to the second pad PAD2 in the scan unit in the (2k) -th row, and is connected to the first clock signal line CBL.
Referring to FIG. 15A to FIG. 15G, and FIG. 18A to FIG. 18H, the scan circuit in some embodiments includes a plurality of second connecting lines CL2. Optionally, the plurality of second connecting lines CL2 are in the second conductive layer.
In some embodiments, a respective second connecting line of the plurality of second connecting lines CL2 in a scan unit in a (2k) -th row is electrically connected to the gate electrode G7 of the seventh transistor T7 in the scan unit in the (2k) -th row, is electrically connected to the first electrode S4 of the fourth transistor T4 in the scan unit in the (2k) -th row, is electrically connected to the first electrode S6 of the sixth transistor T6 in the scan unit in the (2k) -th row, is electrically connected to the gate electrode G1 of the first transistor T1 and the gate electrode G3 of the third transistor T3 in a scan unit in a (2k+1) -th row, and is electrically connected to the second clock signal line CKL.
In some embodiments, the respective second connecting line is connected to the first pad PAD1 in the scan unit in the (2k) -th row, is connected to the second pad PAD2 in the scan unit in the (2k+1) -th row, is connected to the first electrode S4 of the fourth transistor T4 in the scan unit in the (2k) -th row, is connected to the first electrode S6 of the sixth transistor T6 in the scan unit in the (2k) -th row, and is connected to the first clock signal line CKL.
The scan units of the scan circuit depicted in FIG. 18A to FIG. 18H, correspond to the scan units depicted in FIG. 7 and FIG. 8. The scan unit in the (2k) -th row in the scan circuit depicted in FIG. 18A to FIG. 18G, corresponds to the scan unit depicted in FIG. 8. The scan unit in the (2k-1) -th row in the scan circuit depicted in FIG. 18A to FIG. 18G, corresponds to the scan unit depicted in FIG. 7.
In the scan circuit depicted in FIG. 18A to FIG. 18G, because the individual first connecting line extends through the area having the one or more dummy scan units, and the respective first connecting line is connected to the first clock signal line CKL. In comparison, the respective second connecting line does not have to extend through the area having the one or more dummy scan units, the respective second connecting line is connected to the second clock signal line CBL. The respective first connecting line has an increased length as compared to the respective second connecting line. The difference results in different loading between the first clock signal line CKL and the second clock signal line CBL. In some embodiments, the loading on the first clock signal line CKL is significantly larger than the loading on the second clock signal line CBL due to this difference. As shown in FIG. 1 and FIG. 3, the output of the respective scan unit in the (2k-1) -th row is the second clock signal line CBL, and the output of the respective scan unit in the (2k) -th row is the first clock signal line CKL. The difference in the loading on the first clock signal line CKL and the loading on the second clock signal line CBL directly affects the output waveform of the scan circuit. Moreover, even in regions distant from the one or more dummy scan unit, the output signals from a scan unit in an odd-numbered row and a scan unit in an even-numbered row differ from each other due to the disparity between the loading on the first clock signal line CKL and the loading on the second clock signal line CBL, leading to display non-uniformity in a display panel connected to the scan circuit depicted in FIG. 18A to FIG. 18G.
FIG. 19A is a diagram illustrating the structure of multiple scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scan circuit in some embodiments according to the present disclosure. FIG. 19B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 19A. FIG. 19C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 19A. FIG. 19D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 19A. FIG. 19E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 19A. FIG. 19F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 19A. FIG. 19G is a diagram illustrating the structure of a third signal line layer in the scan circuit depicted in FIG. 19A.
[Rectified under Rule 91, 01.12.2023]
Referring to FIG. 19A to FIG. 19G, an area encircled by dotted lines indicates an area having the one or more dummy scan units DSU. In some embodiments, the scan circuit includes a scan unit in the (2k-1) -th row and a scan unit in the (2k) -th row, and one or more dummy scan units DSU spacing apart the scan unit in the (2k-1) -th row and the scan unit in the (2k) -th row.
The scan units of the scan circuit depicted in FIG. 19A to FIG. 19G, correspond to the scan circuit depicted in FIG. 16A to FIG. 16G. The scan unit in the (2k) -th row in the scan circuit depicted in FIG. 19A to FIG. 19G, corresponds to the scan unit in the (2k) -th row in the scan circuit depicted in FIG. 16A to FIG. 16G. The scan unit in the (2k-1) -th row in the scan circuit depicted in FIG. 19A to FIG. 19G, corresponds to the scan unit in the (2k-1) -th row in the scan circuit depicted in FIG. 16A to FIG. 16G.
Referring to FIG. 19A to FIG. 19G, the scan circuit in some embodiments includes a first pad PAD1. Optionally, the first pad PAD1 is in the first conductive layer. Optionally, the first pad PAD1 includes the gate electrode G7 of the seventh transistor T7 in a scan unit in a (2k) -th row. The first pad PAD1 extends away from an area having a scan unit in the (2k-1) -th row, and is connected to the second power supply line CKL at a position in an area having a scan unit in the (2k-1) -th row.
In some embodiments, the scan circuit includes a first connecting line connecting the first pad PAD1 with the second power supply line CKL at the position in the area having a scan unit in the (2k-1) -th row. In some embodiments, the first connecting line extends through the area having the one or more dummy scan units DSU. In some embodiments, the first pad PAD1 at least partially in an area having a scan unit in a (2k) -th row is connected to the second power supply line CKL at a position in an area having a scan unit in the (2k-1) -th row through the first connecting line.
In some embodiments, the first connecting line includes a first signal connecting line SCL1 and a second signal connecting line SCL2. Optionally, the first signal connecting line SCL1 is in the second conductive layer. Optionally, the second signal connecting line SCL2 is in the first conductive layer. In some embodiments, the first pad PAD1 at least partially in an area having a scan unit in a (2k) -th row is connected to the second power supply line CKL at a position in an area having a scan unit in the (2k-1) -th row through the first signal connecting line SCL1 and the second signal connecting line SCL2. Optionally, the first signal connecting line SCL1 at least partially extends in the area having the one or more dummy scan units DSU. Optionally, the second signal connecting line SCL2 at least partially extends in the area having the one or more dummy scan units DSU.
FIG. 20 is a diagram illustrating the structure of a portion of one or more scan circuits in some embodiments according to the present disclosure. Referring to FIG. 20, a scan unit in the (2k-1) -th row and a scan unit in the (2k) -th row are spaced apart by one or more dummy scan units DSU. An individual first connecting line ICL1 extends through an area having the one or more dummy scan units DSU. The individual first connecting line ICL1 is connected to the first clock signal line CKL, is electrically connected to the scan unit in the (2k) -th row (FIG. 17A to FIG. 17G, FIG. 18A to FIG. 18G) . Optionally, the individual first connecting line ICL1 is further connected to the scan unit in the (2k-1) -th row (FIG. 17A to FIG. 17G, FIG. 18A to FIG. 18G, and FIG. 19A to FIG. 19G) . FIG. 20 shows multiple scan circuits. The inventors of the present disclosure discover that this structure results in a disparity between the loading on the first clock signal line and the loading on the second clock signal line, leading to display non-uniformity in a display panel connected to the scan circuit.
FIG. 21A is a diagram illustrating the structure of multiple scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scan circuit in some embodiments according to the present disclosure. FIG. 21B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 21A. FIG. 21C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 21A. FIG. 21D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 21A. FIG. 21E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 21A. FIG. 21F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 21A. FIG. 21G is a diagram illustrating the connectivity of a first clock signal line and a second clock signal line in the scan circuit depicted in FIG. 21A.
The scan units of the scan circuit depicted in FIG. 21A to FIG. 21G correspond to the scan units of the scan circuit depicted in FIG. 17A to FIG. 17G. The second scan unit SU2 in the scan circuit depicted in FIG. 21A to FIG. 21G corresponds to the scan unit in the (2k) -th row in the scan circuit depicted in FIG. 17A to FIG. 17G. The first scan unit SU1 in the scan circuit depicted in FIG. 21A to FIG. 21G corresponds to the scan unit in the (2k-1) -th row in the scan circuit depicted in FIG. 17A to FIG. 17G. The first dummy scan unit DSU1 and the second dummy scan unit DSU2 depicted in FIG. 21A to FIG. 21G correspond to the one or more dummy scan units DSU depicted in FIG. 17A to FIG. 17G.
FIG. 21A is annotated with labels indicating transistors (T1, T2, T3, T4, T5, T6, T7, and T8) and capacitors (C1 and C2) of the scan unit, dummy transistors (DT1, DT3, DT4, DT5, DT7, and DT8) and a dummy capacitor (DC1) of the dummy scan unit, and signal lines (CBL, CKL, VGLL, VGHL, STVL, Vint1, Vint2, and Vint3) in the respective scan unit.
Referring to FIG. 21A to FIG. 21G, in some embodiments, the scan circuit includes a first scan unit SU1, a first dummy scan unit DSU1, and a second scan unit SU2. Optionally, the first scan unit SU1, the first dummy scan unit DSU1, and the second scan unit SU2 are sequentially arranged. Optionally, the first dummy scan unit DSU1 spaces apart the first scan unit SU1 and the second scan unit SU2.
In some embodiments, the scan circuit further includes a second dummy scan unit DSU2. Optionally, the first scan unit SU1, the second dummy scan unit DSU2, the first dummy scan unit DSU1, and the second scan unit SU2 are sequentially arranged. Optionally, the first dummy scan unit DSU1 spaces apart the second scan unit SU2 and the second dummy scan unit DSU2; and the second dummy scan unit DSU2 spaces apart the first dummy scan unit DSU1 and the first scan unit SU1.
Referring to FIG. 21A and FIG. 21B, in some embodiments, the semiconductor material layer includes active layers of transistors in the respective scan unit. FIG. 21B is annotated with labels indicating the active layers of the transistors in the respective scan unit, for example, an active layer ACT1 of the first transistor T1, an active layer ACT2 of the second transistor T2, an active layer ACT3 of the third transistor T3, an active layer ACT4 of the fourth transistor T4, an active layer ACT5 of the fifth transistor T5, an active layer ACT6 of the sixth transistor T6, an active layer ACT7 of the seventh transistor T7, and an active layer ACT8 of the eighth transistor T8. FIG. 21B is further annotated with labels indicating dummy active layers of the dummy transistors in the respective dummy scan unit, for example, a dummy active layer DACT1 of the first dummy transistor DT1, a dummy active layer DACT3 of the dummy third transistor DT3, a dummy active layer DACT4 of the fourth dummy transistor DT4, a dummy active layer DACT5 of the fifth dummy transistor DT5, and a dummy active layer DACT8 of the eighth dummy transistor DT8. FIG. 21B is further annotated with labels indicating first electrodes and second electrodes of certain transistors in the respective scan unit. For example, the first transistor T1 includes a first electrode S1 and a second electrode D1, the second transistor T2 includes a first electrode S2 and a second electrode D2, the third transistor T3 includes a first electrode S3 and a second electrode D3, the sixth transistor T6 includes a first electrode S6 and a second electrode D6, the seventh transistor T7 includes a first electrode S7 and a second electrode D7, and the eighth transistor T8 includes a first electrode S8 and a second electrode D8. FIG. 21B is further annotated with labels indicating dummy first electrodes and dummy second electrodes of certain dummy transistors in the respective scan unit. For example, the first dummy transistor DT1 includes a dummy first electrode DS1 and a dummy second electrode DD1, the third dummy transistor DT3 includes a dummy first electrode DS3 and a dummy second electrode DD3, the sixth dummy transistor DT6 includes a dummy first electrode DS6, and the eighth dummy transistor DT8 includes a dummy first electrode DS8 and a dummy second electrode DD8.
Referring to FIG. 21A and FIG. 21C, in some embodiments, the first conductive layer includes, with respect to the scan unit, a first capacitor electrode Ce1 of the first capacitor C1, a third capacitor electrode Ce3 of the second capacitor C2, a gate electrode G1 of the first transistor T1, a gate electrode G2 of the second transistor T2, a gate electrode G3 of the third transistor T3, a gate electrode G4 of the fourth transistor T4, a gate electrode G5 of the fifth transistor T5, a gate electrode G6 of the sixth transistor T6, a gate electrode G7 of the seventh transistor T7, and a gate electrode G8 of the eighth transistor T8. In some embodiments, the first conductive layer further includes, with respect to the dummy scan unit, a dummy first capacitor electrode DCe1 of a first dummy capacitor DC1, a dummy gate electrode DG4 of the fourth dummy transistor DT4, a dummy gate electrode DG5 of the fifth dummy transistor DT5, a dummy gate electrode DG6 of the sixth dummy transistor DT6, and a dummy gate electrode DG7 of the seventh dummy transistor DT7.
Referring to FIG. 21A and FIG. 21D, in some embodiments, the second conductive layer includes, with respect to the scan unit, a first electrode S4 of the fourth transistor T4, a second electrode D4 of the fourth transistor T4, a first electrode S5 of the fifth transistor T5, a second electrode D5 of the fifth transistor T5, and multiple connecting lines. In some embodiments, the second conductive layer further includes, with respect to the dummy scan unit, a dummy first electrode DS4 of the fourth dummy transistor DT4, a dummy second electrode DD4 of the fourth dummy transistor DT4, a dummy first electrode DS5 of the fifth dummy transistor DT5, a dummy second electrode DD5 of the fifth dummy transistor DT5, and multiple connecting lines.
Referring to FIG. 21A and FIG. 21E, in some embodiments, the first signal line layer includes, with respect to the scan unit, a second capacitor electrode Ce2 of the first capacitor C1 and a fourth capacitor electrode Ce4 of the second capacitor C2.
Referring to FIG. 21A and FIG. 21F, in some embodiments, the second signal line layer includes a first power supply signal line VGLL configured to provide a first power supply signal, a second power supply signal line VGHL configured to provide a second power supply signal, a first clock signal line CKL configured to provide a first clock signal, a second clock signal line CBL configured to provide a second clock signal, a start signal line STVL configured to provide a start signal, a first reset signal supply line Vint1 configured to provide a first reset signal, a second reset signal supply line Vint2 configured to provide a second reset signal, and a third reset signal supply line Vint3 configured to provide a third reset signal.
Referring to FIG. 21A to FIG. 21F, a respective scan unit of the scan circuit in some embodiments includes a first pad PAD1 and a second pad PAD2. Optionally, the first pad PAD1 and the second pad PAD2 are in the first conductive layer. In some embodiments, the first pad PAD1 includes the gate electrode G7 of the seventh transistor T7. In some embodiments, the second pad PAD2 includes the gate electrode G1 of the first transistor T1 and the gate electrode G3 of the third transistor T3. Optionally, the first pad PAD1 is a unitary structure. Optionally, the second pad PAD2 is a unitary structure.
In some embodiments, a respective dummy scan unit of the scan circuit includes a first dummy pad DPAD1. Optionally, the first dummy pad DPAD1 is in the first conductive layer. In some embodiments, the first dummy pad DPAD1 includes the dummy gate electrode DG7 of the seventh dummy transistor DT7. Optionally, the first dummy pad DPAD1 is a unitary structure.
In some embodiments, the second scan unit SU2 includes a second extension E2 connected to the first pad PAD1 in the second scan unit SU2, and the first pad PAD1 is connected to the first electrode S5 of the fifth transistor T5 in the second scan unit SU2. The second extension E2 in the second scan unit SU2 is electrically connected to the gate electrode G7 of the seventh transistor T7 in the second scan unit SU2. Optionally, the second extension E2 in the second scan unit SU2 is connected to the second clock signal line CBL. Optionally, the second extension E2 is in the second conductive layer.
In some embodiments, the first dummy scan unit DSU1 includes a first dummy extension DE1 connected to the first dummy pad DPAD1 in the first dummy scan unit DSU1. Optionally, the first dummy extension DE1 is connected to the first clock signal line CKL. Optionally, the first dummy extension DE1 is in the second conductive layer.
In some embodiments, the first dummy extension DE1 in the first dummy scan unit DSU1 is connected to the second pad PAD2 in the second scan unit SU2. The first dummy extension DE1 in the first dummy scan unit DSU1 is electrically connected to the gate electrode G1 of the first transistor T1 and the gate electrode G3 of the third transistor T3 in the second scan unit SU2. In some embodiments, the first dummy extension DE1 in the first dummy scan unit DSU1 is further connected to the first electrode S2 of the second transistor T2 in the second scan unit SU2. Because the first dummy extension DE1 in the first dummy scan unit DSU1 is connected to the first clock signal line CKL, the first dummy extension DE1 in the first dummy scan unit DSU1 is configured to transmit the first clock signal to the first electrode S2 of the second transistor T2 in the second scan unit SU2, and to the gate electrode G1 of the first transistor T1 and the gate electrode G3 of the third transistor T3 in the second scan unit SU2.
In some embodiments, the first dummy extension DE1 in the first dummy scan unit DSU1 is further connected to the first dummy pad DPAD1 in the first dummy scan unit DSU1.
In some embodiments, the first dummy pad DPAD1 in the first dummy scan unit DSU1 is disconnected from the dummy first electrode DS5 of the fifth dummy transistor DT5 in the first dummy scan unit DSU1, e.g., by the absence of a via connecting the first dummy pad DPAD1 and the dummy first electrode DS5 of the fifth dummy transistor DT5 in the first dummy scan unit DSU1. In one example, the dummy first electrode DS5 and the dummy second electrode DD5 of the fifth dummy transistor DT5 in the first dummy scan unit DSU1 are parts of a unitary structure. In another example, the dummy first electrode DS5 and the dummy second electrode DD5 of the fifth dummy transistor DT5, and the dummy first electrode DS4 and the dummy second electrode DD4 of the fourth dummy transistor DT4, in the first dummy scan unit DSU1 are parts of a unitary structure.
In some embodiments, the first scan unit SU1 includes a first extension E1 connected to the first pad PAD1 in the first scan unit SU1, and the first pad PAD1 in the first scan unit SU1 is connected to the first electrode S5 of the fifth transistor T5 in the first scan unit SU1. The first extension E1 in the first scan unit SU1 is electrically connected to the gate electrode G7 of the seventh transistor T7 in the first scan unit SU1. Optionally, the first extension E1 in the first scan unit SU1 is connected to the first clock signal line CKL. Optionally, the first extension E1 is in the second conductive layer.
In some embodiments, the first extension E1 in the first scan unit SU1 is electrically isolated from any dummy scan units, e.g., the first extension E1 in the first scan unit SU1 is not connected to any component of dummy transistors or dummy capacitors in any dummy scan units.
In some embodiments, the first extension E1 in the first scan unit SU1 is not connected to the second scan unit SU2, e.g., the first extension E1 in the first scan unit SU1 is not connected to any component of transistors or capacitors in the second scan unit SU2.
In some embodiments, the second dummy scan unit DSU2 includes a second dummy extension DE2 connected to the first dummy pad DPAD1 in the second dummy scan unit DSU2. Optionally, the second dummy scan unit DSU2 is electrically isolated from the first clock signal line CKL and electrically isolated from the second clock signal line CBL. Optionally, the second dummy extension DE2 is in the second conductive layer.
In some embodiments, the second dummy extension DE2 in the second dummy scan unit DSU2 is not connected to any component in the first dummy scan unit DSU1, e.g., the second dummy extension DE2 in the second dummy scan unit DSU2 is not connected to any component of the dummy transistors or dummy capacitors in the first dummy scan unit DSU1.
In some embodiments, the second dummy extension DE2 in the second dummy scan unit DSU2 is not connected to the second scan unit SU2, e.g., the second dummy extension DE2 in the second dummy scan unit DSU2 is not connected to any component of transistors or capacitors in the second scan unit SU2.
In some embodiments, the first dummy pad DPAD1 in the second dummy scan unit DSU2 is connected to the dummy first electrode DS5 of the fifth dummy transistor DT5 in the second dummy scan unit DSU2, e.g., by a via connecting the first dummy pad DPAD1 and the dummy first electrode DS5 of the fifth dummy transistor DT5 in the second dummy scan unit DSU2. In one example, the dummy first electrode DS5 and the dummy second electrode DD5 of the fifth dummy transistor DT5 in the second dummy scan unit DSU2 are parts of a unitary structure. In another example, the dummy first electrode DS5 and the dummy second electrode DD5 of the fifth dummy transistor DT5, and the dummy first electrode DS4 and the dummy second electrode DD4 of the fourth dummy transistor DT4, in the second dummy scan unit DSU2 are parts of a unitary structure. In some embodiments, the dummy first electrode DS4 of the fourth dummy transistor DT4 is connected to the second power supply signal line VGHL configured to provide a second power supply signal. In some embodiments, the first dummy pad DPAD1, the second dummy extension DE2, the dummy first electrode DS5 and the dummy second electrode DD5 of the fifth dummy transistor DT5, and the dummy first electrode DS4 and the dummy second electrode DD4 of the fourth dummy transistor DT4, in the second dummy scan unit DSU2 are configured to be provided with a second power supply signal.
[Rectified under Rule 91, 01.12.2023]
The inventors of the present disclosure discover that, in the scan circuit depicted in FIG. 21A to FIG. 21G, the disparity between the loading on the first clock signal line CKL and the loading on the second clock signal line CBL can be significantly reduced, due to the absence of a connecting line extending through an area having the one or more dummy scan units. The display panel connected to the scan circuit depicted in FIG. 21A to FIG. 21G has significantly improved display uniformity.
FIG. 22A is a diagram illustrating the structure of multiple scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scan circuit in some embodiments according to the present disclosure. FIG. 22B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 22A. FIG. 22C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 22A. FIG. 22D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 22A. FIG. 22E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 22A. FIG. 22F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 22A. FIG. 22G is a diagram illustrating the structure of a third signal line layer in the scan circuit depicted in FIG. 22A. FIG. 22H is a diagram illustrating the connectivity of a first clock signal line and a second clock signal line in the scan circuit depicted FIG. 22A.
The scan units of the scan circuit depicted in FIG. 22A to FIG. 22G correspond to the scan units of the scan circuit depicted in FIG. 18A to FIG. 18G. The second scan unit SU2 in the scan circuit depicted in FIG. 22A to FIG. 22G corresponds to the scan unit in the (2k) -th row in the scan circuit depicted in FIG. 18A to FIG. 18G. The first scan unit SU1 in the scan circuit depicted in FIG. 22A to FIG. 22G corresponds to the scan unit in the (2k-1) -th row in the scan circuit depicted in FIG. 18A to FIG. 18G. The first dummy scan unit DSU1 and the second dummy scan unit DSU2 depicted in FIG. 22A to FIG. 22G correspond to the one or more dummy scan units DSU depicted in FIG. 18A to FIG. 18G.
FIG. 22A is annotated with labels indicating transistors (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, and T13) and capacitors (C1, C2, and C3) of the scan unit, dummy transistors (DT8, DT9, DT10, and DT13) and a dummy capacitor (DC1, DC2, and DC3) of the dummy scan unit, and signal lines (CBL, CKL, VGLL, VGHL, and STVL) in the respective scan unit.
Referring to FIG. 22A to FIG. 22G, in some embodiments, the scan circuit includes a first scan unit SU1, a first dummy scan unit DSU1, and a second scan unit SU2. Optionally, the first scan unit SU1, the first dummy scan unit DSU1, and the second scan unit SU2 are sequentially arranged. Optionally, the first dummy scan unit DSU1 spaces apart the first scan unit SU1 and the second scan unit SU2.
In some embodiments, the scan circuit further includes a second dummy scan unit DSU2. Optionally, the first scan unit SU1, the second dummy scan unit DSU2, the first dummy scan unit DSU1, and the second scan unit SU2 are sequentially arranged. Optionally, the first dummy scan unit DSU1 spaces apart the second scan unit SU2 and the second dummy scan unit DSU2; and the second dummy scan unit DSU2 spaces apart the first dummy scan unit DSU1 and the first scan unit SU1.
Referring to FIG. 22A and FIG. 22B, in some embodiments, the semiconductor material layer includes active layers of transistors in the respective scan unit. FIG. 22B is annotated with labels indicating the active layers of the transistors in the respective scan unit, for example, an active layer ACT1 of the first transistor T1, an active layer ACT2 of the second transistor T2, an active layer ACT4 of the fourth transistor T4, an active layer ACT5 of the fifth transistor T5, an active layer ACT6 of the sixth transistor T6, an active layer ACT7 of the seventh transistor T7, an active layer ACT8 of the eighth transistor T8, an active layer ACT9 of the ninth transistor T9, an active layer ACT10 of the tenth transistor T10, an active layer ACT11 of the eleventh transistor T11, and an active layer ACT12 of the twelfth transistor T12. The respective scan unit in some embodiments further includes an active layer of a third transistor and an active layer of a thirteenth transistor. FIG. 22B is further annotated with labels indicating dummy active layers of the dummy transistors in the respective dummy scan unit, for example, a dummy active layer DACT5 of the fifth dummy transistor DT5, a dummy active layer DACT8 of the eighth dummy transistor DT8, a dummy active layer DACT9 of the ninth dummy transistor DT9, and a dummy active layer DACT10 of the tenth dummy transistor DT10, and a dummy active layer DACT13 of the thirteenth dummy transistor DT13. FIG. 22B is further annotated with labels indicating first electrodes and second electrodes of certain transistors in the respective scan unit. For example, the first transistor T1 includes a first electrode S1 and a second electrode D1, the second transistor T2 includes a first electrode S2 and a second electrode D2, the third transistor T3 includes a first electrode S3 and a second electrode D3, the fourth transistor T4 includes a first electrode S4 and a second electrode D4, the fifth transistor T5 includes a first electrode S5 and a second electrode D5, the sixth transistor T6 includes a first electrode S6 and a second electrode D6, the seventh transistor T7 includes a first electrode S7 and a second electrode D7, the eighth transistor T8 includes a first electrode S8 and a second electrode D8, the eleventh transistor T11 includes a first electrode S11 and a second electrode D11, the twelfth transistor T12 includes a first electrode S12 and a second electrode D12, and the thirteenth transistor T13 includes a first electrode S13 and a second electrode D13. FIG. 22B is further annotated with labels indicating dummy first electrodes and dummy second electrodes of certain dummy transistors in the respective scan unit. For example, the fourth dummy transistor DT4 includes a dummy first electrode DS4 and a dummy second electrode DD4, the fifth dummy transistor DT5 includes a dummy first electrode DS5 and a dummy second electrode DD5, the sixth dummy transistor DT6 includes a dummy first electrode DS6 and a dummy second electrode DD6, the seventh dummy transistor DT7 includes a dummy first electrode DS7, the eighth dummy transistor DT8 includes a dummy first electrode DS8 and a dummy second electrode DD8, and the thirteenth dummy transistor DT13 includes a dummy first electrode DS13 and a dummy second electrode DD13.
Referring to FIG. 22A and FIG. 22C, in some embodiments, the first conductive layer includes, with respect to the scan unit, a first capacitor electrode Ce1 of the first capacitor C1, a third capacitor electrode Ce3 of the second capacitor C2, a fifth capacitor electrode Ce5 of the third capacitor C3, a gate electrode G1 of the first transistor T1, a gate electrode G2 of the second transistor T2, a gate electrode G4 of the fourth transistor T4, a gate electrode G5 of the fifth transistor T5, a gate electrode G6 of the sixth transistor T6, a gate electrode G7 of the seventh transistor T7, a gate electrode G9 of the ninth transistor T9, a gate electrode G10 of the tenth transistor T10, a gate electrode G11 of the eleventh transistor T11, and a gate electrode G12 of the twelfth transistor T12. The respective scan unit in some embodiments further includes a gate electrode of a third transistor and a gate electrode of a thirteenth transistor. In some embodiments, the first conductive layer further includes, with respect to the dummy scan unit, a dummy first capacitor electrode DCe1 of a first dummy capacitor DC1, a dummy third capacitor electrode DCe3 of a second dummy capacitor DC2, a dummy fifth capacitor electrode DCe5 of a third dummy capacitor DC3, a dummy gate electrode DG4 of the fourth dummy transistor DT4, a dummy gate electrode DG6 of the sixth dummy transistor DT6, a dummy gate electrode DG7 of the seventh dummy transistor DT7, a dummy gate electrode DG8 of the eighth dummy transistor DT8, a dummy gate electrode DG9 of the ninth dummy transistor DT9, a dummy gate electrode DG10 of the tenth dummy transistor DT10, and a dummy gate electrode DG13 of the thirteenth dummy transistor DT13.
Referring to FIG. 22A and FIG. 22D, in some embodiments, the second conductive layer includes, with respect to the scan unit, a first electrode S9 of the ninth transistor T9, a second electrode D9 of the ninth transistor T9, a first electrode S10 of the tenth transistor T10, a second electrode D10 of the tenth transistor T10, a first power supply signal line VGLL configured to provide a first power supply signal, and multiple connecting lines. In some embodiments, the second conductive layer further includes, with respect to the dummy scan unit, a dummy first electrode DS9 of the ninth dummy transistor DT9, a dummy second electrode DD9 of the ninth dummy transistor DT9, a dummy first electrode DS10 of the tenth dummy transistor DT10, a dummy second electrode DD10 of the tenth dummy transistor DT10, and multiple connecting lines.
Referring to FIG. 22A and FIG. 22E, in some embodiments, the first signal line layer includes, with respect to the scan unit, a second capacitor electrode Ce2 of the first capacitor C1, a fourth capacitor electrode Ce4 of the second capacitor C2, and a sixth capacitor electrode Ce6 of the third capacitor C3. In some embodiments, the first signal layer further includes, with respect to the dummy scan unit, a dummy second capacitor electrode DCe2 of the first dummy capacitor DC1, a dummy fourth capacitor electrode DCe4 of the second dummy capacitor DC2, and a dummy sixth capacitor electrode DCe6 of the third dummy capacitor DC3.
Referring to FIG. 22A and FIG. 22F, in some embodiments, the second signal line layer includes a second power supply signal line VGHL configured to provide a second power supply signal, a first clock signal line CKL configured to provide a first clock signal, a second clock signal line CBL configured to provide a second clock signal, a control signal line CXL configured to provide a control signal to the gate electrode of the thirteenth transistor T13, and a start signal line STVL configured to provide a start signal.
Referring to FIG. 22A and FIG. 22G, in some embodiments, the third signal line layer includes a plurality of first power supply connecting lines VGLCL configured to connect at least two of the plurality of first power supply lines.
Referring to FIG. 22A to FIG. 22G, a respective scan unit of the scan circuit in some embodiments includes a first pad PAD1 and a second pad PAD2. Optionally, the first pad PAD1 and the second pad PAD2 are in the first conductive layer. In some embodiments, the first pad PAD1 includes the gate electrode G7 of the seventh transistor T7. In some embodiments, the second pad PAD2 includes the gate electrode G1 of the first transistor T1 and the gate electrode of the third transistor. Optionally, the first pad PAD1 is a unitary structure. Optionally, the second pad PAD2 is a unitary structure.
In some embodiments, a respective dummy scan unit of the scan circuit includes a first dummy pad DPAD1. Optionally, the first dummy pad DPAD1 is in the first conductive layer. In some embodiments, the first dummy pad DPAD1 includes the dummy gate electrode DG7 of the seventh dummy transistor DT7.
In some embodiments, the second scan unit SU2 includes a second extension E2 connected to the first pad PAD1 in the second scan unit SU2, connected to the first electrode S4 of the fourth transistor T4 in the second scan unit SU2, and connected to the first electrode S6 of the sixth transistor T6 in the second scan unit SU2. The second extension E2 in the second scan unit SU2 is electrically connected to the gate electrode G7 of the seventh transistor T7 in the second scan unit SU2. Optionally, the second extension E2 in the second scan unit SU2 is connected to the first clock signal line CKL. Optionally, the second extension E2 is in the second conductive layer.
In some embodiments, the first dummy scan unit DSU1 includes a first dummy extension DE1 connected to the first dummy pad DPAD1 in the first dummy scan unit DSU1. Optionally, the first dummy extension DE1 is connected to the second clock signal line CBL. Optionally, the first dummy extension DE1 is in the second conductive layer.
In some embodiments, the first dummy extension DE1 in the first dummy scan unit DSU1 is connected to the second pad PAD2 in the second scan unit SU2. The first dummy extension DE1 in the first dummy scan unit DSU1 is electrically connected to the gate electrode G1 of the first transistor T1 and the gate electrode G3 of the third transistor T3 in the second scan unit SU2. In some embodiments, the first dummy extension DE1 in the first dummy scan unit DSU1 is further connected to the first electrode S2 of the second transistor T2 in the second scan unit SU2. Because the first dummy extension DE1 in the first dummy scan unit DSU1 is connected to the second clock signal line CBL, the first dummy extension DE1 in the first dummy scan unit DSU1 is configured to transmit the second clock signal to the first electrode S2 of the second transistor T2 in the second scan unit SU2, and to the gate electrode G1 of the first transistor T1 and the gate electrode G3 of the third transistor T3 in the second scan unit SU2.
In some embodiments, the first dummy extension DE1 in the first dummy scan unit DSU1 is disconnected from the dummy second electrode DD9 of the ninth dummy transistor DT9 in the first dummy scan unit DSU1. In one example, the dummy first electrode DS9 and the dummy second electrode DD9 of the ninth dummy transistor DT9 in the first dummy scan unit DSU1 are parts of a unitary structure.
In some embodiments, the first scan unit SU1 includes a first extension E1 connected to the first pad PAD1 in the first scan unit SU1, connected to the first electrode S4 of the fourth transistor T4 in the first scan unit SU1, and connected to the first electrode S6 of the sixth transistor T6 in the first scan unit SU1. The first extension E1 in the first scan unit SU1 is electrically connected to the gate electrode G7 of the seventh transistor T7 in the first scan unit SU1. Optionally, the first extension E1 in the first scan unit SU1 is connected to the second clock signal line CBL. Optionally, the first extension E1 is in the second conductive layer.
In some embodiments, the first extension E1 in the first scan unit SU1 is electrically isolated from any dummy scan units, e.g., the first extension E1 in the first scan unit SU1 is not connected to any component of dummy transistors or dummy capacitors in any dummy scan units.
In some embodiments, the first extension E1 in the first scan unit SU1 is not connected to the second scan unit SU2, e.g., the first extension E1 in the first scan unit SU1 is not connected to any component of transistors or capacitors in the second scan unit SU2.
In some embodiments, the second dummy scan unit DSU2 includes a second dummy extension DE2 connected to the first dummy pad DPAD1 in the second dummy scan unit DSU2. Optionally, the second dummy scan unit DSU2 is electrically isolated from the first clock signal line CKL and electrically isolated from the second clock signal line CBL. Optionally, the second dummy extension DE2 is in the second conductive layer.
In some embodiments, the second dummy extension DE2 in the second dummy scan unit DSU2 is not connected to any component in the first dummy scan unit DSU1, e.g., the second dummy extension DE2 in the second dummy scan unit DSU2 is not connected to any component of the dummy transistors or dummy capacitors in the first dummy scan unit DSU1.
In some embodiments, the second dummy extension DE2 in the second dummy scan unit DSU2 is not connected to the second scan unit SU2, e.g., the second dummy extension DE2 in the second dummy scan unit DSU2 is not connected to any component of transistors or capacitors in the second scan unit SU2.
In some embodiments, the second dummy extension DE2 in the second dummy scan unit DSU2 is connected to the dummy second electrode DD9 of the ninth dummy transistor DT9 in the second dummy scan unit DSU2. In one example, the dummy first electrode DS9 and the dummy second electrode DD9 of the ninth dummy transistor DT9 in the second dummy scan unit DSU2 are parts of a unitary structure. In some embodiments, the dummy first electrode DS9 and the dummy second electrode DD9 of the ninth dummy transistor DT9 in the second dummy scan unit DSU2 are connected to the second power supply signal line VGHL configured to provide a second power supply signal. In some embodiments, the first dummy pad DPAD1, the second dummy extension DE2, the dummy first electrode DS9 and the dummy second electrode DD9 of the ninth dummy transistor DT9, in the second dummy scan unit DSU2, are configured to be provided with a second power supply signal.
The inventors of the present disclosure discover that, in the scan circuit depicted in FIG. 22A to FIG. 22H, the disparity between the loading on the first clock signal line CKL and the loading on the second clock signal line CBL can be significantly reduced, due to the absence of a connecting line extending through an area having the one or more dummy scan units. The display panel connected to the scan circuit depicted in FIG. 22A to FIG. 22H has significantly improved display uniformity.
FIG. 23A is a diagram illustrating the structure of multiple scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scan circuit in some embodiments according to the present disclosure. FIG. 23B is a diagram illustrating the structure of a semiconductor material layer in the scan circuit depicted in FIG. 23A. FIG. 23C is a diagram illustrating the structure of a first conductive layer in the scan circuit depicted in FIG. 23A. FIG. 23D is a diagram illustrating the structure of a second conductive layer in the scan circuit depicted in FIG. 23A. FIG. 23E is a diagram illustrating the structure of a first signal line layer in the scan circuit depicted in FIG. 23A. FIG. 23F is a diagram illustrating the structure of a second signal line layer in the scan circuit depicted in FIG. 23A. FIG. 23G is a diagram illustrating the structure of a third signal line layer in the scan circuit depicted in FIG. 23A. FIG. 23H is a diagram illustrating the connectivity of a first clock signal line in the scan circuit depicted FIG. 23A.
The scan units of the scan circuit depicted in FIG. 23A to FIG. 23G correspond to the scan units of the scan circuit depicted in FIG. 19A to FIG. 19G. The second scan unit SU2 in the scan circuit depicted in FIG. 23A to FIG. 23G corresponds to the scan unit in the (2k) -th row in the scan circuit depicted in FIG. 19A to FIG. 19G. The first scan unit SU1 in the scan circuit depicted in FIG. 23A to FIG. 23G corresponds to the scan unit in the (2k-1) -th row in the scan circuit depicted in FIG. 19A to FIG. 19G. The first dummy scan unit DSU1 and the second dummy scan unit DSU2 depicted in FIG. 23A to FIG. 23G correspond to the one or more dummy scan units DSU depicted in FIG. 19A to FIG. 19G.
Referring to FIG. 23A to FIG. 23G, in some embodiments, the scan circuit includes a first scan unit SU1, a first dummy scan unit DSU1, and a second scan unit SU2. Optionally, the first scan unit SU1, the first dummy scan unit DSU1, and the second scan unit SU2 are sequentially arranged. Optionally, the first dummy scan unit DSU1 spaces apart the first scan unit SU1 and the second scan unit SU2.
In some embodiments, the scan circuit further includes a second dummy scan unit DSU2. Optionally, the first scan unit SU1, the second dummy scan unit DSU2, the first dummy scan unit DSU1, and the second scan unit SU2 are sequentially arranged. Optionally, the first dummy scan unit DSU1 spaces apart the second scan unit SU2 and the second dummy scan unit DSU2; and the second dummy scan unit DSU2 spaces apart the first dummy scan unit DSU1 and the first scan unit SU1.
Referring to FIG. 23A to FIG. 23G, a respective scan unit of the scan circuit in some embodiments includes a first pad PAD1. Optionally, the first pad PAD1 is in the first conductive layer. In some embodiments, the first pad PAD1 includes the gate electrode G7 of the seventh transistor T7. Optionally, the first pad PAD1 is a unitary structure.
In some embodiments, the scan circuit includes a second extension E2 connected to the first pad PAD1 in the second scan unit SU2. The second extension E2 in the second scan unit SU2 is electrically connected to the gate electrode G7 of the seventh transistor T7 in the second scan unit SU2. Optionally, the second extension E2 is in the first conductive layer. Optionally, the second extension E2 and the first pad PAD1 are parts of a unitary structure.
In some embodiments, the second extension E2 is connected to the first clock signal line CKL, e.g., at a position in an area having the first dummy scan unit DSU1. In some embodiments, the second extension E2 in the second scan unit SU2 is connected to the first clock signal line CKL at a position in an area having the first dummy scan unit DSU1.
In some embodiments, the second extension E2 is not connected to any component in the first dummy scan unit DSU1, e.g., the second extension E2 is not connected to any component of the dummy transistors or dummy capacitors in the first dummy scan unit DSU1.
In some embodiments, the second extension E2 is not connected to the first scan unit SU1, e.g., the second extension E2 is not connected to any component of the transistors or capacitors in the first scan unit SU1.
In some embodiments, the scan circuit includes a dummy first extension DE1 connected to one or more signal lines in the second dummy scan unit DSU2, which are in turn connected to a second power supply line (e.g., VGHL2) .
The inventors of the present disclosure discover that, in the scan circuit depicted in FIG. 23A to FIG. 23H, the disparity between the loading on the first clock signal line CKL and the loading on the second clock signal line CBL can be significantly reduced, due to the absence of a connecting line extending through an area having the one or more dummy scan units. The display panel connected to the scan circuit depicted in FIG. 23A to FIG. 23H has significantly improved display uniformity.
In some embodiments, referring to FIG. 21A to FIG. 21G, FIG. 22A to FIG. 22H, and FIG. 23A to FIG. 23H, an orthographic projection of the first dummy extension DE1 on a base substrate at least partially overlaps with at least one of an orthographic projection of the first clock signal line CKL on the base substrate or an orthographic projection of the second clock signal line CBL on the base substrate.
In another aspect, the present invention provides a display apparatus, including the scan circuit described herein or fabricated by a method described herein, and a display panel having a plurality of light emitting elements. Examples of appropriate display apparatuses include, but are not limited to, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital album, a GPS, etc. Optionally, the display apparatus is an organic light emitting diode display apparatus. Optionally, the display apparatus is a micro light emitting diode display apparatus. Optionally, the display apparatus is a mini light emitting diode display apparatus. Optionally, the display apparatus is a quantum dots display apparatus.
The foregoing description of the embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. Therefore, the term “the invention” , “the present invention” or the like does not necessarily limit the claim scope to a specific embodiment, and the reference to exemplary embodiments of the invention does not imply a limitation on the invention, and no such limitation is to be inferred. The invention is limited only by the spirit and scope of the appended claims. Moreover, these claims may refer to use “first” , “second” , etc. following with noun or element. Such terms should be understood as a nomenclature and should not be construed as giving the limitation on the number of the elements modified by such nomenclature unless specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.

Claims

A scan circuit, comprising:

a first clock signal line;

a second clock signal line; and

in a region comprising multiple scan units and one or more dummy scan units, a first scan unit, a first dummy scan unit, and a second scan unit sequentially arranged;

wherein a respective scan unit comprises a first pad and a second pad;

the first pad comprises a gate electrode of a seventh transistor;

the second pad comprises a gate electrode of a first transistor and a gate electrode of a third transistor;

the first dummy scan unit comprises a first dummy extension;

the first dummy extension is connected to the second pad in the second scan unit, and configured to transmit one of a first clock signal or a second clock signal to the gate electrode of the first transistor and the gate electrode of the third transistor in the second scan unit; and

an orthographic projection of the first dummy extension on a base substrate at least partially overlaps with at least one of an orthographic projection of the first clock signal line on the base substrate or an orthographic projection of the second clock signal line on the base substrate.
The scan circuit of claim 1, wherein the first dummy extension is connected to one of the first clock signal line or the second clock signal line at a position in an area having the first dummy scan unit.
The scan circuit of claim 2, wherein the first dummy extension in the first dummy scan unit is further connected to a first electrode of a second transistor in the second scan unit, and configured to transmit the one of the first clock signal or the second clock signal to the first electrode of the second transistor in the second scan unit.
The scan circuit of claim 1, wherein the second scan unit comprises a second extension connected to the first pad in the second scan unit;

wherein the first pad in the second scan unit comprises the gate electrode of the seventh transistor in the second scan unit; and

the second extension in the second scan unit is connected to another of the first clock signal line or the second clock signal line, and configured to transmit another of the first clock signal or the second clock signal to the gate electrode of the seventh transistor in the second scan unit.
The scan circuit of claim 4, wherein the first pad in the second scan unit is connected to a first electrode of a fifth transistor in the second scan unit; and

the second extension in the second scan unit is configured to transmit the another of the first clock signal or the second clock signal to the first electrode of the fifth transistor in the second scan unit through the first pad in the second scan unit.
The scan circuit of claim 4, wherein the second extension in the second scan unit is connected to a first electrode of a fourth transistor and a first electrode of a sixth transistor in the second scan unit, and configured to transmit the another of the first clock signal or the second clock signal to the first electrode of the fourth transistor and the first electrode of the sixth transistor in the second scan unit.
The scan circuit of claim 1, wherein the first scan unit comprises a first extension connected to the first pad in the first scan unit;

wherein the first pad in the first scan unit comprises the gate electrode of the seventh transistor in the first scan unit;

the first pad in the first scan unit is connected to a first electrode of a fifth transistor in the first scan unit; and

the first extension in the first scan unit is connected to the one of the first clock signal line or the second clock signal line, and configured to transmit the one of the first clock signal or the second clock signal to the gate electrode of the seventh transistor and the first electrode of the fifth transistor in the first scan unit.
The scan circuit of claim 7, wherein the first pad in the first scan unit is connected to the first electrode of the fifth transistor in the first scan unit; and

the first extension in the first scan unit is configured to transmit the one of the first clock signal or the second clock signal to the first electrode of the fifth transistor in the first scan unit through the first pad in the first scan unit.
The scan circuit of claim 7, wherein the first extension in the first scan unit is connected to a first electrode of a fourth transistor and a first electrode of a sixth transistor in the first scan unit, and configured to transmit another of the first clock signal or the second clock signal to the first electrode of the fourth transistor and the first electrode of the sixth transistor in the first scan unit.
The scan circuit of claim 1, wherein the first dummy scan unit further comprises a first dummy pad;

the first dummy pad in the first dummy scan unit comprises a dummy gate electrode of a seventh dummy transistor; and

the first dummy extension is connected to the first dummy pad.
The scan circuit of claim 10, wherein the first dummy pad in the first dummy scan unit is disconnected from a dummy first electrode of a fifth dummy transistor in the first dummy scan unit;

the dummy first electrode and a dummy second electrode of the fifth dummy transistor, and a dummy first electrode and a dummy second electrode of a fourth dummy transistor, in the first dummy scan unit, are parts of a unitary structure; and

the unitary structure is configured to be provided with a second power supply signal.
The scan circuit of claim 1, wherein the first dummy extension in the first dummy scan unit is disconnected from a dummy second electrode of a ninth dummy transistor in the first dummy scan unit;

a dummy first electrode and the dummy second electrode of the ninth dummy transistor in the first dummy scan unit are parts of a unitary structure; and

the unitary structure is configured to be provided with a second power supply signal.
The scan circuit of claim 7, wherein the first extension in the first scan unit is not connected to any component of dummy transistors or dummy capacitors in any dummy scan units; and

the first extension in the first scan unit is not connected to any component of transistors or capacitors in the second scan unit.
The scan circuit of claim 1, in the region comprising multiple scan units and one or more dummy scan units, further comprising a second dummy scan unit;

wherein the first scan unit, the second dummy scan unit, the first dummy scan unit, and the second scan unit are sequentially arranged.
The scan circuit of claim 14, wherein the second dummy scan unit is electrically isolated from the first clock signal line and electrically isolated from the second clock signal line.
The scan circuit of claim 14, wherein the second dummy scan unit comprises a second dummy extension in the second dummy scan unit; and

the second dummy extension in the second dummy scan unit is electrically isolated from the first clock signal line and electrically isolated from the second clock signal line.
The scan circuit of claim 16, wherein the second dummy scan unit further comprises a first dummy pad connected to the second dummy extension in the second dummy scan unit; and

the first dummy pad and the second dummy extension in the second dummy scan unit is electrically isolated from the first clock signal line and electrically isolated from the second clock signal line.
The scan circuit of claim 16, wherein the second dummy extension in the second dummy scan unit is not connected to any component of dummy transistors or dummy capacitors in the first dummy scan unit; and

the second dummy extension in the second dummy scan unit is not connected to any components of transistors or capacitors in the first scan unit or the second scan unit.
The scan circuit of claim 17, wherein the first dummy pad in the second dummy scan unit is connected to a dummy first electrode of a fifth dummy transistor in the second dummy scan unit;

the dummy first electrode and a dummy second electrode of the fifth dummy transistor, and a dummy first electrode and a dummy second electrode of a fourth dummy transistor, in the second dummy scan unit, are parts of a unitary structure; and

the unitary structure is configured to be provided with a second power supply signal.
A scan circuit, comprising:

a first clock signal line;

a second clock signal line; and

in a region comprising multiple scan units and one or more dummy scan units, a first scan unit, a first dummy scan unit, and a second scan unit sequentially arranged;

wherein a respective scan unit comprises a first pad;

the first pad comprises a gate electrode of a seventh transistor;

the scan circuit further comprises a second extension;

the second extension is connected to one of the first clock signal line or the second clock signal line at a position in an area having the first dummy scan unit; and

the second extension is connected to the first pad in a second scan circuit, and configured to transmit one of a first clock signal or a second clock signal to the gate electrode of the seventh transistor.
A display apparatus, comprising the scan circuit of any one of claims 1 to 20, and a display panel connected to the scan circuit.