CN113450692A - Grid driving circuit, driving method thereof and display device - Google Patents
Grid driving circuit, driving method thereof and display device Download PDFInfo
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention provides a grid driving circuit, a driving method thereof and a display device.A first-stage shift register is directly connected with a forward scanning trigger signal, so that the forward scanning trigger signal directly acts on the first-stage shift register without passing through a first virtual shift register, and the problem of driving delay of the grid driving circuit during forward scanning is reduced; and the Nth-stage shift register is directly contacted with the reverse scanning trigger signal, so that the reverse scanning trigger signal is directly acted on the Nth-stage shift register without passing through the second virtual shift register, and the problem of drive delay of a gate drive circuit during reverse scanning is solved. Therefore, according to the technical scheme provided by the invention, on the basis of ensuring that the gate drive circuit can realize bidirectional scanning, the drive delay of the gate drive circuit is reduced, and the performance of the display device is improved.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a gate driving circuit, a driving method thereof, and a display device.
Background
The frame region of the conventional display device includes a gate driving circuit for providing gate driving signals to the pixel units in the display region to scan the pixel units in the display region, thereby achieving the purpose of image display. However, the conventional gate driving circuit has a large driving delay, which degrades the performance of the display device.
Disclosure of Invention
In view of this, the present invention provides a gate driving circuit, a driving method thereof and a display device, which effectively solve the technical problems in the prior art, reduce the driving delay of the gate driving circuit and improve the performance of the display device on the basis of ensuring that the gate driving circuit can realize bidirectional scanning.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a gate drive circuit comprising: the shift register comprises a first virtual shift register, a second virtual shift register, a first-stage shift register to an Nth-stage shift register, wherein N is a positive integer greater than 2;
the output end of the first virtual shift register is electrically connected with the reverse closing input end of the first-stage shift register, the reverse scanning input end of the first virtual shift register is electrically connected with the output end of the first-stage shift register, and the forward scanning input end of the first-stage shift register is connected with a forward scanning trigger signal;
the output end of the ith stage shift register is electrically connected with the forward scanning input end of the (i +1) th stage shift register, the output end of the (i +1) th stage shift register is electrically connected with the reverse scanning input end of the ith stage shift register, and i is an integer which is greater than or equal to 1 and less than N;
the output end of the second virtual shift register is electrically connected with the forward closing input end of the Nth-stage shift register, the forward scanning input end of the second virtual shift register is electrically connected with the output end of the Nth-stage shift register, and the reverse scanning input end of the Nth-stage shift register is connected with a reverse scanning trigger signal.
Correspondingly, the invention also provides a driving method of the gate driving circuit, which is applied to the gate driving circuit and comprises the following steps:
during forward scanning, controlling a forward scanning trigger signal to trigger a first-stage shift register to enable the first-stage shift register to an Nth-stage shift register to sequentially output scanning signals, and after the Nth-stage shift register outputs the scanning signals, responding to the scanning signals output by the Nth-stage shift register by a second virtual shift register, outputting a turn-off signal to a forward turn-off input end of the Nth-stage shift register, wherein the first virtual shift register keeps outputting an invalid level signal;
and after the first-stage shift register outputs the scanning signal, the first virtual shift register responds to the scanning signal output by the first-stage shift register and outputs a turn-off signal to the reverse turn-off input end of the first-stage shift register, wherein the second virtual shift register keeps outputting an invalid level signal.
Correspondingly, the invention also provides a display device which comprises the grid drive circuit.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention provides a grid driving circuit, a driving method thereof and a display device, comprising the following steps: the shift register comprises a first virtual shift register, a second virtual shift register, a first-stage shift register to an Nth-stage shift register, wherein N is a positive integer greater than 2; the output end of the first virtual shift register is electrically connected with the reverse closing input end of the first-stage shift register, the reverse scanning input end of the first virtual shift register is electrically connected with the output end of the first-stage shift register, and the forward scanning input end of the first-stage shift register is connected with a forward scanning trigger signal; the output end of the ith stage shift register is electrically connected with the forward scanning input end of the (i +1) th stage shift register, the output end of the (i +1) th stage shift register is electrically connected with the reverse scanning input end of the ith stage shift register, and i is an integer which is greater than or equal to 1 and less than N; the output end of the second virtual shift register is electrically connected with the forward closing input end of the Nth-stage shift register, the forward scanning input end of the second virtual shift register is electrically connected with the output end of the Nth-stage shift register, and the reverse scanning input end of the Nth-stage shift register is connected with a reverse scanning trigger signal.
As can be seen from the above, in the technical solution provided by the present invention, the nth shift register can be turned off when the gate driving circuit scans in the forward direction through the second virtual shift register, and the first shift register can be turned off when the gate driving circuit scans in the reverse direction through the first virtual shift register, so as to ensure that the display device can realize the function of scanning in both the forward and reverse directions.
In addition, the first-stage shift register is directly connected with the forward scanning trigger signal, so that the forward scanning trigger signal directly acts on the first-stage shift register without passing through the first virtual shift register, and the problem of drive delay of a grid drive circuit during forward scanning is solved; and the Nth-stage shift register is directly contacted with the reverse scanning trigger signal, so that the reverse scanning trigger signal is directly acted on the Nth-stage shift register without passing through the second virtual shift register, and the problem of drive delay of a gate drive circuit during reverse scanning is solved. Therefore, according to the technical scheme provided by the invention, on the basis of ensuring that the gate drive circuit can realize bidirectional scanning, the drive delay of the gate drive circuit is reduced, and the performance of the display device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another gate driving circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another shift register according to an embodiment of the present invention;
FIG. 5 is a timing diagram according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a first virtual shift register according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of a first dummy shift register according to an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of a first dummy shift register according to another embodiment of the present invention;
FIG. 9 is a schematic structural diagram of a first dummy shift register according to another embodiment of the present invention;
FIG. 10 is a schematic structural diagram of a first dummy shift register according to another embodiment of the present invention;
FIG. 11 is a schematic structural diagram of a first dummy shift register according to another embodiment of the present invention;
FIG. 12 is a diagram illustrating a second virtual shift register according to an embodiment of the present invention;
FIG. 13 is a diagram illustrating a second virtual shift register according to an embodiment of the present invention;
FIG. 14 is a schematic structural diagram of a second dummy shift register according to an embodiment of the present invention;
FIG. 15 is a schematic structural diagram of a second dummy shift register according to an embodiment of the present invention;
FIG. 16 is a diagram illustrating a structure of a second dummy shift register according to another embodiment of the present invention;
FIG. 17 is a schematic structural diagram of a second dummy shift register according to an embodiment of the present invention;
fig. 18 is a schematic structural diagram of a first stage shift register according to an embodiment of the present invention;
FIG. 19 is a diagram illustrating a structure of a shift register of a first stage according to an embodiment of the present invention;
fig. 20 is a schematic structural diagram of an nth stage shift register according to an embodiment of the present invention;
fig. 21 is a schematic structural diagram of another nth stage shift register according to an embodiment of the present invention;
fig. 22 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, the frame region of the conventional display device includes a gate driving circuit for providing gate driving signals to the pixel units in the display region to scan the pixel units in the display region, so as to achieve the purpose of displaying images. However, the conventional gate driving circuit has a large driving delay, which degrades the performance of the display device.
Based on this, embodiments of the present invention provide a gate driving circuit, a driving method thereof, and a display device, which effectively solve the technical problems in the prior art, reduce the driving delay of the gate driving circuit on the basis of ensuring that the gate driving circuit can implement bidirectional scanning, and improve the performance of the display device.
To achieve the above object, the technical solutions provided by the embodiments of the present invention are described in detail below, specifically with reference to fig. 1 to 22.
Referring to fig. 1, a schematic diagram of a gate driving circuit according to an embodiment of the present invention is shown, in which an output terminal of each shift register is marked by OUT, a forward scan input terminal of each shift register is marked by SET, a reverse scan input terminal of each shift register is marked by END, a reverse turn-off input terminal of each shift register is marked by DSET, and a forward turn-off input terminal of each shift register is marked by DEND. The gate driving circuit provided by the embodiment of the invention comprises: the first dummy shift register DSR11, the second dummy shift register DSR12, and the first to nth stage shift registers SR11 to SR1N, N being a positive integer greater than 2.
The output end of the first virtual shift register DSR11 is electrically connected with the reverse closing input end of the first stage shift register SR11, the reverse scanning input end of the first virtual shift register DSR11 is electrically connected with the output end of the first stage shift register SR11, and the forward scanning input end of the first stage shift register SR11 is connected with a forward scanning trigger signal STV 11.
An output terminal of the i-th stage shift register SR1i is electrically connected to a forward scan input terminal of the i + 1-th stage shift register SR1(i +1), an output terminal of the i + 1-th stage shift register SR1(i +1) is electrically connected to a reverse scan input terminal of the i-th stage shift register SR1i, and i is an integer greater than or equal to 1 and less than N.
An output end of the second virtual shift register DSR12 is electrically connected with a forward closing input end of the N-th stage shift register SR1N, a forward scanning input end of the second virtual shift register DSR12 is electrically connected with an output end of the N-th stage shift register SR1N, and a reverse scanning input end of the N-th stage shift register SR1N is connected with a reverse scanning trigger signal STV 12.
Correspondingly, an embodiment of the present invention provides a driving method for a gate driving circuit, including:
and after the Nth-stage shift register outputs the scanning signal, the second virtual shift register responds to the scanning signal output by the Nth-stage shift register and outputs a turn-off signal to a forward turn-off input end of the Nth-stage shift register, wherein the first virtual shift register keeps outputting an invalid level signal.
And after the first-stage shift register outputs the scanning signal, the first virtual shift register responds to the scanning signal output by the first-stage shift register and outputs a turn-off signal to the reverse turn-off input end of the first-stage shift register, wherein the second virtual shift register keeps outputting an invalid level signal.
It can be understood that in the technical solution provided in the embodiment of the present invention, the nth shift register can be turned off by the second virtual shift register when the gate driving circuit scans in the forward direction, and the first shift register can be turned off by the first virtual shift register when the gate driving circuit scans in the reverse direction, so as to ensure that the display device can realize the function of scanning in both the forward and reverse directions.
In addition, the first-stage shift register provided by the embodiment of the invention is directly connected to the forward scanning trigger signal, so that the forward scanning trigger signal directly acts on the first-stage shift register without passing through the first virtual shift register, and the problem of drive delay of the gate drive circuit during forward scanning is solved; and the Nth-stage shift register is directly contacted with the reverse scanning trigger signal, so that the reverse scanning trigger signal is directly acted on the Nth-stage shift register without passing through the second virtual shift register, and the problem of drive delay of a gate drive circuit during reverse scanning is solved. Therefore, according to the technical scheme provided by the embodiment of the invention, on the basis of ensuring that the gate driving circuit can realize bidirectional scanning, the driving delay of the gate driving circuit is reduced, and the performance of the display device is improved.
In an embodiment of the present invention, the gate driving circuit provided by the present invention may further include more dummy shift registers and more shift registers, wherein the gate driving circuit shown in fig. 1 is only a basic unit in the gate driving circuit; that is, the gate driving circuit may include a plurality of gate driving circuits shown in fig. 1 and be defined as a first gate driving circuit to an mth gate driving circuit, M being an integer greater than or equal to 2. When the gate driving circuit is set to scan in the forward direction, forward scanning starting signals from the first gate driving circuit to the Mth gate driving circuit are sequentially output, so that after scanning signals are sequentially output from the first gate driving circuit to the ith stage of shift register in the Mth gate driving circuit, the scanning signals are sequentially output from the first gate driving circuit to the (i +1) th stage of shift register in the Mth gate driving circuit. Similarly, when the gate driving circuit is set to scan in the reverse direction, the reverse scanning start signals from the mth gate driving circuit to the first gate driving circuit are sequentially output, so that after the scanning signals are sequentially output from the mth gate driving circuit to the (i +1) th stage shift register in the first gate driving circuit, the scanning signals are sequentially output from the mth gate driving circuit to the ith stage shift register in the first gate driving circuit, and the positive and negative scanning process of the set gate driving circuit is completed.
Specifically, as shown in fig. 2, a schematic structural diagram of another gate driving circuit provided for an embodiment of the present invention is provided, where fig. 2 illustrates an example including a first gate driving circuit and a second gate driving circuit, where the first gate driving circuit includes a first dummy shift register DSR11, a second dummy shift register DSR12, and first to nth shift registers SR11 to SR 1N; and the second gate driving circuit includes a first dummy shift register DSR21, a second dummy shift register DSR22, and first to nth stage shift registers SR21 to SR 2N. The connection relations between the virtual shift register and the shift register and between the ith-stage shift register and the (i +1) th-stage shift register in the first gate driving circuit and the second gate driving circuit are the same as those in fig. 1. During forward scanning, a forward scanning trigger signal STV11 of the first gate driving circuit and a forward scanning trigger signal STV21 of the second gate driving circuit are sequentially output, so that after scanning signals are sequentially output from the ith stage of shift register in the first gate driving circuit to the second gate driving circuit, scanning signals are sequentially output from the first gate driving circuit to the (i +1) th stage of shift register in the second gate driving circuit. And in the reverse scanning process, a reverse scanning trigger signal STV12 of the second gate driving circuit and a reverse scanning trigger signal STV22 of the first gate driving circuit are sequentially output, so that after scanning signals are sequentially output from the second gate driving circuit to the (i +1) th stage of shift register in the first gate driving circuit, the scanning signals are sequentially output from the second gate driving circuit to the ith stage of shift register in the first gate driving circuit.
Alternatively, in the gate driving circuit shown in fig. 2 of the present invention, the first stage shift register SR11 to the nth stage shift register SR1N of the first gate driving circuit and the first stage shift register SR21 to the nth stage shift register SR2N of the second gate driving circuit may be alternately arranged. Similarly, the first dummy shift register DSR11 and the second dummy shift register DSR12 of the first gate driving circuit are respectively arranged in an alternating manner with the first dummy shift register DSR21 and the second dummy shift register DSR22 of the second gate driving circuit, and the present invention is not particularly limited thereto, and needs to be specifically designed according to practical applications.
As shown in fig. 3, a schematic structural diagram of a shift register provided in an embodiment of the present invention is shown, where the first virtual shift register, the second virtual shift register, and the first-stage shift register to the nth-stage shift register provided in the embodiment of the present invention each include: the precharge module 100, the first pull-down module 210, the second pull-down module 220, and the output module 300.
The output terminal of the precharge module 100 is electrically connected to the first node P.
The first pull-down module 210 is electrically connected to the first node P, and the first pull-down module 210 controls an on state between the reference level terminal VG and the second node Q in response to a signal of the first node P.
The second pull-down module 220 is electrically connected to the second node Q, and the second pull-down module 220 controls the Q signal of the second node in response to the first clock signal CKB and controls the on-state between the reference level terminal VG and the first node P and between the reference level terminal VG and the output terminal GOUT of the shift register in response to the signal of the second node Q.
The output module 300 is electrically connected to the first node P, the output module 300 controls a turn-on state between the first clock signal CKB and the output terminal GOUT of the shift register in response to a signal of the first node P, and the output module 300 controls a turn-on state between the reference level terminal VG and the output terminal GOUT of the shift register in response to the second clock signal CK.
In an embodiment of the present invention, the precharge module, the first pull-down module, the second pull-down module, and the output module provided in the embodiment of the present invention may be formed by transistors, where the transistors may be all N-type transistors or all P-type transistors, and the present invention is not limited in particular. The technical solution provided by the present invention is described in more detail by specific circuit structures, and all transistors are illustrated as N-type transistors.
Fig. 4 is a schematic structural diagram of another shift register according to an embodiment of the present invention, where fig. 4 shows a circuit composition structure of the second to N-1 shift registers, a precharge module of the shift register in any one of the second to N-1 shift registers includes a ninth transistor T9 and a tenth transistor T10, a gate of the ninth transistor T9 is a forward scan input SET of the shift register and is electrically connected to an output terminal of the shift register of the previous stage, a first terminal of the ninth transistor T9 is connected to a first voltage terminal DIR1, and a second terminal of the ninth transistor T9 is electrically connected to a first node P. A gate of the tenth transistor T10 is an inverted scan input END of the shift register and is electrically connected to an output END of the next stage of the shift register, a first terminal of the tenth transistor is electrically connected to the second voltage terminal DIR2, and a second terminal of the tenth transistor T10 is electrically connected to the first node P.
As shown in fig. 4, the first pull-down module of the shift register includes an eleventh transistor T11, a gate of the eleventh transistor T11 is electrically connected to the first node P, a first terminal of the eleventh transistor T11 is electrically connected to the second node Q, and a second terminal of the eleventh transistor T11 is electrically connected to the reference level terminal VG.
As shown in fig. 4, the second pull-down module of the shift register includes a twelfth transistor T12, a thirteenth transistor T13 and a first capacitor C1, a first plate of the first capacitor C1 is connected to the first clock signal CKB, a second plate of the first capacitor C1 is electrically connected to the second node Q, a gate of the twelfth transistor T12 is electrically connected to the second node Q, a first end of the twelfth transistor T12 is electrically connected to the first node P, a second end of the twelfth transistor T12 is electrically connected to the reference level terminal VG, a gate of the thirteenth transistor T13 is electrically connected to the second node Q, a first end ut of the thirteenth transistor T13 is electrically connected to the output terminal goi of the shift register, and a second end of the thirteenth transistor T13 is electrically connected to the reference level terminal VG.
As shown in fig. 4, the output module of the shift register includes a fourteenth transistor T14, a fifteenth transistor T15 and a second capacitor C2, a first plate of the second capacitor C2 is electrically connected to the first node P, a second plate of the second capacitor C2 is electrically connected to the output terminal GOUT of the shift register, a gate of the fourteenth transistor T14 is electrically connected to the first node P, a first end of the fourteenth transistor T14 is connected to the first clock signal CKB, a second end of the fourteenth transistor T14 is electrically connected to the output terminal GOUT of the shift register, a gate of the fifteenth transistor T15 is connected to the second clock signal CK, a first end ut of the fifteenth transistor T15 is electrically connected to the output terminal GOUT of the shift register, and a second end of the fifteenth transistor T15 is electrically connected to the reference level terminal VG. The first clock signal CKB and the second clock signal CK are out of phase (i.e., the second clock signal CK is falling when the first clock signal CKB is rising, and the second clock signal CK is rising when the first clock signal CKB is falling), and the first voltage terminal DIR1 and the second voltage terminal DIR2 are opposite in level (i.e., the second voltage terminal DIR2 is low when the first voltage terminal DIR1 is high, and the second voltage terminal DIR2 is high when the first voltage terminal DIR1 is low).
Referring to fig. 4 and 5, fig. 5 is a timing diagram of an embodiment of the invention, in which the reference level terminal VG outputs a low level, and the output level of the first voltage terminal DIR1 is opposite to the output level of the second voltage terminal DIR 2; when the gate driving circuit is in the positive scan state, the first voltage terminal DIR1 outputs high level, and the second voltage terminal DIR2 outputs low level; and when the gate driving circuit is reversely swept, the first voltage terminal DIR1 outputs a low level, and the second voltage terminal DIR2 outputs a high level. The first voltage terminal DIR1 outputting high level and the second voltage terminal DIR2 outputting low level when the gate driving circuit is in normal scan will be described. The operation of the shift register shown in fig. 4 includes three stages, i.e., a first stage t1, a second stage t2, and a third stage t 3:
in the first phase T1, the positive scan input SET is asserted to the high trigger signal to control the ninth transistor T9 to transmit the high level of the first voltage terminal DIR1 to the first node P. The first node P controls the eleventh transistor T11 and the fourteenth transistor T14 to be turned on, so that the second node Q is turned on with the reference level terminal VG, and the output terminal GOUT of the shift register and the first clock signal CKB are turned on; meanwhile, the fifteenth transistor T15 is controlled to be turned on by the second clock signal CK, so that the output terminal GOUT of the shift register is connected to the reference level terminal VG. At this time, the potential of the first node P is at a high level, the potential of the second node Q is at a low level, and the output terminal GOUT of the shift register is at a low level.
In the second stage T2, due to the bootstrap effect of the capacitor C2, the potential of the first node P is higher than that in the first stage T1, the first node P controls the eleventh transistor T11 and the fourteenth transistor T14 to be turned on, so that the second node Q is turned on with the reference level terminal VG, and the output terminal GOUT of the shift register and the first clock signal CKB are turned on; and the fifteenth transistor T15 is turned off in response to the low level of the second clock signal CK. At this time, the voltage level of the first node P is high, the voltage level of the second node Q is low, and the output terminal GOUT of the shift register is high transmitted by the first clock signal CKB.
In the third stage T3, the inverse scan input END is turned on to a high level, and the tenth transistor T10 is controlled to turn on the first node P and the second voltage terminal DIR2, the first node P is a low level transmitted by the second voltage terminal DIR2, and the transistor whose gate is electrically connected to the first node P is turned off. The fifteenth transistor T15 is controlled by the second clock signal CK to be turned on, so that the output terminal GOUT of the shift register is connected to the reference level terminal VG. At this time, the potential of the first node P is at a low level, the potential of the second node Q is at a low level, and the output terminal GOUT of the shift register is at a low level. And after the third stage T3, the potential of the second node Q is high-level-converted with the high level of the first clock signal CKB, and then when the potential of the second node Q is high-level, the twelfth transistor T12 and the thirteenth transistor T13 are controlled to be turned on, so that the first node P and the output terminal GOUT of the shift register are both electrically connected to the reference level terminal VG, and the potentials of the first node P and the output terminal GOUT of the shift register are kept at low levels.
It should be noted that, when the gate driving circuit is in reverse scan, the operation principle of the shift register shown in fig. 4 in the first stage to the third stage is the same as that of the gate driving circuit in normal scan, and the difference is that: in the first stage of reverse scanning, the high level is switched on by the reverse scanning input end, the tenth transistor is controlled to transmit the high level of the second voltage end to the first node, and the ninth transistor is switched off in response to the low level of the forward scanning input end; and in the third stage of reverse scan, the forward scan input end is connected to a high level, the ninth transistor is controlled to transmit the low level of the first voltage end to the first node, and the tenth transistor is turned off in response to the low level of the reverse scan input end, which is not described in detail herein.
Further, the shift register provided in the embodiment of the present invention may further include a reset module, where the reset module is configured to control on states of the reference level terminal and the first node, and the reference level terminal and the output terminal of the shift register in response to a reset signal, and the reset module is configured to reset potentials of the first node and the output terminal of the shift register before the gate driving circuit operates. Specifically, as shown in fig. 4, the reset module of the shift register according to the embodiment of the present invention includes a sixteenth transistor T16 and a seventeenth transistor T17, gates of the sixteenth transistor T16 and the seventeenth transistor T17 are both connected to the reset signal RE, a first end of the sixteenth transistor T16 is electrically connected to the first node P, a second end of the sixteenth transistor T16 is electrically connected to the reference level terminal VG, a first end of the seventeenth transistor T17 is electrically connected to the output terminal GOUT of the shift register, and a second end of the seventeenth transistor T17 is electrically connected to the reference level terminal VG.
As shown in fig. 6, which is a schematic structural diagram of a first dummy shift register according to an embodiment of the present invention, wherein a precharge module of the first dummy shift register includes: a first transistor T1, a gate of the first transistor T1 is connected to the normally-off control signal VGx, a first terminal of the first transistor T1 is connected to the first voltage terminal DIR1, and a second terminal of the first transistor T1 is electrically connected to the first node P; a gate of the second transistor T2 is electrically connected to an output terminal of the first stage shift register (a gate of the second transistor T2 is an inverted scan input terminal END of the first dummy shift register), a first terminal of the second transistor T2 is electrically connected to the second voltage terminal DIR2, and a second terminal of the second transistor T2 is electrically connected to the first node P.
It can be understood that, in the precharge module of the first virtual shift register provided in the embodiment of the present invention, since the gate of the first transistor is connected to the normally-off control signal, the normally-off control signal can control the first transistor to maintain the off state, so that the path between the first voltage terminal and the first node can be maintained in the off state. Since the first voltage terminal cannot transmit a signal to the first node, the first dummy shift register can be kept outputting an invalid level signal while being swept. And when the grid driving circuit performs reverse scanning, the reverse scanning input end of the first virtual shift register is connected with the scanning signal output by the output end of the first-stage shift register, then the second transistor is controlled to connect the second voltage end with the first node, and after the work processing of each composition structure of the first virtual shift register, the switching-off signal is output to the reverse switching-off input end of the first-stage shift register, so that the first-stage shift register is switched off. The preparation processes of the transistors of the virtual shift register and the shift register provided by the embodiment of the invention can be the same, so that the preparation of a circuit is facilitated, the preparation efficiency is improved, and the preparation cost is reduced.
As shown in fig. 7, a schematic structural diagram of another first dummy shift register provided in the embodiment of the present invention is shown, wherein the precharge module of the first dummy shift register includes: a gate of the second transistor T2 is electrically connected to an output terminal of the first stage shift register (a gate of the second transistor T2 is an inverted scan input terminal END of the first dummy shift register), a first terminal of the second transistor T2 is electrically connected to the second voltage terminal DIR2, and a second terminal of the second transistor T2 is electrically connected to the first node P.
It can be understood that, in the precharge module of the first virtual shift register shown in fig. 7 of the present invention, compared to the precharge module of the first virtual shift register shown in fig. 6, the first transistor is removed to reduce the area of the gate driving circuit and increase the wiring space. In this regard, the first dummy shift register can keep outputting an invalid level signal during the forward scan by transmitting no signal from the first voltage terminal to the first node. And when the grid driving circuit performs reverse scanning, the reverse scanning input end of the first virtual shift register is connected with the scanning signal output by the output end of the first-stage shift register, then the second transistor is controlled to connect the second voltage end with the first node, and after the work processing of each composition structure of the first virtual shift register, the switching-off signal is output to the reverse switching-off input end of the first-stage shift register, so that the first-stage shift register is switched off.
In an embodiment of the present invention, on the basis of the first dummy shift register shown in fig. 6 and 7, transistors may be added to maintain an arrangement substantially symmetrical to the number of structural devices of the second to N-1 th shift registers or substantially symmetrical to the self circuit structure. Specifically, as shown in fig. 8, which is a schematic structural diagram of another first virtual shift register according to an embodiment of the present invention, a precharge module of the first virtual shift register shown in fig. 8 is partially the same as the precharge module of the first virtual shift register shown in fig. 6, except that: the precharge module of the first virtual shift register provided in fig. 8 of the present invention further includes: a gate of the first auxiliary transistor T11, a gate of the first auxiliary transistor T11 is electrically connected to the output terminal of the first stage shift register, a first terminal of the first auxiliary transistor T11 is electrically connected to the second voltage terminal DIR2, and a second terminal of the first auxiliary transistor T11 is electrically connected to the first node P.
Or as shown in fig. 9, which is a schematic structural diagram of another first virtual shift register provided in the embodiment of the present invention, a precharge module of the first virtual shift register shown in fig. 9 is partially the same as the precharge module of the first virtual shift register shown in fig. 7, except that: the precharge module of the first dummy shift register provided in fig. 9 of the present invention further includes: a gate of the first auxiliary transistor T11, a gate of the first auxiliary transistor T11 is electrically connected to the output terminal of the first stage shift register, a first terminal of the first auxiliary transistor T11 is electrically connected to the second voltage terminal DIR2, and a second terminal of the first auxiliary transistor T11 is electrically connected to the first node P.
Or as shown in fig. 10, which is a schematic structural diagram of another first virtual shift register provided in the embodiment of the present invention, a precharge module of the first virtual shift register shown in fig. 10 is partially the same as the precharge module of the first virtual shift register shown in fig. 6, except that: the precharge module of the first dummy shift register shown in fig. 10 of the present invention further includes: a first auxiliary transistor T11, a gate of the first auxiliary transistor T11 is electrically connected to the output terminal of the first stage shift register, a first terminal of the first auxiliary transistor T11 is electrically connected to the second voltage terminal DIR2, and a second terminal of the first auxiliary transistor T11 is electrically connected to the first node P; a second auxiliary transistor T12, a gate of the second auxiliary transistor T12 is connected to the normally-off control signal VGx, a first terminal of the second auxiliary transistor T12 is connected to the first voltage terminal DIR1, and a second terminal of the second auxiliary transistor TI2 is electrically connected to the first node P.
Or as shown in fig. 11, which is a schematic structural diagram of another first virtual shift register provided in the embodiment of the present invention, a precharge module of the first virtual shift register shown in fig. 11 is partially the same as the precharge module of the first virtual shift register shown in fig. 6, except that: the precharge module of the first dummy shift register provided in fig. 11 of the present invention further includes: a second auxiliary transistor T12, a gate of the second auxiliary transistor T12 is connected to the normally-off control signal VGx, a first terminal of the second auxiliary transistor T12 is connected to the first voltage terminal DIR1, and a second terminal of the second auxiliary transistor TI2 is electrically connected to the first node P.
As shown in fig. 12, a schematic structural diagram of a second dummy shift register according to an embodiment of the present invention is provided, in which a precharge module of the second dummy shift register includes: a third transistor T3, a gate of the third transistor T3 is electrically connected to the output terminal of the nth stage shift register (the gate of the third transistor T3 is the forward scan input terminal SET of the second virtual shift register), a first end of the third transistor T3 is electrically connected to the first voltage terminal DIR1, and a second end of the third transistor T3 is electrically connected to the first node P; a gate of the fourth transistor T4, the fourth transistor T4 is connected to the normally-off control signal VGx, a first terminal of the fourth transistor T4 is electrically connected to the second voltage terminal DIR2, and a second terminal of the fourth transistor T4 is electrically connected to the first node P.
It can be understood that, in the precharge module of the second virtual shift register provided in the embodiment of the present invention, since the gate of the fourth transistor is connected to the normally-off control signal, the normally-off control signal can control the fourth transistor to maintain the off state, so that the path between the second voltage terminal and the first node can be maintained in the off state. The second virtual shift register can keep outputting an invalid level signal when reversely scanning because the second voltage terminal can not transmit the signal to the first node. And when the grid drive circuit is in positive scanning, the positive scanning input end of the second virtual shift register is connected with the scanning signal output by the output end of the Nth-stage shift register, the third transistor is controlled to connect the first voltage end with the first node, and after the work processing of each composition structure of the second virtual shift register, the turn-off signal is output to the positive turn-off input end of the Nth-stage shift register, so that the Nth-stage shift register is turned off. The virtual shift register and the shift register provided by the embodiment of the invention have the same transistor preparation process, thereby facilitating the preparation of the circuit, improving the preparation efficiency and reducing the preparation cost, and the invention is not particularly limited
As shown in fig. 13, a schematic structural diagram of another second dummy shift register provided in the embodiment of the present invention is shown, wherein the precharge module of the second dummy shift register includes: a third transistor T3, wherein a gate of the third transistor T3 is electrically connected to the output terminal of the nth stage shift register, a first terminal of the third transistor T3 is electrically connected to the first voltage terminal DIR1, and a second terminal of the third transistor T3 is electrically connected to the first node P.
It can be understood that, in the precharge module of the second virtual shift register shown in fig. 13, compared to the precharge module of the second virtual shift register shown in fig. 12, the fourth transistor is removed to reduce the area of the gate driving circuit and increase the wiring space. In this regard, the signal of the second voltage terminal is not transmitted to the first node, so that the second dummy shift register can keep outputting the invalid level signal during the reverse scan. And when the grid drive circuit is in positive scanning, the positive scanning input end of the second virtual shift register is connected with the scanning signal output by the output end of the Nth-stage shift register, the third transistor is controlled to connect the first voltage end with the first node, and after the work processing of each composition structure of the second virtual shift register, the turn-off signal is output to the positive turn-off input end of the Nth-stage shift register, so that the Nth-stage shift register is turned off.
In an embodiment of the present invention, on the basis of the second dummy shift register shown in fig. 12 and 13, transistors may be added to maintain an arrangement substantially symmetrical to the number of structural devices of the second to N-1 th shift registers or substantially symmetrical to the self circuit structure. Specifically, as shown in fig. 14, which is a schematic structural diagram of another second virtual shift register provided in the embodiment of the present invention, a precharge module of the first virtual shift register shown in fig. 14 is partially the same as a precharge module of the second virtual shift register shown in fig. 12, except that: the precharge module of the second dummy shift register shown in fig. 14 of the present invention further includes: a gate of the third auxiliary transistor T13 and a gate of the third auxiliary transistor T13 are electrically connected to the output terminal of the nth stage shift register, a first terminal of the third auxiliary transistor T13 is electrically connected to the first voltage terminal DIR1, and a second terminal of the third auxiliary transistor T13 is electrically connected to the first node P.
Or as shown in fig. 15, which is a schematic structural diagram of another second virtual shift register provided in the embodiment of the present invention, a precharge module of the first virtual shift register shown in fig. 15 is partially the same as a precharge module of the second virtual shift register shown in fig. 13, except that: the precharge module of the second dummy shift register provided in fig. 15 of the present invention further includes: a gate of the third auxiliary transistor T13 and a gate of the third auxiliary transistor T13 are electrically connected to the output terminal of the nth stage shift register, a first terminal of the third auxiliary transistor T13 is electrically connected to the first voltage terminal DIR1, and a second terminal of the third auxiliary transistor T13 is electrically connected to the first node P.
Or as shown in fig. 16, which is a schematic structural diagram of another second virtual shift register provided in the embodiment of the present invention, a precharge module of the first virtual shift register shown in fig. 16 is partially the same as a precharge module of the second virtual shift register shown in fig. 12, except that: the second virtual shift register precharge module shown in fig. 16 of the present invention further includes: a third auxiliary transistor T13, a gate of the third auxiliary transistor T13 being electrically connected to the output terminal of the nth stage shift register, a first terminal of the third auxiliary transistor T13 being electrically connected to the first voltage terminal DIR1, a second terminal of the third auxiliary transistor T13 being electrically connected to the first node P; a gate of the fourth auxiliary transistor T14, the fourth auxiliary transistor T14 is connected to the normally-off control signal VGx, a first terminal of the fourth auxiliary transistor T14 is electrically connected to the second voltage terminal DIR2, and a second terminal of the fourth auxiliary transistor T14 is electrically connected to the first node P.
Or as shown in fig. 17, which is a schematic structural diagram of a second virtual shift register according to another embodiment of the present invention, a precharge module of the first virtual shift register shown in fig. 17 is partially the same as a precharge module of the second virtual shift register shown in fig. 12, except that: the precharge module of the second dummy shift register provided in fig. 17 of the present invention further includes: a gate of the fourth auxiliary transistor T14, the fourth auxiliary transistor T14 is connected to the normally-off control signal VGx, a first terminal of the fourth auxiliary transistor T14 is electrically connected to the second voltage terminal DIR2, and a second terminal of the fourth auxiliary transistor T14 is electrically connected to the first node P.
As shown in fig. 18, a schematic structural diagram of a first stage shift register according to an embodiment of the present invention is shown, where a precharge module of the first stage shift register according to the embodiment of the present invention includes: a fifth transistor T5, a gate of the fifth transistor T5 is connected to the forward scan trigger signal STV11 (the gate of the fifth transistor T5 is the forward scan input terminal SET of the first stage shift register), a first end of the fifth transistor T5 is electrically connected to the first voltage terminal DIR1, and a second end of the fifth transistor T5 is electrically connected to the first node P; a sixth transistor T6, a gate of the sixth transistor T6 is electrically connected to the output terminal of the second stage shift register (the gate of the sixth transistor T6 is the inverse scan input END of the first stage shift register), a first END of the sixth transistor T6 is electrically connected to the second voltage terminal DIR2, and a second END of the sixth transistor T6 is electrically connected to the first node P; a gate of the fifth auxiliary transistor T15, a gate of the fifth auxiliary transistor T15 is electrically connected to the output terminal of the first dummy shift register (the gate of the fifth auxiliary transistor T15 is the reverse turn-off input terminal DSET of the first stage shift register), a first terminal of the fifth auxiliary transistor T15 is electrically connected to the first voltage terminal DIR1 or the gate of the fifth auxiliary transistor (the first terminal of the fifth auxiliary transistor and the gate electrical connection thereof are not shown), and a second terminal of the fifth auxiliary transistor T15 is electrically connected to the first node P.
It can be understood that, the first stage shift register provided in the embodiment of the present invention receives the forward scan trigger signal when the gate driving circuit is in the forward scan state, so as to trigger the first stage shift register to operate and output the scan signal to the second stage shift register. And when the grid driving circuit performs reverse scanning, the first-stage shift register is switched on to work after being accessed with the scanning signal output by the second-stage shift register, and the first-stage shift register outputs the scanning signal to the reverse scanning input end of the first virtual shift register, so that the first virtual shift register works to output a turn-off signal to the reverse turn-off input end of the first-stage shift register, the current work of the first-stage shift register is turned off through the turn-off signal, and the reverse scanning process of the grid driving circuit is completed.
In an embodiment of the present invention, on the basis of the first stage shift register shown in fig. 18, transistors may be added to maintain an arrangement that is substantially symmetrical to the number of structural devices of the second to N-1 th shift registers or substantially symmetrical to the self circuit structure. Fig. 19 is a schematic structural diagram of another first-stage shift register according to an embodiment of the present invention, in which a precharge module of the first-stage shift register shown in fig. 19 is partially the same as the precharge module of the first-stage shift register shown in fig. 18, except that: the precharge module of the first stage shift register provided in fig. 19 of the present invention further includes: a gate of the sixth auxiliary transistor T16 is electrically connected to an output terminal of the second stage shift register (the gate of the sixth auxiliary transistor T16 is an inverse scan input terminal END of the first stage shift register), a first terminal of the sixth auxiliary transistor T16 is electrically connected to the second voltage terminal DIR2, and a second terminal of the sixth auxiliary transistor T16 is electrically connected to the first node P.
As shown in fig. 20, a schematic structural diagram of an nth stage shift register according to an embodiment of the present invention is provided, wherein a precharge module of the nth stage shift register includes: a seventh transistor T7, a gate of the seventh transistor T7 is electrically connected to the output terminal of the N-1 th stage shift register (the gate of the seventh transistor T7 is the forward scan input terminal SET of the nth stage shift register), a first terminal of the seventh transistor T7 is electrically connected to the first voltage terminal DIR1, and a second terminal of the seventh transistor T7 is electrically connected to the first node P; an eighth transistor T8, a gate of the eighth transistor T8 is connected to the reverse scan trigger signal STV12, a first terminal of the eighth transistor T8 is electrically connected to the second voltage terminal DIR2, and a second terminal of the eighth transistor T2 is electrically connected to the first node P; a gate of the seventh auxiliary transistor T17, a gate of the seventh auxiliary transistor T17 is electrically connected to the output terminal of the second dummy shift register (the gate of the seventh auxiliary transistor T17 is the forward-off input terminal ded of the nth stage shift register), a first terminal of the seventh auxiliary transistor T17 is electrically connected to the second voltage terminal DIR2 or the gate of the seventh auxiliary transistor (an electrical connection structure between the first terminal of the seventh auxiliary transistor and the gate thereof is not shown), and a second terminal of the seventh auxiliary transistor T17 is electrically connected to the first node P.
In an embodiment of the present invention, on the basis of the nth stage shift register shown in fig. 20, transistors may be added to maintain an arrangement that is substantially symmetrical to the number of structural devices of the second to N-1 th shift registers or substantially symmetrical to the own circuit structure. Fig. 21 is a schematic structural diagram of another nth stage shift register according to an embodiment of the present invention, wherein a precharge module of the nth stage shift register shown in fig. 21 is partially the same as the precharge module of the nth stage shift register shown in fig. 20, except that: the precharge module of the nth stage shift register shown in fig. 20 of the present invention further includes: a gate of the eighth auxiliary transistor T18, the gate of the eighth auxiliary transistor T18 is electrically connected to the output terminal of the N-1 th shift register (the gate of the eighth auxiliary transistor T18 is the forward scan input terminal SET of the nth shift register), a first end of the eighth auxiliary transistor T18 is electrically connected to the first voltage terminal DIR1, and a second end of the eighth auxiliary transistor T18 is electrically connected to the first node P.
In an embodiment of the present invention, the first pull-down module, the second pull-down module, the output module, and the reset module of the first virtual shift register, the second virtual shift register, the first stage shift register, and the nth stage shift register provided in the present invention are all the same as the circuit structures shown in fig. 4, and redundant description is not repeated herein. And the forward scanning trigger signal and the reverse scanning trigger signal provided by the invention are the same signal, thereby reducing the number of signal ends in the circuit.
Correspondingly, the embodiment of the invention also provides a display device, and the display device comprises the gate driving circuit provided by any one of the embodiments.
As shown in fig. 22, which is a schematic structural diagram of a display device according to an embodiment of the present invention, the display device according to an embodiment of the present invention includes the gate driving circuit according to any one of the embodiments described above, where the display device may be a mobile terminal 1000.
It should be noted that the display device provided in the embodiment of the present invention may also be a notebook, a tablet, a computer, a wearable device, and the like, and the present invention is not limited in particular.
The embodiment of the invention provides a gate drive circuit, a drive method thereof and a display device, wherein the gate drive circuit comprises: the shift register comprises a first virtual shift register, a second virtual shift register, a first-stage shift register to an Nth-stage shift register, wherein N is a positive integer greater than 2; the output end of the first virtual shift register is electrically connected with the reverse closing input end of the first-stage shift register, the reverse scanning input end of the first virtual shift register is electrically connected with the output end of the first-stage shift register, and the forward scanning input end of the first-stage shift register is connected with a forward scanning trigger signal; the output end of the ith stage shift register is electrically connected with the forward scanning input end of the (i +1) th stage shift register, the output end of the (i +1) th stage shift register is electrically connected with the reverse scanning input end of the ith stage shift register, and i is an integer which is greater than or equal to 1 and less than N; the output end of the second virtual shift register is electrically connected with the forward closing input end of the Nth-stage shift register, the forward scanning input end of the second virtual shift register is electrically connected with the output end of the Nth-stage shift register, and the reverse scanning input end of the Nth-stage shift register is connected with a reverse scanning trigger signal.
As can be seen from the above, in the technical solution provided in the embodiment of the present invention, the nth shift register can be turned off by the second virtual shift register when the gate driving circuit scans in the forward direction, and the first shift register can be turned off by the first virtual shift register when the gate driving circuit scans in the reverse direction, so as to ensure that the display device can realize the function of scanning in both the forward and reverse directions.
In addition, the first-stage shift register provided by the embodiment of the invention is directly connected to the forward scanning trigger signal, so that the forward scanning trigger signal directly acts on the first-stage shift register without passing through the first virtual shift register, and the problem of drive delay of the gate drive circuit during forward scanning is solved; and the Nth-stage shift register is directly contacted with the reverse scanning trigger signal, so that the reverse scanning trigger signal is directly acted on the Nth-stage shift register without passing through the second virtual shift register, and the problem of drive delay of a gate drive circuit during reverse scanning is solved. Therefore, according to the technical scheme provided by the embodiment of the invention, on the basis of ensuring that the gate driving circuit can realize bidirectional scanning, the driving delay of the gate driving circuit is reduced, and the performance of the display device is improved.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (19)
1. A gate drive circuit, comprising: the shift register comprises a first virtual shift register, a second virtual shift register, a first-stage shift register to an Nth-stage shift register, wherein N is a positive integer greater than 2;
the output end of the first virtual shift register is electrically connected with the reverse closing input end of the first-stage shift register, the reverse scanning input end of the first virtual shift register is electrically connected with the output end of the first-stage shift register, and the forward scanning input end of the first-stage shift register is connected with a forward scanning trigger signal;
the output end of the ith stage shift register is electrically connected with the forward scanning input end of the (i +1) th stage shift register, the output end of the (i +1) th stage shift register is electrically connected with the reverse scanning input end of the ith stage shift register, and i is an integer which is greater than or equal to 1 and less than N;
the output end of the second virtual shift register is electrically connected with the forward closing input end of the Nth-stage shift register, the forward scanning input end of the second virtual shift register is electrically connected with the output end of the Nth-stage shift register, and the reverse scanning input end of the Nth-stage shift register is connected with a reverse scanning trigger signal.
2. The gate driving circuit according to claim 1, wherein the first dummy shift register, the second dummy shift register, and the first to nth stage shift registers each include: the device comprises a pre-charging module, a first pull-down module, a second pull-down module and an output module;
the output end of the pre-charging module is electrically connected with the first node;
the first pull-down module is electrically connected with the first node, and the first pull-down module controls the connection state between a reference level end and a second node in response to a signal of the first node;
the second pull-down module is electrically connected with the second node, responds to a first clock signal to control a signal of the second node, and responds to the signal of the second node to control the connection state between a reference level end and the first node and between the reference level end and the output end of the shift register;
the output module is electrically connected to the first node, controls an on state between the first clock signal and the output terminal of the shift register in response to a signal of the first node, and controls an on state between the reference level terminal and the output terminal of the shift register in response to a second clock signal.
3. The gate driving circuit of claim 2, wherein the pre-charge module of the first dummy shift register comprises: a first transistor, a gate of which is connected to a normally-off control signal, a first terminal of which is connected to a first voltage terminal, and a second terminal of which is electrically connected to the first node;
and a gate of the second transistor is electrically connected with the output end of the first-stage shift register, a first end of the second transistor is electrically connected with a second voltage end, and a second end of the second transistor is electrically connected with the first node.
4. The gate driving circuit of claim 2, wherein the pre-charge module of the first dummy shift register comprises: and a gate of the second transistor is electrically connected with the output end of the first-stage shift register, a first end of the second transistor is electrically connected with a second voltage end, and a second end of the second transistor is electrically connected with the first node.
5. The gate driving circuit according to claim 3 or 4, wherein the precharge module of the first dummy shift register further comprises: and the grid electrode of the first auxiliary transistor is electrically connected with the output end of the first-stage shift register, the first end of the first auxiliary transistor is electrically connected with the second voltage end, and the second end of the first auxiliary transistor is electrically connected with the first node.
6. The gate driving circuit of claim 3, wherein the pre-charge module of the first dummy shift register further comprises: a gate of the first auxiliary transistor is electrically connected to an output terminal of the first stage shift register, a first end of the first auxiliary transistor is electrically connected to the second voltage terminal, and a second end of the first auxiliary transistor is electrically connected to the first node;
a gate of the second auxiliary transistor is connected to a normally-off control signal, a first end of the second auxiliary transistor is connected to the first voltage end, and a second end of the second auxiliary transistor is electrically connected to the first node.
7. The gate driving circuit of claim 3, wherein the pre-charge module of the first dummy shift register further comprises: and a gate of the second auxiliary transistor is connected to a normally-off control signal, a first end of the second auxiliary transistor is connected to the first voltage end, and a second end of the second auxiliary transistor is electrically connected to the first node.
8. The gate driving circuit of claim 2, wherein the pre-charge module of the second dummy shift register comprises: a third transistor, a gate of which is electrically connected to an output terminal of the nth shift register, a first terminal of which is electrically connected to a first voltage terminal, and a second terminal of which is electrically connected to the first node;
and a gate of the fourth transistor is connected with a normally-off control signal, a first end of the fourth transistor is electrically connected with the second voltage end, and a second end of the fourth transistor is electrically connected with the first node.
9. The gate driving circuit of claim 2, wherein the pre-charge module of the second dummy shift register comprises: and a gate of the third transistor is electrically connected to the output terminal of the nth shift register, a first end of the third transistor is electrically connected to the first voltage terminal, and a second end of the third transistor is electrically connected to the first node.
10. A gate drive circuit as claimed in claim 8 or 9, wherein the precharge module of the second dummy shift register further comprises: and a gate of the third auxiliary transistor is electrically connected with an output end of the nth-stage shift register, a first end of the third auxiliary transistor is electrically connected with the first voltage end, and a second end of the third auxiliary transistor is electrically connected with the first node.
11. The gate driving circuit of claim 8, wherein the precharge module of the second dummy shift register further comprises: a gate of the third auxiliary transistor is electrically connected to an output terminal of the nth stage shift register, a first terminal of the third auxiliary transistor is electrically connected to the first voltage terminal, and a second terminal of the third auxiliary transistor is electrically connected to the first node;
a gate of the fourth auxiliary transistor is connected to a normally-off control signal, a first end of the fourth auxiliary transistor is electrically connected to the second voltage end, and a second end of the fourth auxiliary transistor is electrically connected to the first node.
12. The gate driving circuit of claim 8, wherein the precharge module of the second dummy shift register further comprises: a gate of the fourth auxiliary transistor is connected to a normally-off control signal, a first end of the fourth auxiliary transistor is electrically connected to the second voltage end, and a second end of the fourth auxiliary transistor is electrically connected to the first node.
13. The gate driving circuit of claim 2, wherein the pre-charge module of the first stage shift register comprises: a gate of the fifth transistor is connected to the forward scanning trigger signal, a first end of the fifth transistor is electrically connected to a first voltage end, and a second end of the fifth transistor is electrically connected to the first node;
a gate of the sixth transistor is electrically connected with an output end of the second-stage shift register, a first end of the sixth transistor is electrically connected with a second voltage end, and a second end of the sixth transistor is electrically connected with the first node;
a gate of the fifth auxiliary transistor is electrically connected to the output terminal of the first dummy shift register, a first end of the fifth auxiliary transistor is electrically connected to the first voltage terminal or the gate of the fifth auxiliary transistor, and a second end of the fifth auxiliary transistor is electrically connected to the first node.
14. The gate driving circuit of claim 13, wherein the pre-charge module of the first stage shift register further comprises: and a gate of the sixth auxiliary transistor is electrically connected to an output end of the second stage shift register, a first end of the sixth auxiliary transistor is electrically connected to the second voltage end, and a second end of the sixth auxiliary transistor is electrically connected to the first node.
15. The gate driving circuit according to claim 2, wherein the precharge module of the nth stage shift register comprises: a gate of the seventh transistor is electrically connected with an output end of the shift register of the (N-1) th stage, a first end of the seventh transistor is electrically connected with the first voltage end, and a second end of the seventh transistor is electrically connected with the first node;
a gate of the eighth transistor is connected to the reverse scan trigger signal, a first end of the eighth transistor is electrically connected to a second voltage end, and a second end of the eighth transistor is electrically connected to the first node;
a seventh auxiliary transistor, a gate of which is electrically connected to an output terminal of the second dummy shift register, a first terminal of which is electrically connected to the second voltage terminal or the gate of the seventh auxiliary transistor, and a second terminal of which is electrically connected to the first node.
16. The gate driving circuit of claim 15, wherein the precharge module of the nth stage shift register further comprises: and a gate of the eighth auxiliary transistor is electrically connected with an output end of the N-1 th-stage shift register, a first end of the eighth auxiliary transistor is electrically connected with the first voltage end, and a second end of the eighth auxiliary transistor is electrically connected with the first node.
17. The gate driving circuit according to claim 1, wherein the forward direction scan trigger signal and the reverse direction scan trigger signal are the same signal.
18. A driving method of a gate driving circuit, applied to the gate driving circuit of any one of claims 1 to 17, comprising:
during forward scanning, controlling the forward scanning trigger signal to trigger the first-stage shift register, so that the first-stage shift register to the Nth-stage shift register sequentially output scanning signals, and after the Nth-stage shift register outputs the scanning signals, the second virtual shift register responds to the scanning signals output by the Nth-stage shift register and outputs a turn-off signal to a forward turn-off input end of the Nth-stage shift register, wherein the first virtual shift register keeps outputting an invalid level signal;
and when the second virtual shift register outputs an invalid level signal, the second virtual shift register controls the reverse scanning trigger signal to trigger the Nth shift register so that the Nth shift register and the first shift register sequentially output scanning signals, and the first virtual shift register responds to the scanning signals output by the first shift register and outputs a turn-off signal to a reverse turn-off input end of the first shift register after the first shift register outputs the scanning signals.
19. A display device comprising the gate driver circuit according to any one of claims 1 to 17.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101984485A (en) * | 2010-11-03 | 2011-03-09 | 友达光电股份有限公司 | Display device with bidirectional-transfer shift registers |
| JP2012215899A (en) * | 2012-06-29 | 2012-11-08 | Mitsubishi Electric Corp | Gate line drive circuit |
| CN105719593A (en) * | 2016-04-29 | 2016-06-29 | 上海中航光电子有限公司 | Grid electrode driving circuit, display panel and electronic equipment |
| US20190066617A1 (en) * | 2017-04-12 | 2019-02-28 | Boe Technology Group Co., Ltd. | Shift Register Unit, Gate Driving Circuit and Driving Method Thereof |
-
2021
- 2021-06-25 CN CN202110714148.1A patent/CN113450692A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101984485A (en) * | 2010-11-03 | 2011-03-09 | 友达光电股份有限公司 | Display device with bidirectional-transfer shift registers |
| JP2012215899A (en) * | 2012-06-29 | 2012-11-08 | Mitsubishi Electric Corp | Gate line drive circuit |
| CN105719593A (en) * | 2016-04-29 | 2016-06-29 | 上海中航光电子有限公司 | Grid electrode driving circuit, display panel and electronic equipment |
| US20190066617A1 (en) * | 2017-04-12 | 2019-02-28 | Boe Technology Group Co., Ltd. | Shift Register Unit, Gate Driving Circuit and Driving Method Thereof |
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Application publication date: 20210928 |