Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/46—Manufacturing multilayer circuits
  • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
  • H05K3/4691—Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; ELECTRIC HEARING AIDS; PUBLIC ADDRESS SYSTEMS
  • H04R17/00—Piezoelectric transducers; Electrostrictive transducers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; ELECTRIC HEARING AIDS; PUBLIC ADDRESS SYSTEMS
  • H04R31/00—Apparatus or processes specially adapted for the manufacture of transducers or diaphragms therefor
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09009—Substrate related
  • H05K2201/09109—Locally detached layers, e.g. in multilayer
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
  • H05K2201/09872—Insulating conformal coating
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
  • H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
  • H05K2203/308—Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/46—Manufacturing multilayer circuits
  • H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components

Definitions

• Acoustic impedance (the speed of sound in a material multiplied by its density, measured in Rayls) is a measure of the opposition that a system presents to the acoustic pressure applied to the system. It is an important quantity in piezoelectricbased ultrasound systems, since it determines how much acoustic power is effectively transferred to a target material being imaged.
• An “acoustic matching layer” is a mandatory structure in piezoelectric-based systems to reduce the impedance mismatch between the impedance of the piezoelectric crystals and the lower or higher impedance of the target materials (e.g., tissues or metals). These matching layers are typically made of high-density rubber combined with liquid gel, and are located between the crystals and the target material.
• United States patent nos. 10,509,013, 10,564,132, and 10,598,632 collectively describe two ways of microfabricating CMUTs: surface micromachining and wafer-bonding.
• surface micromachining the cavity underneath the membrane is created by depositing or growing a sacrificial layer on the carrier substrate. After membrane deposition, the sacrificial layer is removed with an etchant that is specifically chosen to dissolve the sacrificial material via etch channels without damaging the membrane material.
• wafer-bonding the membrane and the cavity are defined on separate wafers that are bonded together under vacuum conditions. Given that etching channels are not required, the fabrication process is simplified, and a higher fill factor can be achieved.
• Silicon nitride and polysilicon are the most popular materials for fabricating CMUT membranes, while chromium and aluminum are typically used to pattern electrodes on top of these membranes. These materials are chosen mainly for their mechanical properties, such that the membranes can be as thin as possible, in order to minimize the effective gap between the bottom and top (or “hot”) electrodes. By decreasing the effective gap between electrodes, the electric field can be increased, and the impedance matching to the electronics that drive the CMLIT can be improved. Once the desired operational frequency and the maximum biasing voltage have been identified, the CMLIT membranes are preferably designed as thick as possible, given that their bandwidths linearly increase with thickness.
• TSVs Through Silicon Vias
• TSVs are vertical electrical interconnects that pass through a silicon wafer or chip, connecting different layers of circuitry. TSVs are used to enable better performance, smaller form factors, and higher integration in semiconductor devices. They offer several advantages, including reduced signal propagation delays, increased bandwidth, and the ability to connect multiple chip layers in a compact manner.
• the main limitation with TSVs is that they only permit communication between opposing sides of the substrate (front and rear) through a vertical conductive channel.
• PCBs can facilitate routing in different layers through the use of vias and multi-layer construction.
• Through-hole vias go through the entire thickness of the PCB, connecting all layers. They are commonly used for components and traces that require strong connections.
• Blind and buried vias connect only specific layers of the PCB.
• Blind vias connect an outer layer to one or more inner layers, while buried vias connect two or more inner layers. Both types of vias allow for more complex routing without affecting the outer layers.
• Modem PCBs often consist of multiple layers of copper traces separated by insulating material in the form of the PCB’s substrate. The inner layers are sandwiched between the outer layers. Each layer can be used for routing, power planes, or ground planes.
• PCBs can be fabricated using materials such as FR-4 (fiberglass-reinforced epoxy), high-Tg materials for elevated temperatures, flexible materials like polyimide and polyester, rigid-flex materials combining rigidity and flexibility, metal core materials for improved heat dissipation, ceramic materials for high-temperature stability, RF/microwave materials for high-frequency applications, and specialized materials like TeflonTM (PTFE) for specific performance requirements.
• FR-4 fiberglass-reinforced epoxy
• high-Tg materials for elevated temperatures
• flexible materials like polyimide and polyester
• rigid-flex materials combining rigidity and flexibility
• metal core materials for improved heat dissipation
• ceramic materials for high-temperature stability
• RF/microwave materials for high-frequency applications
• PTFE TeflonTM
• the choice depends on factors such as application, thermal management, operating frequency, and desired electrical and mechanical properties.
• Low-temperature co-fired ceramic is a ceramic electronics technology used for ceramic PCB or PCBA (i.e. , a PCB assembly with all components on the PCB) fabrication.
• LTCC developed from the HTCC (high-temperature co-fired ceramic) technology in 1982, is a multilayer low-temperature ceramic PCB manufacturing technology.
• HTCC is a ceramic based on alumina (AI2O3) and aluminum nitride (AIN).
• LTCC is a ceramic in which glass is mixed into alumina, and is also generally referred to as “glass ceramics”.
• HTCC substrates are cured at a temperature of 1500 °C or higher.
• tungsten (W) and molybdenum (Mo), which have high melting points, are used for the circuit electrodes.
• the curing temperature can be decreased down to 900 °C by mixing glass into the alumina ceramic.
• silver or copper, which have low conductivity, for wiring is possible to use.
• PCBs fabricated in FR-4 utilize a composite material of fiberglass and epoxy, offering moderate electrical insulation and mechanical strength, suitable for standard electronics.
• FR-4 is versatile and cost-effective for general-purpose electronics and can be manufactured by a great number of fabrication facilities around the world.
• PCBs made with LTCC involve layering ceramic tapes with embedded conductors, resulting in superior electrical properties, high thermal stability, and suitability for high-frequency and high-temperature applications, making them ideal for RF modules, microwave devices, and sensors in demanding environments.
• a method for manufacturing a capacitive micromachined ultrasonic transducer comprising: removing a layer from a top side of a substrate, wherein at least a pair of electrical interconnects extend at least partially through the substrate and are exposed on the top side; after the removing, depositing a first electrically conductive material on the top side, wherein the first electrically conductive material covers the pair of electrical interconnects; patterning the first conductive material to form a bottom electrode and a contact area for a top electrode, wherein the bottom electrode is electrically connected to one of the pair of electrical interconnects and the contact area for the top electrode is electrically connected to the other of the pair of electrical interconnects; after the patterning, depositing a sacrificial material on the bottom electrode; patterning the sacrificial material to form a sacrificial membrane area connected to at least one sacrificial etch channel; after the sacrificial material is patterned, deposit
• the first polymer layer may be deposited on the substrate, the bottom electrode, the contact area for the top electrode, and the sacrificial material after the sacrificial material is patterned, and the method may further comprise: depositing a second polymer layer on top of the second electrically conductive material and the sacrificial membrane area; and patterning the second polymer layer to avoid plugging the at least one via.
• the silicon layer may be deposited on the substrate, the bottom electrode, the contact area for the top electrode, and the sacrificial material after the sacrificial material is patterned.
• the substrate may comprise a printed circuit board.
• the printed circuit board may be flexible.
• the substrate may comprise a ceramic.
• Removing the layer may be performed mechanically.
• removing the layer may comprise polishing or grinding the top side of the substrate.
• the top side may have a surface roughness of no more than 50 nanometers.
• the first conductive material may comprise a layer of gold between two layers of chromium.
• the first conductive material may have a thickness of approximately 100 nm.
• the sacrificial material may be approximately 200 nm thick.
• Depositing the sacrificial material may comprise depositing a layer of lift-off resist and then depositing a layer of positive photoresist.
• Patterning the sacrificial material may be performed by wet etching using an aqueous solution comprising tetramethylammonium hydroxide.
• Figure 26A and Figure 26B show the top and cross-sectional views respectively of the substrate shown in Figure 25A and Figure 25B after a second polymer layer was deposited and patterned; the via holes on the first polymer layer remain open so that the sacrificial layer can be etched.
• Figure 35A and Figure 35B show the top and cross-sectional views respectively of the substrate shown in Figure 34A and Figure 34B after the sacrificial layer has been etched in a solvent.
• the remaining structure is a CMLIT with a cavity filled with air.
• Figure 39A and Figure 39B show the top isometric and top plan views respectively of an example polyCMUT linear array fabricated from the substrate of Figures 38A and 38B.
• Figure 40A and Figure 40B show the bottom isometric and bottom plan views respectively of the polyCMUT linear array of Figures 39A and 39B,.
• Figure 41 shows the cross-sectional view of the polyCMUT linear array of Figures 39A and 39B.
• Figure 43A shows the top view of the polyCMUT matrix array of Figures 42A and 42B.
• the polyCMUTs were fabricated on a polished surface with embedded vias.
• Figure 43B shows the detail A from Figure 43A showing a plurality of polyCMUT elements in a matrix array. The via holes are not visible.
• Figure 44A shows the bottom view of the polyCMUT matrix array of Figures 42A and 42B.
• Figure 45A shows the bottom view of a polyCMUT linear array fabricated according to an example embodiment.
• Figure 45A shows an electrical contact assembly mounted at the rear of the array with a plurality of electrical tracks.
• Figure 45B shows the detail A shown in Figure 45A.
• An optional electronic component or a circuit containing electronic components, such as a bias tee is mounted between the vias and the electrical contact assembly.
• Figure 46A shows the top view of the polyCMUT linear array of Figure 45A showing a plurality of polyCMUT elements.
• Figure 46D shows the detail B from Figure 46B, in which several layers of the substrate with embedded electronic components are illustrated.
• Figure 47 shows an exploded view of a polyCMUT transducer assembly fabricated according to an example embodiment.
• An acoustic lens is mounted on top of a polyCMUT linear array and a contact assembly is mounted at the rear.
• Figures 48A, 48B, and 48C show the cross-sectional view of a polyCMUT linear array fabricated according to an example embodiment with different thicknesses and their relative bending condition along at least one axis. A thinner substrate leads to a smaller of curvature.
• Figures 49A and 49B are pictures of a substrate having a circular shape and a plurality of conductive vias.
• Figure 50A shows the detail B shown in Figure 49B.
• the plurality of contact areas where an ordinary electrical header can be mounted are apparent in Figure 50A.
• Figure 50B shows the detail C shown in Figure 50A. The individual annular rings and even the conductive vias are apparent in Figure 50B.
• Figure 51 shows the detail A from Figure 49A. In Figure 51 , a plurality of via holes that will connect to the top electrode in polyCMUT elements are apparent.
• Figure 52A and Figure 52B show the measurement of the surface roughness of the substrate of Figures 49A and 49B before and after the substrate has been polished.
• Figure 53A shows a circular substrate with several polyCMUT arrays fabricated on the top of the substrate of Figures 49A and 49B, according to an example embodiment.
• Figure 53B shows several of the polyCMUT arrays of Figure 53A after the substrate was diced to mechanically separate the arrays in the substrate.
• Figure 54A shows a linear polyCMUT array fabricated according to an example embodiment. A contact assembly was soldered at the bottom of the array.
• Figure 54B shows the polyCMUT array from Figure 54A mounted on a test circuit board.
• the polyCMUT elements can be independently controlled using this test circuit.
• Figure 55A shows the time-domain response obtained from the polyCMUT array from Figure 54B operating in water.
• the CMUT transducer has a short pulse characteristic.
• Figure 55B shows the frequency domain response of Figure 55A using a Fast Fourier Transform (FFT).
• FFT Fast Fourier Transform
• Figure 56A shows the computer design of a substrate PCB having a circular shape and a plurality of conductive vias shown in the inset.
• Figure 56B shows the rear view of the substrate of Figure 56A, showing a plurality of contact pads electrically coupled to the substrate’s conductive vias.
• Figure 57A shows the front view of a physical substrate PCB manufactured based on the design of Figure 56A and having a circular shape and a plurality of conductive vias.
• the protective solder mask layer acts as a planarization layer.
• Figure 57B shows the front view of the substrate from Figure 57A after polishing the conductive and the planarization layers.
• Figure 58A shows a picture obtained using a microscope of the polished substrate from Figure 57B, with the polished surface having a mirror-like finishing.
• Figure 58B shows a zoomed-in view of the polished substrate from Figure 58A, showing the polished conductive material and the polished planarization layer.
• Figure 59A shows a picture of a needle profilometer to measure the surface roughness of the substrate from Figure 57B.
• Figure 59B shows the profilometer measurement along the longitudinal axis of the substrate from Figure 59A to measure the curvature or “bow” of the substrate.
• Figure 59C shows the profilometer measurement along the longitudinal axis of the substrate from Figure 59B to measure the surface roughness of the polished conductive material and the planarization layer.
• Figure 60A shows the profilometer measurement along the X and Y axes of a standard 100 mm prime-grade silicon wafer with an oxide layer to measure the curvature or “bow” of the substrate.
• Figure 60B shows the profilometer measurement along the X and Y axes of the substrate from Figure 59A to measure the curvature or “bow” of the substrate.
• Figure 61 A shows a short profilometer measurement along the X axis of the center region of a standard 100mm prime-grade silicon wafer with an oxide layer to measure the surface roughness of the substrate.
• Figure 61 B shows a short profilometer measurement along the X axis of the center region of the substrate from Figure 59A to measure the surface roughness of the substrate.
• Figure 62A shows a short profilometer measurement along the X axis of the planarization layer region from Figure 59A to measure the surface roughness.
• Figure 62B shows an even shorter profilometer measurement (relative to Figure 62A) along the X axis of the center region of the substrate from Figure 59A to measure the surface roughness of the substrate.
• Figure 63 shows a table with the expected ringing effects for a substrate consisting of FR4.
• the expected ringing correlates with the thickness of the substrate.
• Figure 64A and Figure 64B show cross-sectional views of an ultrasound assembly comprising polyCMUTs manufactured in accordance with an example embodiment.
• Figures 65A, 65B, and 65C show a probe assembly that has a flexible polyCMUT array manufactured in accordance with an example embodiment at its bottom.
• the polyCMUT array is deflected inwards depending on the pressure in an inner chamber of the probe assembly.
• Figures 66A, 66B, and 66C show a probe assembly that has a flexible polyCMUT array manufactured in accordance with an example embodiment at its bottom.
• the polyCMUT array is deflected inwards due to a deflection mechanism.
• Figure 67 shows a polyCMUT linear array manufactured in accordance with an example embodiment containing two planar inductors embedded in its substrate.
• An “annular ring” is the area of copper pad around a drilled and finished via. All around this via there is enough conductive material (such as copper) to form a solid connection between conductive traces and the via in a multilayer PCB. Therefore, the main purpose of an annular ring is to establish a good connection between a via and the conductive trace leading to the via. In some cases, a via can be created without the need of an annular ring, or the annular ring may be small enough to be comparable to the diameter of a via. An annular ring is a particular example of a conductive pad that is electrically connected to the via. b.
• Poly-CMUT elements may be formed by the methods disclosed in US Patent No. 10,598,362 by Cretu et al. or United States Patent No. 7,673,375 by Chang et al.
• LORTM lift-off resist composition comprising cyclopentanone, PGME, a polyaliphatic imide copolymer, and a proprietary dye (less than 2 percent of total volume) and a surfactant; and “SU-8”, an optically transparent polymer-based photoresist material that comprises bisphenol A NovolacTM epoxy dissolved in an organic solvent and comprises up to 10 weight percent triarylsulfonium/hexafluoroantimonate salt.
• the LORTM composition and SU-8 photoresist and the corresponding SU-8 developer may be acquired from Kayaku Advanced Materials of Westborough, Massachusetts. i.
• “Substrate” means an underlying substance or layer upon which the poly- CMLIT devices are fabricated.
• Substrates can comprise a range of metallic materials (e.g., aluminum), non-metallic materials (e.g., ceramics, composite materials), semiconductors (e.g., silicon) and even polymer- based materials such as polyimide, KaptonTM, plexiglass, or LexanTM.
• a substrate can also comprise optically transparent or semitransparent materials such as glass or Indium Tin Oxide (ITO).
• ITO Indium Tin Oxide
• a substrate can be rigid, semi-rigid, or flexible.
• a substrate can also comprise combinations of the aforementioned options: for example, a piece of glass covered by a layer of indium tin oxide, or a piece of polyimide covered by a metallic layer.
• a substrate in the form of a PCB may be rigid, semi-rigid, moderately flexible (i.e., bendable only to a certain radius of curvature), or fully flexible (i.e., bendable until opposing portions of the PCB contact each other and prevent further bending).
• Fully flexible PCBs in particular may be manufactured using polyimide as a substrate, for example.
• a “via” in a substrate such as a PCB is an electrical interconnect that extends at least partially through a substrate.
• a via may be an electrical conductive path created when a hole or opening is filled with conductive material. This via hole can connect two or more surfaces in a multi-layer substrate (for example, a PCB).
• Vias are typically created mechanically (by using drilling or laser ablation) or chemically (using abrasive materials to etch the substrate in a selective way). These holes can be later electroplated to create the electrically conductive path to form the via.
• a common material for electroplating is, in some embodiments, copper (Cu).
• a filler may be conductive or non-conductive epoxy. This is a practice to avoid material contamination and to prevent particles from accumulating in the hole. Vias can be plugged- vias, capped vias, though-hole vias, blind vias, buried vias, staggered vias, or microvias.
• Vias may follow a non-linear path through substrate (/.e., vias need not be a direct vertical connection between the top and bottom layers of the substrate).
• inner layers of a substrate may be interconnected using conductive traces to facilitate deviation from a linear via that extends linearly between a substrate’s top and bottom layers.
• X-ray mammography means the practice of using radiographic imaging of a breast of a patient to screen for breast cancer. Young women in particular have a high proportion of dense breast tissue. During the radiographic imaging, the dense breast tissue absorbs X-rays in a manner which is to some extent similar to potential tumor tissue, making it difficult to distinguish between dense breast tissue and potential tumor tissue. Poly-CMUT arrays are useful in association with x-ray mammography.
• Figures 1A - 9B are in respect of the fabrication procedure of polyCMUTs according to a first embodiment, where a PCB with pre-existing via holes is grinded and polished to obtain a surface roughness in the orders of a few nanometers or lower.
• Figures 10A - 19B are in respect of the fabrication procedure of polyCMUTs according to a second embodiment, where a PCB with pre-existing via holes is grinded and polished to obtain a surface roughness on the order of a few tens or hundreds of nanometers.
• a planarization layer is subsequently deposited to reduce the surface roughness down to a few nanometers or lower. This may be achieved, for instance, by spin-coating a layer of polymer on top.
• Figures 20A - 28B are in respect of the fabrication procedure of polyCMUTs according to a third embodiment, where a PCB with pre-existing via holes and a pre-existing bottom electrode is covered with a planarization layer. Then, the substrate is grinded and polished to obtain a surface roughness on the order of a few tens or hundreds of nanometers, exposing the polished surface of the bottom electrode.
• Figures 29A - 36B are in respect of the fabrication procedure of polyCMUTs according to a fourth embodiment, and involve a multi-layer PCB with more than two layers and pre-existing via holes accessible from the bottom side.
• the bottom electrode of the depicted polyCMUT is patterned in one of the inner layers, surrounded by subsequent layers of the same core material. Then, the substrate is grinded and polished to obtain a surface roughness on the order of a few tens or hundreds of nanometers, exposing the polished surface of the bottom electrode. There is no need to add a planarization layer since the core material surrounds and encapsulates the bottom electrode.
• Figures 37 A and 37B are in respect of the fabrication procedure of silicon-based CMUTs according to a fifth embodiment in which the silicon-based CMLIT is fabricated on a ceramic substrate.
• the assembly 10 is comprised of a substrate 11 with an exposed top side 12, bottom side 13 and vias 21 manufactured in the substrate 11.
• the bottom side 13 has additional layers in some embodiments (not shown), including protective layers for the conductive vias or for the protection of the substrate 11 .
• the vias 21 and the annular rings 22 are also exposed.
• the diameter D2 of the annular ring 22 extends beyond the diameter D1 of the via 21 .
• the vias 21 are shown completely filled for illustrative purposes.
• the assembly 10 is comprised of a substrate 11 with an exposed top side 12 and bottom side 13 and vias 21 manufactured in the substrate 11.
• the bottom side 13 may have additional layers (not shown), which may comprise protective layers for the conductive vias 21 or for the protection of the substrate 10.
• the vias 21 and the annular rings 22 are exposed. Note that diameter D2 of the annular ring 22 extends beyond diameter D1 of the via
• a sacrificial material 105 is deposited on top of the assembly 10, covering portions of the planarization layer 40 and the first conductive material 101.
• the sacrificial material 105 can be patterned using lithography techniques such as lift-off or etching a blanket layer of sacrificial material.
• the sacrificial material 105 may be, in some embodiments, a layer of LORTM lift-off resist, followed by a layer of, in some embodiments, positive photoresist.
• the first polymer via holes 111 allow the sacrificial material 105 to be etched using a solvent that allows the sacrificial membrane area 107 to become the cavity in a polyCMUT cell.
• the sacrificial membrane area 107 and the sacrificial etch channels 106 appear as dashed lines in Figure 15A.
• the first polymer layer 110 covers the unconnected region of the planarization layer 40 and prevents short circuits between the bottom electrode 102 and the contact area 103 for the top electrode.
• the thickness of this encapsulation material 130 is in at least some embodiments half of the thickness of the sacrificial material 105 to help ensure a proper seal of the sacrificial etch channels 106.
• the bottom side 13 of the assembly 10 can be protected (using for instance, peelable tape) to prevent the encapsulation material 130 from covering the annular rings 22.
• the areas where the air area 125 used to be are also replaced by a vacuum area 131.
• the vacuum area 131 allows the membrane in a polyCMUT cell to move in liquid-coupled applications, such as biomedical ultrasound examinations.
• the vacuum area 131 becomes the sealed cavity in a polyCMUT cell.
• the planarization layer 40 conformally covers all the sides of the substrate conductive material 23 that are not in contact with the substrate 11 .
• An optional degassing stage can be used to remove any air bubbles that might become trapped during the deposition of this planarization layer 40.
• the purpose of this planarization layer 40 is to fill the exposed areas on the top side 12 of the substrate 11 that are not already covered by the substrate conductive material 23.
• This first polymer layer 110 can be deposited using, in some embodiments, lithography coating techniques (such as a spin coater).
• the typical thickness of this first polymer layer 110 ranges from, in some embodiments, a few tens of nanometers to a few micrometers (typically 700 nm).
• the thickness of this first polymer layer 110 is tailored to a specific design for ultrasound transducers and to be able to withstand normal operational voltages, ranging from 10 V - 100 V.
• the first polymer layer 110 is patterned (in geometrical shapes) to form a uniform layer with some first polymer via holes 111.
• the first polymer via holes 111 create a direct connection to some portions of the sacrificial etch channels 106 from the exterior.
• the first polymer via holes 111 allow the sacrificial material 105 to be etched using a solvent that allows the sacrificial membrane area 107 to become the cavity in a polyCMUT cell.
• the sacrificial membrane area 107 and the sacrificial etch channels 106 appear as dashed lines in Figure 24A.
• the fist polymer layer 110 covers the unconnected region of the polished planarization layer 50 and prevents short circuits between the polished conductive area that acts as the bottom electrode 34 and the polished conductive area 35 for the top electrode.
• a second conductive material 115 is deposited on top of the assembly 10, covering portions of the first polymer layer 110 and some portions of the polished conductive area for top electrode 35.
• the second conductive material 115 can be patterned using lithography techniques such as lift-off or etching a blanket layer of conductive material.
• the second conductive material 115 may be, in some embodiments, a layer of titanium, followed by a layer of gold.
• This second conductive material 115 can be deposited using, in some embodiments, physical vapor deposition systems (such as a sputtering system) for a conformal covering.
• the typical thickness of this second conductive material 115 is, in some embodiments, a few tens of nanometers (typically 100 nm).
• the second conductive material 115 is patterned (in geometrical shapes) to form a top electrode area 116 and a top electrode interconnect 117.
• the second conductive material 115 is patterned in such a way to avoid any overlap with the first polymer via holes 111.
• the second conductive material 115 is patterned in such a way to avoid any electrical contact with the polished conductive area that acts as the bottom electrode 34 to avoid short circuiting the bottom and top electrodes of a polyCMUT cell.
• the second conductive material 115 is patterned in such a way to maintain an electrical contact with the polished conductive area 35 for the top electrode; therefore, an electrical connection is formed between the second conductive material 115 and only one of the vias 21 , which in Figure 25B is the via 21 on the right-hand side.
• the top electrode interconnect 117 is used to create an electrical connection with adjacent polyCMUT cells (not shown), and to allow the creation of polyCMUT elements 201. There exists at least one connection point between the top electrode interconnect 117 and the polished conductive area 35 for the top electrode.
• the second conductive layer 115 will become the top electrode in a polyCMUT cell.
• a second polymer layer 120 is deposited on top of the assembly 10, covering portions of the first polymer layer 110 and the second conductive material 115.
• This second polymer layer 120 can be, in some embodiments, a UV photosensitive material such as SU-8 photoresist.
• the second polymer layer 120 can be patterned directly using a UV exposure system and then patterned using, for example, wet etching using SU-8 developer.
• This second polymer layer 120 can also be patterned using lithography techniques such as lift-off or etching a blanket layer of polymer.
• This second polymer layer 120 can be deposited using, in some embodiments, lithography coating techniques (such as a spin coater).
• the typical thickness of this second polymer layer 120 ranges from, in some embodiments, a few hundreds of nanometers to a few tens of micrometers (typically 5 urn).
• the thickness of this second polymer layer 120 is tailored to a specific design for ultrasound transducers and to be able to withstand normal operational voltages.
• the second polymer layer 120 is patterned (in geometrical shapes) to form a second polymer membrane area 121 that avoids sealing or plugging the first polymer via holes 111.
• This second polymer layer 120 can also uniformly cover the entire assembly 10 (not shown in Figure 26A or Figure 26B) except in the areas where the first polymer via holes 111 are located.
• the purpose of this second polymer layer 120 is to increase the overall thickness of the membrane in a polyCMUT cell so as to be able to operate at frequencies between 1 MHz and 10 MHz..
• the sacrificial membrane area 107 and the sacrificial etch channels 106 appear as dashed lines in Figure 26A.
• the sacrificial material 105 (including the sacrificial etch channels 106 and the sacrificial membrane area 107) is etched, dissolved, or otherwise removed (e.g., mechanically).
• the sacrificial material 105 can be removed with wet etching using solvents or dry etching using gases.
• the assembly 10 When using wet etching, the assembly 10 is immersed in, in some embodiments, an aqueous solution containing tetramethylammonium hydroxide (TMAH) where the sacrificial material 105 is dissolved without damaging or dissolving the rest of the materials (i.e., the first polymer layer 110, second conductive material 115, and second polymer layer 120).
• TMAH tetramethylammonium hydroxide
• the assembly is transferred into a container filled with isopropanol (IPA); the IPA replaces the aqueous solution containing TMAH.
• the assembly 10 is transferred into the chamber of a critical point drier system (CPD), where liquid carbon dioxide (CO2) enters the chamber at high pressures and replaces the IPA; then this liquid CO2 transforms into gaseous CO2 when the pressure in the chamber is gradually reduced to atmospheric pressure.
• CPD critical point drier system
• CO2 liquid carbon dioxide
• the areas where the sacrificial material 105 used to be are now replaced by an air area 125.
• the air area 125 allows the membrane in a polyCMUT cell to move, but it is not suitable for water-coupled operations due to the presence of the first polymer via holes 111.
• an encapsulation material 130 is uniformly coated over the entire assembly 10, thereby covering portions of the polished planarization layer 50, the polished substrate conductive material 33, the first polymer layer 110, the second conductive material 115, and the second polymer layer 120.
• the encapsulation material 130 may be, in some embodiments, Parylene C.
• the encapsulation material 130 can be deposited using a low-pressure chamber, such as in a vacuum. The encapsulation material 130 conformally coats the top side 12 of the assembly 10, and it gradually accumulates in the inner walls of the sacrificial etch channels 106 until they are sealed.
• the thickness of this encapsulation material 130 is in at least some embodiments at least half of the thickness of the sacrificial material 105 so as to have a proper seal of the sacrificial etch channels 106.
• the bottom side 13 of the assembly 10 can be protected (using for instance peelable tape) to prevent the encapsulation material 130 from covering the annular rings 22.
• the areas where the air area 125 was is replaced by a vacuum area 131 .
• the vacuum area 131 allows the membrane in a polyCMUT cell to move in liquid-coupled applications, such as biomedical ultrasound examination.
• the vacuum area 131 becomes the sealed cavity in a polyCMUT cell.
• the assembly 10 is comprised of a substrate 11 bonded and accordingly adhered to an upper substrate layer 14.
• This upper substrate layer 14 is made of the same material as the substrate 11.
• the materials for the substrate 11 and the upper substrate layer 14 typically comprise, in some embodiments, glass-reinforced epoxy laminate material (commonly known as “FR4”) or hydrocarbon ceramic laminates (commonly known as “Rogers material”).
• FR4 glass-reinforced epoxy laminate material
• Rogers material commonly known as “Rogers material”.
• the substrate 11 and the upper substrate layer 14 are typically bonded in vacuum at high temperatures to avoid any air bubbles or voids in between.
• the assembly 10 may have an additional lower substrate layer 15 (not shown in Figure 29A or 29B) bonded on the bottom side 13 of the substrate 10.
• This optional lower substrate layer 15 has the same physical properties as the upper substrate layer 14.
• the optional lower substrate layer 15 may have vias 21 to maintain an electrical connection with the substrate conductive material 23.
• the bottom side 13 of the substrate 11 may have additional layers (not shown) that may include protective layers for the conductive vias 21 or for the protection of the substrate 11.
• the vias 21 and the annular rings 22 are exposed.
• the diameter D2 of the annular ring 22 extends beyond the diameter D1 of the via 21.
• the vias 21 are shown completely filled for illustrative purposes.
• the thickness TC of the substrate conductive material 23 used for the annular ring 22 is determined from manufacturing specifications.
• the thicknesses T1 of the substrate 11 and T3 of the upper substrate layer 14 are determined from manufacturing specifications; typically, T3 is larger than T1.
• the substrate conductive material 23 between the substrate 11 and the upper substrate layer 14 has been patterned to obtain a substrate conductive area 24 for the bottom electrode and a substrate conductive area 25 for the top electrode 25 (shown as dashed lines in Figure 29A).
• the substrate conductive material 23 is patterned during the fabrication of the assembly 10 using lithography techniques such as masking and etching like those used in a PCB manufacturing facility.
• the via 21 makes a direct electrical connection between the substrate conductive area 24 for the bottom electrode on the top side 12 and the annular ring 22 on the bottom side 13.
• FIG. 30A top view
• Figure 30B cross-sectional view taken along line X-X’ of Figure 30A
• a portion of the assembly 10 is removed by mechanical means (such as a grinder or polishing machine) or by chemical means (such as a solvent that etches both the upper substrate layer 14 and the substrate conductive material 23).
• mechanical means such as a grinder or polishing machine
• chemical means such as a solvent that etches both the upper substrate layer 14 and the substrate conductive material 23.
• the thickness TCP of the polished substrate conductive material 33 is smaller than the original thickness TC of the substrate conductive material 23.
• the result is an assembly 10 with a polished substrate conductive material 33 and a polished upper substrate layer 36 with a surface roughness of a few nanometers or lower. The surface roughness depends on the removal mechanism.
• the thickness of the polished substrate conductive material 33 and the polished upper substrate layer 36 have the same thickness TCP. Fabrication in accordance with this depicted embodiments can be done without the deposition of a planarization layer 40, which is discussed above in respect of Figure 21 A. Maintaining a flat and level surface is important for the upcoming fabrication steps for crating polyCMUT cells and eventually polyCMUT elements 201 and polyCMUT arrays 204. A portion of the PCB itself (i.e. , the polished upper substrate layer 36) between a polished conductive area that acts as the bottom electrode 34 and a polished conductive area 35 for the top electrode is co-planar with the bottom electrode 34 and the conductive area 35.
• This first polymer layer 110 can be deposited using, in some embodiments, lithography coating techniques (such as a spin coater).
• the typical thickness of this first polymer layer 110 ranges from, in some embodiments, a few tens of nanometers to a few micrometers (typically 700 nm).
• the thickness of this first polymer layer 110 is tailored to a specific design for ultrasound transducers and to be able to withstand normal operational voltages between 10 V and 100 V.
• the first polymer layer 110 is patterned (in geometrical shapes) to form a uniform layer with some first polymer via holes 111.
• the first polymer via holes 111 create a direct connection to some portions of the sacrificial etch channels 106 from the exterior.
• a second conductive material 115 is deposited on top of the assembly 10, covering portions of the first polymer layer 110 and some portions of the polished conductive area 35 for the top electrode.
• the second conductive material 115 can be patterned using lithography techniques such as lift-off or etching a blanket layer of conductive material.
• the second conductive material 115 may be, in some embodiments, a layer of titanium, followed by a layer of gold.
• This second conductive material 115 can be deposited using, in some embodiments, physical vapor deposition systems (such as a sputtering system) for a conformal covering.
• the typical thickness of this second conductive material 115 is, in some embodiments, a few to several tens of nanometers (typically 100 nm).
• the second conductive material 115 is patterned (in geometrical shapes) to form a top electrode area 116 and a top electrode interconnect 117.
• the second conductive material 115 is patterned in such a way to avoid any overlap with the first polymer via holes 111.
• the second conductive material 115 is patterned in such a way to avoid any electrical contact with the polished conductive area that acts as the bottom electrode 34; otherwise, it would create short circuits between the bottom and top electrodes of a polyCMUT cell.
• the second conductive material 115 is patterned in such a way to maintain an electrical contact with the polished conductive area 35 for the top electrode; therefore, an electrical connection is formed between the second conductive material 115 and only one of the vias 21 , which in Figure 25B is the via 21 on the right-hand side.
• the top electrode interconnect 117 is used to create an electrical connection with adjacent polyCMUT cells (not shown), and to allow the creation of polyCMUT elements 201. There exists at least one connection point between the top electrode interconnect 117 and the polished conductive area 35 for the top electrode.
• the second conductive layer 115 will become the top electrode in a polyCMUT cell.
• a second polymer layer 120 is deposited on top of the assembly 10, covering portions of the first polymer layer 110 and the second conductive material 115.
• This second polymer layer 120 can be, in some embodiments, a UV photosensitive material such as SU-8 photoresist.
• the second polymer layer 120 can be patterned directly using a UV exposure system then patterned with, for example, wet etching using SU-8 developer.
• This second polymer layer 120 can also be patterned using lithography techniques such as lift-off or etching a blanket layer of polymer.
• This second polymer layer 120 can be deposited using, in some embodiments, lithography coating techniques (such as a spin coater).
• the typical thickness of this second polymer layer 120 ranges from, in some embodiments, a few hundreds of nanometers to a few tens of micrometers (typically 5 urn).
• the thickness of this second polymer layer 120 is tailored to a specific design for ultrasound transducers and to be able to withstand normal operational voltages, between 10 V and 100 V.
• the second polymer layer 120 is patterned (in geometrical shapes) to form a second polymer membrane area 121 that avoids sealing or plugging the first polymer via holes 111.
• This second polymer layer 120 can also uniformly cover the entire assembly 10 (not shown in Figure 34A or Figure 34B) except in the areas where the first polymer via holes 111 are located.
• the purpose of this second polymer layer 120 is to increase the overall thickness of the membrane in a polyCMUT cell and to be able to reach a desired frequency between 1 MHz and 10 MHz.
• the sacrificial membrane area 107 and the sacrificial etch channels 106 appear as dashed lines in Figure 34A.
• the sacrificial material 105 (including the sacrificial etch channels 106 and the sacrificial membrane area 107) is etched, dissolved, or otherwise removed (e.g., mechanically).
• the sacrificial material can be removed with, in some embodiments, wet etching using solvents or dry etching using gases.
• the assembly 10 is transferred into the chamber of a critical point drier system (CPD), where liquid carbon dioxide (CO2) enters the chamber at high pressures and replaces the IPA; then this liquid CO2 transforms into gaseous CO2 when the pressure in the chamber is gradually reduced to atmospheric pressure.
• CPD critical point drier system
• CO2 liquid carbon dioxide
• the areas where the sacrificial material 105 used to be are replaced by an air area 125.
• the air area 125 allows the membrane in a polyCMUT cell to move, but it may not be suitable for water-coupled operations due to the presence of the first polymer via holes 111.
• an encapsulation material 130 is uniformly coated over the entire assembly 10, thereby covering portions of the polished upper substrate layer 36, the polished substrate conductive material 33, the first polymer layer 110, the second conductive material 115, and the second polymer layer 120.
• the encapsulation material 130 may be, in some embodiments, Parylene C.
• the encapsulation material 130 can be deposited using a low-pressure chamber, which may operate as a vacuum.
• the encapsulation material 130 conformally coats the top side of the assembly 10, and it gradually accumulates in the inner walls of the sacrificial etch channels 106 until they are plugged and thereby sealed.
• the thickness of this encapsulation material 130 is in at least some embodiments at least half of the thickness of the sacrificial material 105 to have a proper seal of the sacrificial etch channels 106.
• the bottom side 13 of the assembly 10 can be protected (using for instance peelable tape) to prevent the encapsulation material 130 from covering the annular rings 22.
• the areas where the air area 125 were are replaced by a vacuum area 131 .
• the vacuum area 131 allows the membrane in a polyCMUT cell to move in liquid-coupled applications, such as biomedical ultrasound examination.
• the vacuum area 131 becomes the sealed cavity in a polyCMUT cell.
• the solvents used for wet etching in the first through fourth embodiments depicted in Figures 1A to 37B are selected to be chemically compatible with the substrate 11 and the other materials deposited on the substrate, such as the various polymer layers 110,120 and the conductive material 115 used for electrodes. I.e. , the solvent is selected to etch away the sacrificial material 105 without dissolving or damaging the substrate 11 and those other materials.
• Example suitable solvents used for wet etching comprise SU-8 developer of which the predominant ingredient is 1- methoxy-2-propanol acetate and tetramethylammonium hydroxide (TMAH).
• TMAH tetramethylammonium hydroxide
• Other suitable solvents may comprise 1 -methoxy-2-propanol acetate alone or when part of another composition that is not SU-8 developer, acetone, and isopropanol (IPA).
• an encapsulation material 130 is uniformly coated over the entire assembly 10, thereby covering portions of the polished upper substrate layer 36, the polished substrate conductive material 33, the silicon-based material 110, and the second conductive material 115.
• the encapsulation material 130 may be, in some embodiments, silicon nitride, silicon dioxide, or polysilicon. In some embodiments, the encapsulation material 130 can be deposited using a low- pressure chamber that may operate as a vacuum.
• FIG. 39A and Figure 39B there are respectively shown top isometric and top plan views of a 3D visualization of a polyCMUT array 204 in the form of a polyCMUT linear array 202 fabricated on a substrate 11.
• the polyCMUT linear array 202 is one of the multiple arrays 202 manufactured from the wafer substrate 210 of Figures 38A and 38B.
• the polyCMUT linear array 202 is comprised of 128 polyCMUT elements 201 stacked on each other along the length of the array 202, with each of the polyCMUT elements comprising around 300 polyCMUT cells (not individually shown).
• the polyCMUT elements are respectively electrically connected to independent vias 21 (not individually shown) on the substrate 11 that extend through to the substrate’s 11 bottom side 13.
• An electrical contact assembly 230 is mounted on the bottom side 13 of the substrate 11 and is electrically connected to the vias 21.
• the 128 polyCMUT elements are respectively electrically coupled to 128 of the vias 21 .
• the polyCMUT linear array 202 is fabricated on top of a polished substrate 30 according to the first embodiment described above and depicted in accordance with Figures 1 A to 9B.
• FIG. 40A and Figure 40B there are respectively shown isometric and bottom views of a 3D visualization of the bottom side 13 of the polyCMUT linear array 202 of Figures 39A and 39B.
• the polyCMUT linear array 202 being on the top side of the substrate 11 , is not shown.
• the electrical contact assembly 230 has several dozen independent electrical contact assembly connections 231. Each of these electrical contact assembly connections 231 connects to a via 21 and accordingly is also electrically connected to the second conductive material 115 of their corresponding polyCMUT elements 201 (not shown).
• a top isometric view and a bottom isometric view of a polyCMUT array 204 are respectively shown.
• a polyCMUT matrix array 203 comprising hundreds of polyCMUT elements 201 arranged in several dozen rows and columns is fabricated on top of a polished substrate 30.
• the polished substrate 30 can comprise one or more layers of substrate conductive material 23 that allow the proper routing and distribution of the substrate conductive contact areas 26. For instance, printed circuit boards may have two, four, six, or more layers interconnected by inner vias.
• a polyCMUT matrix array 203 comprising hundreds of polyCMUT elements 201 in several dozen rows and columns along the X and Y axes is fabricated on top of a polished substrate 30.
• the polyCMUT matrix array 203 has independent connections for the top and bottom electrodes of the polyCMUT cells in some embodiments (not shown).
• the polyCMUT matrix array 203 has independent connections for the top electrode and a common electrical connection for the bottom electrode (not shown) in some embodiments.
• the substrate conductive contact area 26 can be split into two or more substrate conductive contact tracks 27 (not shown) to permit mounting of two or more electronic components 241 ; for instance, an array comprising a resistor and a capacitor may be mounted to respective substrate conductive contact tracks 27 to create a “bias-tee” circuit to add DC and AC voltages.
• FIG. 47 an exploded view of a transducer assembly 250 is shown. It comprises an electrical contact assembly 230.
• the electrical contact assembly 230 comprises a plurality of electrical contact assembly connections 231 , and is attached (e.g., adhered or soldered) to the polyCMUT array 204.
• This polyCMUT array 204 can be either a polyCMUT linear array 202 or a polyCMUT matrix array 203 (not shown).
• An acoustic lens 240 is also attached (e.g., adhered or casted) to the top surface of the polyCMUT array 204. The purpose of this acoustic lens 240 is to generate a concentrated ultrasound beam.
• this acoustic lens 240 can be casted directly on top of the polyCMUT array 204 using a mold (not shown) or, in other embodiments, can be casted on a separate mold and then glued in place using an adhesive compatible with the material of the acoustic lens 240 and the polyCMUT array 204.
• FIGS 48A, 48B, and 48C three cross-sectional views of a polyCMUT linear array 202 with different thicknesses (T4, T5, and T6) of the substrate 11 are illustrated, and the individual polyCMUT elements 201 can be seen on the top sides thereof.
• Thicker substrates (T4) lead to larger radius of curvature (R4) when the polyCMUT linear arrays 202 are bent around the X axis (not shown, axis coming out of the page) such that T4 > T5 > T6 and R4 > R5 > R6.
• some substrates 11 having vias 21 can be fabricated in thin substrates (typically 0.4 mm thick) that lead to a semi-rigid/bendable polyCMUT linear array 202.
• FIG 49A a picture of a wafer substrate 210 fabricated in a printed circuit board manufacturing facility is illustrated.
• the wafer substrate front side 211 has several hundred exposed vias 21 and annular rings 22 (too small to be individually identified in Figure 49A).
• the positions of these vias 21 and annular rings 22 match the position of polyCMUTs arrays 204 to be fabricated on this wafer substrate front side 211 .
• the detailed view of area A is shown in Figure 51 .
• FIG 49B a picture of a wafer substrate 210 fabricated in a printed circuit board manufacturing facility is shown.
• the wafer substrate back side 212 has several hundred electrical contact pads that have electrical individual access to the vias 21 on the wafer substrate front side 211. These electrical contact pads allow the soldering of electrical contact assemblies 230 (such as headers or receptacles used in PCB industry) for the interaction with external electronic equipment such as ultrasound pulsers and amplifiers.
• the detailed view of area B is shown in Figure 50A.
• FIG. 50B the detailed view of area C that appears in Figure 50A is illustrated. It corresponds to the microscopic view of the wafer substrate back side 212.
• the annular rings 22 are electrically connected to the substrate conductive contact areas 26 through a plurality of substrate conductive tracks 27 patterned using the same substrate conductive material 23.
• FIG 51 the detailed view of area A that appears in Figure 49A is shown. It corresponds to the microscopic view of the wafer substrate front side 211 .
• a polished substrate 30 was achieved by using a mechanical grinding and polishing system, alongside with polishing chemicals and abrasive agents. Some polished vias 31 are also shown; these polished vias will be used to connect to the top electrodes in individual polyCMUT elements 201 that will be fabricated on top (not shown).
• the polishing system planarized the wafer substrate front side 211 uniformly until a surface roughness of a few nm were achieved.
• FIG 52A the surface roughness measurement of the wafer substrate front side 211 along a distance L (shown in Figure 51 ) before a polishing stage is shown.
• the average surface roughness is 2.092 urn. This measurement was acquired using a DektakXTTM needle profilometer.
• FIG 52B the surface roughness measurement of the wafer substrate front side 211 along a distance L (shown in Figure 51 ) after a polishing stage is illustrated.
• the average surface roughness is 52.805 nm. This measurement was acquired using a DektakXTTM needle profilometer.
• FIG. 53A a picture of a wafer substrate 210 with several polyCMUT arrays 204 fabricated on top after the wafer substrate 210 was polished in a grinding/lapping machine is shown.
• FIG. 53B a picture of a polyCMUT group of arrays 205 is illustrated.
• the polyCMUT arrays 204 were separated using a dicing saw. Just a few of the polyCMUT linear arrays 202 are shown in this picture.
• FIG 54A a picture of a polyCMUT linear array 202 fabricated on a substrate 11 (also shown in Figure 53B) is shown.
• the polyCMUT linear array 202 is comprised of 128 polyCMUT elements 201 electrically connected to independent vias 21 (too small to be individually signaled in Figure 54A) on the substrate 11 .
• An electrical contact assembly 230 is mounted on the bottom side 13 of the substrate 11 .
• the polyCMUT linear array 202 was fabricated on top of a polished substrate 30 according to the first embodiment described above.
• FIG. 54B a picture of a polyCMUT linear array 202 mounted on an electrical test circuit board 233 is shown.
• the electrical contact assembly 230 mounted on the back side of the polyCMUT linear array 202 interfaces with an electrical contact mating connection 232 that is integrated into the electrical test circuit board 233.
• This electrical test circuit board 233 is used to send and receive electrical signals to and from the polyCMUT linear array 202.
• FIG. 55B a Fast-Fourier transform (FFT) signal corresponding to the time-domain signal shown in Figure 55A is shown.
• FFT Fast-Fourier transform
• FIG 56A the computer design of a wafer substrate 210 to be fabricated in a printed circuit board manufacturing facility is illustrated.
• the polished substrate conductive material 33 and polished conductive areas 35 for the top electrodes are shown in the inset.
• the polished substrate conductive material 33 comprises more than 95% of the total area of the wafer substrate 210.
• FIG 59A a picture of a needle profilometer with the substrate from Figure 57B is shown.
• the profilometer is used to measure the surface roughness of the polished conductive area that acts as the bottom electrodes 34.
• FIG. 59B the profilometer measurement along the longitudinal axis (refer to line Y-Y’ from Figure 57B) of the substrate from Figure 59A is shown.
• the 80 mm-long measurement shows the curvature or “bow” of the substrate alongside with some surface roughness parameters.
• FIG 59C the profilometer measurement along the transverse axis (refer to line X-X’ from Figure 58B) of the substrate from Figure 59A is shown.
• the 1.6 mm-long measurement shows the surface profile of the polished conductive area for top electrode 35 and the polished planarization layer 50.
• FIG. 60A the profilometer measurement along the X and Y axes of a standard 100mm prime-grade silicon wafer with an oxide layer is shown. This was performed to measure the curvature or “bow” of a typical silicon wafer used in microfabrication. The wafer bow is between 20 urn and 30 urn.
• FIG. 60B the measurement data along the X and Y axes of the substrate from Figure 59A is shown.
• the wafer bow is between 30 urn and 40 urn, which is very comparable to the bow of a standard silicon wafer. This means that the wafer substrate 210 is compatible to be processed in standard microfabrication equipment.
• FIG. 61 A the profilometer measurement along the center region of a standard 100mm prime-grade silicon wafer with an oxide layer is shown. This was performed to measure the surface roughness of a typical silicon wafer used in microfabrication. The wafer roughness is between 20 nm to 40 nm.
• FIG. 61 B the profilometer measurement along the center region of the substrate from Figure 59A is shown.
• the surface roughness is between 0 nm to 30 nm, very comparable to surface roughness of a standard silicon wafer. This means that the wafer substrate 210 is suitable for processing using standard microfabrication equipment and can be used for the direct fabrication of polyCMUT arrays 205.
• FIG. 62A the profilometer measurement along the polished planarization layer 50 of the substrate from Figure 59A is shown.
• the surface roughness is between -40 nm to 20 nm. This means that the first polymer layer 110 and the top electrode interconnect 117 can be patterned directly, as discussed in respect of Figure 25B.
• Figure 62B the profilometer measurement 100um along the region of the substrate from Figure 59A is shown. The surface roughness is between -5 nm to 5 nm.
• any ringing effects are located outside of the frequency range of interest.
• the acoustic signal shown in Figure 55B has a center frequency of 7.4 MHz; the ringing effects in this substrate would appear around 1 .68 MHz for a substrate with a thickness of 1 mm. This frequency lies outside of the -6 dB lower frequency (around 4.0 MHz).
• Poly-CMUTs made according to at least some of the embodiments here are advantageous over traditional silicon-based CMUTs.
• the total manufacturing cost of poly-CMUTs can in many instances be well below US$100.
• Minimal and inexpensive manufacturing equipment can be used for poly-CMUTs (e.g., mask aligner, metal evaporator, critical point drier). This is an advantage over silicon- based CMUTs, where expensive and cumbersome equipment is needed.
• the poly- CMUT arrays of at least some embodiments also possess flexibility as shown in Figures 48A, 48B, and 48C, which show bendability in either one (x) or two (x, y) dimensions.
• Polymer-based CMUTs can be manufactured on flexible substrates for wearable applications; as discussed above, PCBs may be flexible or rigid. This cannot be done with silicon-based CMUTs, including the silicon-based CMUT embodiment of Figures 37A and 37B, since they need rigid substrates. Similarly, flexible substrates cannot be used when fabricating CMUTs using ceramic piezoelectric materials.
• Another advantage of the fabrication approach described in respect of the embodiments herein is that a multi-layer fabrication approach allows the electrical shielding of signal cables. For example, individual routing from CMUT elements can be protected between two ground planes to minimize electromagnetic interference (EMI).
• EMI electromagnetic interference
• the epoxy resins used in the fabrication of PCBs such as FR4 have a low X-ray mass absorption coefficient. Therefore, the substrate can be considered X-ray transparent.
• FIG. 64A and 64B the cross-sectional front view and the cross-sectional side view respectively of a probe assembly 251 is shown.
• a polyCMUT array 204 with an acoustic lens 240 and an electrical contact assembly 230 is mounted on an existing probe case 252 containing an electrical contact mating connection 232 that connects to an electrical interface board 234 containing a plurality of electronic components 241 (e.g., capacitors, inductors, resistors, etc.).
• An advantage of the fabrication methodology described in any of the embodiments herein is that that the assembly or repair of ultrasound probes is greatly simplified.
• the fabrication methodology avoids the wirebonding, encapsulation, and lens casting procedures of traditional piezoelectric and silicon-based transducers.
• a pressure higher than atmospheric pressure (not shown) will cause the polyCMUT array 204 to deflect outwards away from the probe case.
• Many or all of the polyCMUT elements in the polyCMUT array 204 may operate simultaneously to generate individual ultrasound waves 270.
• an unfocused ultrasound beam 271 or a focused ultrasound beam 272 can be obtained with a variable focal point 273. In some embodiments, this may be beneficial for ultrasound probes dedicated to therapeutic applications, in which a physically focused ultrasound beam 272 is desired over an electronically-focused ultrasound beam to deliver relatively high acoustic energy for an accelerated tissue healing.
• a probe assembly 251 comprised of a probe case 252 in which a polyCMUT array 204 is assembled to become an ultrasound probe is shown.
• the probe case 252 has a deflection mechanism 262 that is attached to the back side of the polyCMUT array 204.
• This deflection mechanism causes a vertical displacement 263 (D1 , D2, and D3) that induces a deflection of the polyCMUT array 204.
• the polyCMUT array 204 is thin enough to be deflected by the deflection mechanism 262.
• Many or all of the polyCMUT elements 201 in the polyCMUT array 204 can operate simultaneously to generate individual ultrasound waves 270.
• an unfocused ultrasound beam 271 or a focused ultrasound beam 272 can be obtained with a variable focal point 273. In some embodiments, this may be beneficial for ultrasound probes dedicated for therapeutic applications, where a physically focused ultrasound beam 272 is desired over an electronically-focused ultrasound beam to deliver relatively high acoustic energy for accelerated tissue healing.
• a reference to a value being “about” or “approximately” a quantity means that value is within +/- 10% of that quantity unless the context indicates otherwise.
• connection and variants of it such as “connected”, “connects”, and “connecting” as used in this description are intended to include indirect and direct connections unless otherwise indicated. For example, if a first device is connected to a second device, that coupling may be through a direct connection or through an indirect connection via other devices and connections. Similarly, if the first device is communicatively connected to the second device, communication may be through a direct connection or through an indirect connection via other devices and connections.
• phrases such as “at least one of A, B, and C”, “at least one of A, B, or C”, “one or more of A, B, and C”, and “A, B, and/or C” are intended to include both a single item from the enumerated list of items (i.e., only A, only B, or only C) and multiple items from the list (i.e., A and B, B and C, A and C, and A, B, and C). Accordingly, the phrases “at least one of”, “one or more of”, and similar phrases when used in conjunction with a list are not meant to require that each item of the list be present, although each item of the list may be present.

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Transducers For Ultrasonic Waves (AREA)
• Physics & Mathematics (AREA)
• Acoustics & Sound (AREA)
• Signal Processing (AREA)
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• Production Of Multi-Layered Print Wiring Board (AREA)

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• 2023
  • 2023-08-30 CN CN202380075454.2A patent/CN120112478A/zh active Pending
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