EP4449293A4 - Placement automatisé de niveau de transistor destiné à la conception de circuits intégrés - Google Patents

Placement automatisé de niveau de transistor destiné à la conception de circuits intégrés

Info

Publication number
EP4449293A4
EP4449293A4 EP23756765.6A EP23756765A EP4449293A4 EP 4449293 A4 EP4449293 A4 EP 4449293A4 EP 23756765 A EP23756765 A EP 23756765A EP 4449293 A4 EP4449293 A4 EP 4449293A4
Authority
EP
European Patent Office
Prior art keywords
design
integrated circuits
transistor level
automated placement
automated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP23756765.6A
Other languages
German (de)
English (en)
Other versions
EP4449293A1 (fr
Inventor
Xiaoqing Xu
Dino Ruic
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GDM Holding LLC
Original Assignee
X Development LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by X Development LLC filed Critical X Development LLC
Publication of EP4449293A1 publication Critical patent/EP4449293A1/fr
Publication of EP4449293A4 publication Critical patent/EP4449293A4/fr
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
EP23756765.6A 2022-02-16 2023-02-06 Placement automatisé de niveau de transistor destiné à la conception de circuits intégrés Pending EP4449293A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202263310675P 2022-02-16 2022-02-16
US17/957,621 US12602532B2 (en) 2022-02-16 2022-09-30 Automated transistor-level placement for design of integrated circuits
PCT/US2023/012431 WO2023158565A1 (fr) 2022-02-16 2023-02-06 Placement automatisé de niveau de transistor destiné à la conception de circuits intégrés

Publications (2)

Publication Number Publication Date
EP4449293A1 EP4449293A1 (fr) 2024-10-23
EP4449293A4 true EP4449293A4 (fr) 2025-12-03

Family

ID=87558719

Family Applications (1)

Application Number Title Priority Date Filing Date
EP23756765.6A Pending EP4449293A4 (fr) 2022-02-16 2023-02-06 Placement automatisé de niveau de transistor destiné à la conception de circuits intégrés

Country Status (6)

Country Link
US (1) US12602532B2 (fr)
EP (1) EP4449293A4 (fr)
JP (2) JP7656150B2 (fr)
KR (1) KR20240125056A (fr)
CN (1) CN118661174A (fr)
WO (1) WO2023158565A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12169677B2 (en) * 2020-07-23 2024-12-17 Nvidia Corp. Standard cell layout generation with applied artificial intelligence
CN119886037B (zh) * 2025-03-26 2025-07-08 华中科技大学 一种标准单元中晶体管的自动布局方法、设备及存储介质
CN120524901B (zh) * 2025-05-13 2026-01-09 北京知识产权运营管理有限公司 一种面向多行标准单元的层次化晶体管布局方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5701255A (en) 1994-09-14 1997-12-23 Matsushita Electric Industrial Co., Ltd. Cell generation method and cell generation system
JPH08236732A (ja) * 1995-02-28 1996-09-13 Mitsubishi Electric Corp トランジスタ配置方法
TW330342B (en) 1995-11-21 1998-04-21 Matsushita Electric Industrial Co Ltd Compacting method, compacting assembly, layout method, layout assembly, rough layout method and assembly
JP3014646B2 (ja) 1995-11-21 2000-02-28 松下電器産業株式会社 配線方法及びコンパクション方法
JP3078739B2 (ja) * 1995-12-26 2000-08-21 松下電器産業株式会社 トランジスタ概略配置方法
US5984510A (en) * 1996-11-01 1999-11-16 Motorola Inc. Automatic synthesis of standard cell layouts
US6209123B1 (en) * 1996-11-01 2001-03-27 Motorola, Inc. Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors
US5987086A (en) * 1996-11-01 1999-11-16 Motorola Inc. Automatic layout standard cell routing
US6006024A (en) * 1996-11-01 1999-12-21 Motorola, Inc. Method of routing an integrated circuit
US6239607B1 (en) * 1998-10-16 2001-05-29 Agilent Technologies, Inc. Simulation-based method for estimating leakage currents in defect-free integrated circuits
JP2000195958A (ja) 1998-12-24 2000-07-14 Sharp Corp レイアウト生成装置、レイアウト生成方法、レイアウト生成プログラムを記録した媒体、および基本セルのデータを記録した媒体
US7523429B2 (en) 2004-02-20 2009-04-21 Takumi Technology Corporation System for designing integrated circuits with enhanced manufacturability
US8018503B2 (en) 2007-02-19 2011-09-13 Nikon Corporation Imaging apparatus with multiple timing-adjusting parts
JP5046976B2 (ja) 2008-01-29 2012-10-10 株式会社オービックビジネスコンサルタント 情報処理システム、更新サーバ装置、およびユーザ管理装置
JP5487563B2 (ja) 2008-06-19 2014-05-07 カシオ計算機株式会社 電子機器
US8438530B2 (en) * 2009-07-22 2013-05-07 Synopsys, Inc. Connection navigation in electronic design automation
US8793636B2 (en) * 2011-04-14 2014-07-29 International Business Machines Corporation Placement of structured nets
US9652580B2 (en) 2014-07-23 2017-05-16 Samsung Electronics Co., Ltd. Integrated circuit layout design system and method
US10318656B2 (en) 2016-04-26 2019-06-11 The Boeing Company Systems and methods for optimizing component placement in a battery design
CN108287932B (zh) 2017-01-10 2021-09-21 上海复旦微电子集团股份有限公司 一种基于解析方法的总体fpga自动化布局方法
US11392748B2 (en) 2018-09-28 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit design using fuzzy machine learning
US11537773B2 (en) 2020-05-18 2022-12-27 Taiwan Semiconductor Manufacturing Company Ltd. Systems and methods for integrated circuit layout
CN111767689A (zh) 2020-05-20 2020-10-13 西南科技大学 一种基于图形处理的三维集成电路布局方法

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
"Vlsi-Soc: From Systems To Silicon", vol. 240, 17 October 2005, article LAZZARI CRISTIANO ET AL: "A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming", pages: 331 - 344, XP093328817, DOI: 10.1007/978-0-387-73661-7_21 *
HSU CHEN-HAO ET AL: "TransPlace: A Scalable Transistor-Level Placer for VLSI Beyond Standard-Cell-Based Design", PROCEEDINGS OF THE 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 22 January 2024 (2024-01-22), pages 312 - 318, XP034577097, DOI: 10.1109/ASP-DAC58780.2024.10473978 *
MICHAEL A RIEPE ET AL: "Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis", PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN, 12 April 1999 (1999-04-12), pages 74 - 81, XP058322434, DOI: 10.1145/299996.300028 *
PRAKASH GOPALAKRISHNAN ET AL: "Direct transistor-level layout for digital blocks", PROCEEDINGS OF THE IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, 4 November 2001 (2001-11-04), pages 577 - 584, XP058305623, DOI: 10.1109/ICCAD.2001.968713 *
See also references of WO2023158565A1 *

Also Published As

Publication number Publication date
KR20240125056A (ko) 2024-08-19
WO2023158565A1 (fr) 2023-08-24
US20230259689A1 (en) 2023-08-17
CN118661174A (zh) 2024-09-17
JP2025508413A (ja) 2025-03-26
EP4449293A1 (fr) 2024-10-23
US12602532B2 (en) 2026-04-14
JP7656150B2 (ja) 2025-04-02
JP2025108442A (ja) 2025-07-23

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Owner name: GDM HOLDING LLC