EP4392893A4 - Automatisierte verifikation integrierter schaltungen - Google Patents

Automatisierte verifikation integrierter schaltungen

Info

Publication number
EP4392893A4
EP4392893A4 EP22862000.1A EP22862000A EP4392893A4 EP 4392893 A4 EP4392893 A4 EP 4392893A4 EP 22862000 A EP22862000 A EP 22862000A EP 4392893 A4 EP4392893 A4 EP 4392893A4
Authority
EP
European Patent Office
Prior art keywords
integrated circuits
automated verification
verification
automated
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP22862000.1A
Other languages
English (en)
French (fr)
Other versions
EP4392893A2 (de
Inventor
Calum Macrae
Richard Philpott
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Celera Inc
Original Assignee
Celera Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Celera Inc filed Critical Celera Inc
Priority claimed from PCT/US2022/041264 external-priority patent/WO2023028080A2/en
Publication of EP4392893A2 publication Critical patent/EP4392893A2/de
Publication of EP4392893A4 publication Critical patent/EP4392893A4/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/10—Numerical modelling

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)
EP22862000.1A 2021-08-24 2022-08-23 Automatisierte verifikation integrierter schaltungen Pending EP4392893A4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202163236589P 2021-08-24 2021-08-24
PCT/US2022/041264 WO2023028080A2 (en) 2021-08-24 2022-08-23 Automated verification of integrated circuits

Publications (2)

Publication Number Publication Date
EP4392893A2 EP4392893A2 (de) 2024-07-03
EP4392893A4 true EP4392893A4 (de) 2025-07-09

Family

ID=91370894

Family Applications (1)

Application Number Title Priority Date Filing Date
EP22862000.1A Pending EP4392893A4 (de) 2021-08-24 2022-08-23 Automatisierte verifikation integrierter schaltungen

Country Status (1)

Country Link
EP (1) EP4392893A4 (de)

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
OLIVADESE SALVATORE BERNARDO ET AL: "Parameterized and DC-Compliant Small-Signal Macromodels of RF Circuit Blocks", IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, vol. 5, no. 4, 1 April 2015 (2015-04-01), pages 508 - 522, XP011578949, DOI: 10.1109/TCPMT.2015.2403071 *
ROB A RUTENBAR ET AL: "Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs", PROCEEDINGS OF THE IEEE, vol. 95, no. 3, 1 March 2007 (2007-03-01), pages 640 - 669, XP011179944, DOI: 10.1109/JPROC.2006.889371 *

Also Published As

Publication number Publication date
EP4392893A2 (de) 2024-07-03

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Ipc: G06F 111/10 20200101ALN20250605BHEP

Ipc: G06F 30/398 20200101ALI20250605BHEP

Ipc: G06F 30/367 20200101AFI20250605BHEP