Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/36—Circuit design at the analogue level
  • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level
  • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2111/00—Details relating to CAD techniques
  • G06F2111/10—Numerical modelling

Definitions

• the present disclosure pertains to electronic circuits, and in particular, to techniques for improved test and verification of electronic circuits.
• Circuit schematics may include each transistor in the circuit together with connections between the transistors.
• the schematics can be used to simulate how the electronic circuit will operate to ensure proper functionality.
• the transistors are laid out as geometric shapes.
• test systems are developed to test the fabricated chip.
• Fig. 4A illustrates a functional circuit component including a test mode according to an embodiment.
• transistor level schematics are configured based on parameter values and test routines are automatically generated based on the parameter values to verify the transistor level schematics.
• test routines are converted to test cells to verify transistor level schematics.
• the system includes a test mode, where additional circuitry may be included in the transistor level schematics for testing the circuitry.
• Test routines may include tests that interface with the added test circuitry in the schematics, for example to test one or more circuit modules, for example.
• the test routines may further be converted into programs executable on automated test equipment to test physical semiconductor circuits, for example.
• Fig. 1A illustrates automated verification according to one example embodiment.
• Generator software system (“Generator”) 102 may receive information specifying a plurality of circuit specification parameters 104 corresponding to at least one analog functional circuit component 101 to be created (e.g., into a transistor level schematic or a layout, or both).
• generator software 102 includes a circuit generator component 190 for producing transistor level circuits and a test generator component 191 for producing test routines (sometimes referred to as “test macros”).
• test macros sometimes referred to as “test macros”.
• circuit generator 190 and test generator 191 may be part of the same or different software systems. Generating circuits is described in more detail in U.S.
• Generator 102 may process the parameters and generate test routines. For example, generator 102 may select a subset of test routines from a plurality of test routines 110-112 for analog functional circuit component 101. Selection of a subset test routines may be based on (among other things) the parameters (e.g., the same parameters used to select sub-circuits for the functional circuit component), for example. Accordingly, functional circuit components 101 with different parameterized configurations may be automatically tested using different subsets of test routines which are selected based on the same parameters.
• the parameters 104 for functional circuit component 101 may have different values corresponding to different configurations of the transistor level schematic for functional circuit component 101 to be generated.
• a first set of values for parameters 104 (e.g., params_l) may result in generator 102 selecting a first subset of test routines 120 from the plurality of test routines 110-112.
• the selected test routines may be used to test one transistor level embodiment of functional circuit component 101 configured using the first set of values for parameters 104, such as functional circuit component (params_l) 130, for example.
• a second set of values for parameters 104 e.g., params_2
• test routines 150 may be used to automatically generate a verification system for a transistor level schematic.
• Fig. IB illustrates an example of how test routines may be applied to transistor level schematics of parameterized functional circuit components.
• test routines 150 are received by a code converter (or translator) 151.
• the test routines 150 may have been selected based on a type of functional circuit component and particular parameter values (“param_i”), for example.
• Examples of different types of functional circuit components may include amplifiers, buffers, comparators, oscillators, power switches, resistor dividers, feedback dividers, voltage to current converters, current sources, current generators, current mirrors, and a wide range of other analog/mixed signal circuit components, for example.
• Different functional circuit component types may have different groups of test routines to select from.
• functional circuit component A may have corresponding parameters 204a for selecting subsets of test routines from test set A 210, which may include test routines 211-213.
• functional circuit component B may have corresponding parameters 204b for selecting subsets of test routines from test set B 215, which may include test routines 216-218, for example.
• test routines 221 are selected from test set A 210 when generator 203 receives different values for parameters A 204a (e.g., denoted here as Set A, params_N) for functional circuit component A 201.
• test routines 221 may be used to test another embodiment of functional circuit component A 231 having parameters “param_N,” for example.
• test routines 241 are selected from test set B 215 when generator 203 receives different values for parameters B 204b (e.g., denoted here as Set B, params_M) for component B 202.
• Test routines 241 may be used to test another embodiment of functional circuit component B 251 having parameters “params_M,” for example.
• Figs. 2B-C illustrate one advantage of some embodiments.
• a first set of parameter values for a plurality of functional circuit components are used to generate an analog circuit schematic (and chip) 290 including functional circuit components 270-272, for example, each being generated based on particular parameter values.
• the parameter values are also used to generate a custom test script 291 comprising customized test routines 260-263 selected based on the parameter values (and possibly other criteria).
• Fig. 5B illustrates an example transistor level schematic EDA environment including test cell 520 and a composite circuit 500 comprising circuit modules 540a-c.
• DFT has been turned on for components 501a-c.
• generator software selects sub-circuit schematics and DFT sub-circuit schematics to produce circuit modules 540a-c.
• the same non-DFT subcircuits schematics may be used to produce circuits 541a-c as above in Fig. 5A.
• test cell 520 circuit modules 541a-c, and switches 510-518 are transistor level schematics (e.g., in an EDA environment, such as Cadence® or Mentor®). Accordingly, the analog voltages and currents to and from the APs, as well as the voltages and currents in the circuit modules may be simulated (as mentioned above in connection with Fig. 3A).
• one or more of the circuit modules may be independently turned on and off (e.g., shutdown using an enable pin).
• digital signals 650 may cause digital controller 612 to shutdown circuit modules 610 and 611 (and any other circuits drawing current from Vdd_sys) during a supply current test, for example, so that only circuit module 601 is drawing current during the test.
• Fig. 8 illustrates a verification system for parameterized functional circuit components and corresponding circuit modules according to another embodiment.
• a user has specified N (an integer) functional circuit components 802-804 in a user interface (UI) 801 with corresponding parameter values 805-807, respectively, and turned DFT on for each one. While the components are illustrated here as in series, it is to be understood that a wide variety of other circuit configurations known to those skilled in the art may be used.
• Digital configuration interface terminals 860 may be a bus (e.g., I2C) comprising multiple digital lines 850 for configuring one or more modules in circuit 890, for example.
• buffer circuit module 1001 configured on an integrated circuit with a plurality of other circuit modules 1002-1004.
• the circuit modules may be coupled together to perform a particular function during normal operation.
• the example in Fig. 10 shows the configuration of the test circuitry.
• buffer 1001 includes an external analog input (EXTIN), a digital test output PATENT
• analog outputs from buffer 1001 are coupled through AMUX 1007 to a first analog test output terminal TAOO.
• Analog outputs from circuit module 1004 are coupled through AMUX 1010 to a second analog test output terminal.
• Analog outputs from circuit module 1003 may be coupled through AMUX 1009, for example, to either or both of analog test output terminals TAOO and/or TAO1. Accordingly, analog test outputs of a circuit module may be selectively coupled to one analog test output TAOO (as in the case for buffer 1001) or to multiple analog test output terminals (as in the case for circuit module 1003).
• multiple analog circuit nodes of the same module or different modules may be coupled to the same test analog output terminal to advantageously allow testing of particular features of particular modules inside the integrated circuit.
• analog outputs of the same or different circuit modules may share the analog test output terminals by performing different tests at different time periods and reconfiguring the AMUXs between tests, as needed, for example.
• multiple analog test output terminals e.g., TAOO and TAO1
• TAOO and TAO1 may advantageously allow multiple analog signals to be measured from the same or different circuit modules simultaneously, for example.
• an integrated circuit may be advantageously tested from the inside out.
• circuit modules 1001-1004 may generate digital test outputs ⁇ dout>_tst. Such digital test outputs may be coupled through switch circuits such as PATENT
• DMUXs digital multiplexers 1015-1017, for example, to one or more digital test output terminals, e.g., TDOO and TDO1.
• Digital test output terminals shared across one or more circuit modules may allow for determine operability of subcircuits in the modules using, for example, a variety of built-in self-test circuits that generate a positive digital signal when the test is passed (e.g., successful power up or a variety of selfchecking circuits on various subcircuits in the module, for example).
• the switch circuits may be controlled by a plurality of configurations circuits.
• AMUXs 1005-1010 coupled to TAI0, TAI1, TAOO and/or TAO1 and DMUXs 1015-1017 are selected using a plurality of select configuration circuits 1018-1022.
• Each select configuration circuit 1018-1022 may be configured over a control bus.
• each select configuration circuit 1018-1022 may have a different address (e.g., a unique address on the particular integrated circuit).
• Each select configuration circuit 1018-1022 may further have logic to set one or more data bits (D) high or low based on signals received over the bus.
• D data bits
• circuit modules may have digital inputs for configuring the operation of the circuit module.
• a select configuration circuit has one or more digital bit outputs (D) couple to a digital input of a circuit module (e.g., the enable input of buffer 1001).
• Circuit module 1004 may have a test digital input, Din_tst, coupled to one or more digital data inputs (D) of a select configuration circuit. Accordingly, the digital values of Din_tst may be set on the fly over the control bus (Ctrl) to change the behavior of a circuit module and/or provide test digital inputs for testing the circuit module, for example.
• Select configuration circuits 1018-1022 may be controlled over the control bus, which may also be coupled an interface controller digital circuit.
• PATENT PATENT
• Pins 1 and 2 are used to communicate with the I2C interface 1050 (over clock SCL and data SDA lines), Pins 3 and 4 are coupled to the test analog output terminals TAOO and TAO1, Pines 5 and 6 are coupled to the test analog input terminals TAI0 and TAI1, and Pins 7 and 8 are coupled to the test digital output terminals TDOO and TDO1, respectively.
• switch circuits for coupling analog and digital signals between test terminals of the integrated circuit and test nodes of particular circuit modules may be configured using select configuration circuits that receive data over an internal test configuration and control bus (Ctrl) 1051.
• a particular configuration circuit detects it’s address on the control bus (Ctrl) line, it translates the instruction on the bus into output commands (e.g., digital signals to select a particular MUX path or to enable or otherwise configure a digital input of a circuit module).
• output commands e.g., digital signals to select a particular MUX path or to enable or otherwise configure a digital input of a circuit module.
• control bus architectures could be used in various embodiments.
• embodiments of the present disclosure may further automatically generate the instance of a synchronous bus interface circuit 1050 (e.g., a
• test routines to test various embodiments of functional circuit components, including, PATENT
• test routines 1150 when the test routines 1150 are selected based on particular parameter values (e.g., param_i) that are also used to generate a transistor level schematic of a circuit including a number of parameterized functional circuit components, such test routines 1150 may be automatically converted into an ATE test program 1157 for testing an integrated circuit chip embodying the same parameterized functional circuit components.
• Automated test equipment (ATE) 1158 may include a wide range of systems, but may specifically include voltage/current sources, voltage/current meters, waveform generators (aka function generators), and waveform measurement systems.
• the ATE test program 1157 is used to control benchtop test equipment (e.g., a bench setup) comprising one or more voltage/current sources, one or PATENT
• test equipment 1158 may be a semiconductor ATE for analog or mixed signal production test of integrated circuits as are well known to those skilled in the art, including systems with analog or mixed signal testing capability offered by Teradyne®, Advantest®, or Cohu®, for example.
• Such systems may load ATE test program 1157 into a control unit, and execution of the test program issues command signals to a variety of test system components (e.g., test head cards) for generating voltage/current, measuring voltage/current, generating waveforms, and/or measuring waveforms, for example.
• test system components e.g., test head cards
• some embodiments of the present disclosure may automatically select test routines that may be used to generate transistor level verification and/or physical verification (e.g., automated bench testing and/or production testing), for example.
• Fig. 12A illustrates a plurality of functional circuit components (FCCA- FCCZ), each configurable with parameters.
• FCCA may be configured with N (an integer) different parameters (e.g., FCCA 1201 has parameter values “params_l” and FCCA 1207 has parameter values “params_N”).
• FCCZ may be configured with M (an integer) different parameters (e.g., FCCZ 1213 has parameter values “params_l”’ and FCCA 1207 has parameter values “params_M”).
• each set of parameter values for each FCC may be used to select test routines, such as test routines 1204 for FCCA:params_l, test routines 1210 for FCCA:params_N, test routines 1216 for FCCZ:params_l’, and test routines 1222 for FCCZ:params_M.
• the various parameterized functional circuit components and corresponding test routines may be used in various chip designs where they are converted to circuit schematics and test cells (schematics 1202, 1208, 1214, and 1220 and corresponding test cells 1205, 1211, 1217, and 1223, respectively).
• the schematics may, in turn, be converted to layouts to produces physical circuits, and the test routines may be converted to corresponding ATE test programs (e.g., physical circuits 1203, 1209, 1215, and 1221 and corresponding ATE test programs 1206, 1212, 1218, and 1224).
• the various parameterizations of the FCCs may be incorporated into chip designs as illustrated at 1250. Different designs may use different FCCs having different parameters, and some designs will have the same FCCs with the same parameters.
• design 1251 has different FCCs with different parameters than designs 1252 and 1253, but design 1252 uses FCCA with the same parameters (pl) as design 1253. Since FCCs may be tested while embedded in a plurality of designs using the at least some of the same tests derived from the same test routines, data for the same parameterized functional circuit components may be obtained across designs, for example, to improve the characterization of the functional circuit component. In this example, test data for all the parameterized FCCs are stored in a database 1254.
• the test data may include a plurality of test results for different tests
• the test data may include data distributions for particular tests for each FCC having the same parameters (e.g., the same gain) or tests that span multiple parameterizations (e.g., offset voltage).
• test data describing the behavior of each physical manifestation of each functional circuit component may be used to update behavioral models 1256 used to model each functional circuit component, for example, thereby increasing the accuracy of the behavioral models used to design the integrated circuits.
• Fig. 12B illustrates generating a circuit according to an embodiment.
• a plurality of functional circuit components are specified for a circuit to be generated.
• functional circuit components may be parameterized building blocks of larger circuit, where the parameters change the characteristics of the functional circuit component.
• the functional circuit components are analog functional circuit components for generating analog circuits.
• functional circuit components may be one or more of: a comparator circuit, an oscillator circuit, a delay circuit, a current generator circuit, a voltage reference circuit, an amplifier circuit, a voltage buffer circuit, a bandgap circuit, a current mirror circuit, a transconductance circuit, and a voltage-to-current converter circuit.
• functional circuit components have a plurality of corresponding parameters, where different values for each of the plurality of corresponding parameters produce functional circuit components with different characteristics. Accordingly, at
• parameters are specified for each functional circuit component.
• Functional circuit components for a circuit to be generated may be specified in a variety of ways. For example, in one embodiment, a user may drag graphical representations of the functional circuit components into a circuit design canvas and enter the parameter values for each functional circuit component to form the circuit. In other embodiments, a user may input a specification for a circuit to be generated, and a software engine (e.g., using predefined rules) may select the required functional circuit components and configure the parameters for each functional circuit component to form the circuit.
• a software engine e.g., using predefined rules
• predefined behavioral models are selected based on the parameters. For instance, different parameters for a same functional circuit component (e.g., two values for amplifier gain) result in selection of different corresponding behavioral models (e.g., one model optimized for each gain value). As described in more detail below, behavioral models according to the present disclosure may be optimized for particular functional circuit component parameters. In one example, a behavioral model is customized to accurately model a functional circuit component for one or more parameters values (e.g., dominant parameters, such as gain or offset). In other PATENT
• a behavioral model is customized for each unique set of parameters. For example, if an amplifier’ s parameters are gain, offset, and input type, a different behavioral model for each unique set of parameter values may be generated and stored for use when an amplifier having those unique set of parameter values is part of a circuit design. At 1233, steps 1231 and 1232 are repeated for any additional functional circuit components in the circuit to be generated. At 1234, a behavioral simulation of the circuit to be generated may be executed based on the selected predefined behavior models.
• the behavioral models are generated based on data collected from actual silicon circuits of the functional circuit components having the particular specified values, they are sufficiently accurate to move to generation of the circuit at 1235 (e.g., without transistor level simulation).
• generation of the circuit at 1235 includes automatically generating the circuit schematic based on the parameterized functional circuit components and generating the mask for the circuit.
• the transistor level schematics and mask are generated based on the behavioral simulation of the circuit and not a transistor level simulation of the circuit, for example.
• a functional circuit component e.g., a comparator
• test data from the circuit e.g., including the comparator with particular parameters
• the functional circuit component with particular parameters may be on multiple different circuits, and test data from the circuits includes particular data for the functional circuit component with particular parameters.
• Fig. 12C illustrates generating a circuit according to another embodiment.
• one or more circuits are generated from parameterized functional circuit components using traditional transistor level simulation techniques, converted to masks, fabricated, and tested. Data from working functional circuit components with particular parameter values are used to generate custom behavioral models.
• circuits comprising functional circuit components with corresponding custom behavioral models are advantageously simulated using the behavioral model, and masks are generated without the need for additional timeconsuming transistor level simulations.
• a functional circuit component is specified at 1240.
• the parameters for the functional circuit components are specified.
• behavioral models for the functional circuit components are retrieve from a storage location 1260 (if they exist).
• a functional circuit component may have a generic behavioral model used for any and all parameter values. Accordingly, when a behavioral simulation is performed at 1243, the results may not match the actual results in an actual physical (e.g., silicon) implementation.
• a transistor level schematic of the circuit to be generated is produced (e.g., automatically by software) and simulated at 1245 to verify the functionality of the functional circuit components and the circuit as a whole (e.g., top level functionality).
• Attorney Docket No.: 000203-000502WO same or different parameter values may be stored in a data repository 1249.
• a customized behavioral model corresponding to the functional circuit component having the particular parameters is generated at 1261 based on at least a portion of the data (e.g., a data for a comparator with particular parameters, data for a current mirror having particular parameters, data for an amplifier having particular parameters).
• the generic behavioral model already existed for a functional circuit component, then the generic behavioral model may be modified to produce a customized behavioral model.
• the result is that functional circuit components with particular parameter values will each have a corresponding predefined behavioral model customized to fit the test data from a physical implementation of that functional circuit component and particular parameter values.
• the same functional circuit components with the same parameters may be reused and embedded in multiple integrated circuits. Therefore, the predefined behavioral models are modified based on the test data for those components to generate the customized behavioral models corresponding to particular parameters.
• different parameter values for a comparator functional circuit component may produce N (where N is an integer greater than 1) different types of comparators and N different transistor level schematics of comparators with different electrical characteristics.
• each of the N comparators may be tested. Testing may involve collecting data for a wide variety of electrical characteristics as are known to those skilled in the art. Test data may include multiple data points for each of the electrical characteristics taken across many instances of each of the N comparators. For example, fabrication may produce M (where M is an integer greater than 1) physical comparator die having the same parameters. Thus, test data may be gathered for MxN physical circuits, where M is the number of physical comparator circuits having the same parameters and N is the number of different types of comparators.
• Test data may include a wide range of data commonly referred to as characterization data, which characterizes the behavior of a circuit. Characterization data for each of the N PATENT
• models Ml may all be associated with a particular functional circuit component (e.g., an amplifier), where model MIA is associated with the amplifier having a first set of parameter values, model M1B is associated with the amplifier having a second set of parameter values, and so on up to model MIN, where N is an integer.
• another functional circuit component may have a plurality of behavioral models based on the parameters.
• models M2 may all be associated with another particular functional circuit component (e.g., a comparator), where model M2A is associated with the comparator having a first set of parameter values, model M2B is associated with the comparator having a second set of parameter values, and so on up to model M2P, where P is an integer.
• Different functional circuit components may have different numbers of parameters and different numbers of parameter values. Accordingly, different functional circuit components may have different numbers of customized behavioral models. Thus, different parameters for a same functional circuit component result in selection of different corresponding predefined parameterized behavioral models.
• Fig. 13 illustrates a computer implemented method according to an embodiment.
• a plurality of circuit designs may be generated from a plurality of functional circuit components.
• the functional circuit components may comprise a plurality of parameters, where the circuit designs have at least some different circuit modules corresponding to different functional circuit components having different parameters.
• a user may perform a behavioral simulation of the circuit design. Once the behavioral simulation works as desired (e.g., once the required functional circuit components are included in the design and set with the correct parameter values), the user may trigger generator software to generate a transistor level schematic for the design (and a layout).
• a plurality of test routines are selected for functional circuit components in the circuit designs.
• the test routines may be selected based, at least in part, on parameter values of the functional circuit components in the circuit design.
• a plurality of test data are gathered for the plurality of circuit designs.
• the test data may comprise results of a plurality of tests for each functional circuit component, for example.
• the plurality of test data is stored in a database.
• the behavioral models for the functional circuit components are updated using the test data.
• Fig. 14 illustrates example computer system hardware according to certain embodiments. Various embodiments of the present disclosure may be implemented in computer executable code (software) for performing various techniques described herein. Fig. 14 illustrates a simplified example of a computer used to execute software according to various embodiments. One or more such computers may be used to PATENT
• a computer system 1400 may include one or more processors 1401, such as a multi-processor CPU (e.g., from Intel® or AMD®).
• processors 1401 may load executable program code from a computer readable storage medium, which when executed, performs some or all of the techniques described herein.
• Processors 1401 may be coupled to one or more buses, which are represented here as bus 1405, to communicate with various subsystems.
• processor(s) 1401 may communicate with a storage device 1402 (e.g., to retrieve executable code), which may comprise magnetic storage, optical storage, or solid-state storage, for example.
• Processor(s) 1401 may further communicate with memory 1403 over a bus 1405.
• Memory 1403 may represent a number of memories including a random-access memory (RAM) for storage of instructions and data during program execution and a read-only memory (ROM) 1420 in which fixed instructions are stored, for example.
• processor(s) 1401 may communicate with removable media (e.g., CD-ROM, DVD, Blu-Ray, etc.), a removable flash memory -based drive or card, and/or other types of storage media known in the art.
• Processor(s) 1401 may communicate with a network interface 1404 over a bus 1405, for example.
• Network interface 1404 may allow computer system 1400 to communicate with a network 1410 which may be in communication with other computer systems to perform the techniques described herein, for example.
• network interface 1404 may include, for example, an Ethernet card to support a variety of Ethernet rate connections (e.g., in an office, server room, or data center), a Wi-Fi, IEEE 802 based system, and/or cellular adapter, a modem (telephone, satellite, cable, ISDN, etc.), digital subscriber line (DSL) units, and/or other data communications systems, for example.
• Fig. 15 illustrates various computer system configurations that may be used in certain embodiments.
• the executable code for performing the some or all of techniques disclosed herein may be executing on one or more server computers coupled together over a network 1510, such as a local area network (LAN), wide area network (WAN), or other networks (e.g., the Internet).
• LAN local area network
• WAN wide area network
• Internet the Internet
• some embodiments described herein may receive inputs from users. Accordingly, users may interact with computer systems 1530-1532, which in turn communicate with one or more server computers 1511-1514 over network 1510 to perform the techniques described herein, for example.
• a plurality of test routines associated with different parameter values have different associated test conditions.
• the method further comprises converting selected test routines to test cells, wherein the test cells are executable by a transistor level schematic simulator.
• the method further comprises generating one or more test cells based on the selected subset of test routines, wherein the one or more test cells are coupled to the at least one transistor level circuit module schematic.
• the hardware description language code is one of Verilog- AMS or Verilog-A.
• the method further comprises generating a plurality of switch circuit schematics configured between analog nodes of the circuit module PATENT
• a plurality of subsets of test routines are selected for a plurality of functional circuit components.
• each functional circuit component is tested by a corresponding subset of test routines independently of other functional circuit components.
• one or more of the analog nodes are an internal nodes.
• one or more of the analog nodes are outputs of the corresponding circuit modules.
• the plurality of switch circuits further comprising a fifth plurality of switch circuits, the fifth plurality of switch circuits configured between internal analog nodes of the corresponding circuit modules and the at least one analog test output.
• the third plurality of switch circuits are selectively coupled to the at least one analog test input through a sixth plurality of switch circuits.
• the sixth plurality of switch circuits form one or more analog multiplexers.
• the sixth plurality of switch circuits form an analog tree structure between the at least one analog test input and the third plurality of switch circuits.
• the fourth plurality of switch circuits are selectively coupled to the at least one analog test output through a sixth plurality of switch circuits.
• the sixth plurality of switch circuits form one or more analog multiplexers.
• At least a portion of the switch circuits coupled to each circuit module are configured by one or more corresponding addressable digital configuration circuits.
• the digital configuration circuits each comprise an address, and wherein switch circuits of the plurality of switch circuits coupled to a first circuit module are opened and closed in response to one or more corresponding digital configuration circuits receiving a first address and data.
• the digital configuration circuits are coupled to a synchronous bus interface circuit to receive data from an external source.
• the present disclosure includes computer-implemented method comprising: receiving, by at least one software system executing on at least one computer, parameters corresponding to at least one analog functional circuit component the parameters comprising an activated test mode parameter; and selecting, based on the circuit specification parameters and the activated test mode parameter, a plurality of subcircuit schematics, wherein the subcircuit schematics include circuitry for externally accessing the at least one functional circuit component when the at least one functional circuit component is embedded in a circuit design; and generating a transistor level schematic for the circuit design, the transistor level schematic comprising circuitry for accessing one or more of an input node, an output node, or an internal node of the at least one analog functional circuit component.
• a different plurality of subcircuit schematics are selected when the test mode parameter is deactivated.
• the integrated further comprises selecting a subset of test routines from a plurality of test routines for the at least one analog functional circuit component, wherein the plurality of test routines are configured to test the at least one analog functional circuit component across different values of the circuit specification parameters.
• the present disclosure includes a computer- implemented method comprising: generating a plurality of circuit designs from a plurality of functional circuit components, the functional circuit components comprising a plurality of parameters, wherein the circuit designs have at least some different circuit modules corresponding to different functional circuit components having different parameters; selecting, for the functional circuit components in the circuit designs, a plurality of test routines, wherein the test routines are selected based, at least in part, on parameter values of the functional circuit component parameters; gathering a plurality PATENT
• test data for the plurality of circuit designs, the test data comprising results of a plurality of tests for each functional circuit component; storing the plurality of test data in a database; and updating behavioral models for the functional circuit components using the test data.
• the present disclosure includes a computer- implemented method comprising: specifying a plurality of functional circuit components for a circuit to be generated; for each of one or more of the functional circuit components of the plurality of functional circuit components: specifying parameters of the functional circuit component; and selecting, based on the parameters, a predefined behavioral model corresponding to the functional circuit component having the specified parameters, wherein different parameters for a same functional circuit component result in selection of different corresponding behavioral models; executing a behavioral simulation of the circuit to be generated based on the selected predefined behavior models for the plurality of functional circuit components.
• the method further comprises generating a mask for the circuit, wherein the mask is generated based on the behavioral simulation of the circuit and not a transistor level simulation of the circuit.
• a plurality of predefined behavioral models corresponding to particular functional circuit components having different user specified parameters are generated from characterization data from one or more automatically generated circuits comprising said functional circuit components.
• the parameters are generated in response to user inputs.
• the functional circuit components are analog functional circuit components for generating analog circuits.
• the functional circuit components have a plurality of corresponding parameters, wherein different values for each of the plurality of PATENT
• the functional circuit components are one or more of: a comparator circuit, an oscillator circuit, a delay circuit, a current generator circuit, a voltage reference circuit, an amplifier circuit, a voltage buffer circuit, a bandgap circuit, a current mirror circuit, a transconductance circuit, and a voltage-to-current converter circuit.
• the present disclosure includes a method comprising: specifying a plurality of functional circuit components for a circuit to be generated; specifying parameters of the plurality of functional circuit components; and generating a mask for the circuit to be generated comprising the plurality of functional circuit components having the specified parameters; fabricating the circuit based on the mask; storing data specifying an actual behavior of the plurality of functional circuit components having the specified parameters in the fabricated circuit; and for each functional circuit component, generating a customized behavioral model corresponding to the functional circuit component having the specified parameters based on at least a portion of the data.
• the method further comprises generating a mask for the second circuit, wherein the mask is generated based on a behavioral simulation of the circuit and not a transistor level simulation of the circuit.
• the functional circuit components are analog functional circuit components for generating analog circuits.
• the functional circuit components have a plurality of corresponding parameters, wherein different values for each of the plurality of corresponding parameters produce functional circuit components with different characteristics.

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• 2022
  • 2022-08-23 EP EP22862000.1A patent/EP4392893A4/de active Pending

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