EP4363964A1 - Division method and circuit - Google Patents

Abstract

In the present invention, the divider circuit divides two integer numbers using a novel hardware and circuit implementation technique to get the resultant quotient and the residue or remainder, based on using Modified Divisor (MDr) and variable dividend grouping based on the number of zeros canceled to achieve variable conversion time or latency and area efficiency. The number of iterations depends on the number of group dividends are formed based on the count of the number of zeros canceled while deriving Modified Divisor (MDr).

Description

FIELD OF INVENTION

The invention relates to the field of methods, apparatus, hardware and circuit implementation for performing mathematical operations within embedded systems, digital systems, integrated circuits (IC), application specific integrated circuits (ASIC), digital circuits, computer systems with and without transistory memory included but not limited to volatile memory, non-volatile memory, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs), DVDs (digital versatile discs or digital video discs), or other media capable of storing code and/or data now known or later developed.

BACKGROUND OF THE INVENTION

Division operation is a derived operation like multiplication; instead of successive addition, it is derived by successive subtraction or multiplication and some controlling conditions. Modern applications like computers, the internet of things (IoT), 5G communication, artificial intelligence (AI), machine learning, image processing, biomedical engineering, aeronautical and space engineering, green fuel system, embedded systems, quantum computing, etc. require thorough application of mathematical concepts to mitigate (cover) with the desired goals of the problem or application. All mathematical operations have been implemented using electronic or digital platforms, but it is still critical to implement a division operator. Time and area are two basic requirements of embedded systems, digital systems, integrated circuits, digital circuits, and computer systems. Many techniques that have been designed and implemented to improve the division operation can be broadly classified into two classes - digit recurrence and functional iteration classes. Multiplicative or functional iterative techniques/algorithms are faster in operation than subtractive techniques/algorithms but require relatively larger area for implementation. Digit recurrence algorithm-based divider techniques are the most commercially implemented dividers, and SRT division is one of the most implemented non-restoring digit recurrence division algorithms. Although SRT dividers exhibit simple conversion logic, the implementation of the SRT divider is restricted to low order radix due to the practically unfeasible quotient selection table requirement. The overlapping region in the quotient selection table can cause a problem in selecting the quotient value.

OBJECTIVES OF THE INVENTION

Implementation of division operation in FPGA is needed because of the emerging applications where these devices are used to implement some critical system-on-chip application or improve the existing application, and indirect division operation results are not enough. High radix reduces latency but requires a large capacity look-up table which impractical for implementation. Furthermore, Newton-Raphson generates an error depending on how close is selected multiplier or reciprocal value at the beginning. Reducing the error requires introducing a tradeoff between an additional chip area for a look-up table and the latency of the divider. Also, many optimization techniques like operand scaling and cascading were implemented to improve the SRT division algorithm, improving the speed, but the area overhead increases rapidly. It motivates to develop a new technique which is fast in operation, and area-efficient. Thus, the main objective of the present invention to provide an area-efficient solution for divider implementation.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

The invention will now be described concerning the accompanying drawings, in which:

Fig. 1 A is a Functional Block Diagram of USP-Awadhoot Technique used in divider circuit.

Fig. IB is a Schematic block diagram of the proposed divider based on the USP-Awadhoot technique.

Fig. 2 is a Circuit Description Sheet 1, which is also termed as input stage for the divider, illustrating divider selection circuit part of dividend and divisor selection circuit and new divisor and flag digit selection circuit of the divider. This part of the circuit also controls the number of iterations related to the number of groups arranged.

Fig. 3 is a Circuit Description Sheet 2, which is also termed the status check stage, illustrating the dividend grouping circuit and iteration and condition check circuit. In addition, the dividend groups and quotients of the dividend groups called a Group Quotient (GQn) are stored and updated. Fig. 4 is a Circuit Description Sheet 3, which is also termed as input stage 2 for the divider, illustrating dividend selection circuit part of dividend and divisor selection circuit and modified divisor and number of zeros canceled selection circuit. Also, the values of NDr, Drl, Dr, and Dd manage and stored.

Fig. 5 is a Circuit Description Sheet 4 for an intermediate stage, illustrating the part of the circuit that manages and stores values of MDr, and shows residue or remainder circuit part of result circuit that calculates residues for each iteration.

Fig. 6 is a Circuit Description Sheet 5 for an intermediate stage, illustrating the part of the circuit that manages and stores the second dividend group, residue value, and part of FD.

Fig. 7 is a Circuit Description Sheet 6 for an intermediate stage, illustrating the part of the circuit that manages the value of the Gross dividend (GDd), stores value of FD, and manages and stores values of NDd and value of n, i.e., iteration count.

Fig. 8 is a Circuit Description Sheet 7, for a pre-output stage illustrating part of iteration and condition check circuit and result circuit, which manages and stores the FSM states for condition check and control and Additional Quotient (AQ) value.

Fig. 9 is a Circuit Description Sheet 8 for an Output stage, illustrating part of the result circuit that maintains Additional Quotient (AQ) value and derives Quotient (Q) output. Fig. 10 is a FSM State Diagram.

Fig. 11 is a Main Circuit Flow Chart.

Fig. 12 is a Sub Circuit Flow chart.

Fig. 13 is an Awadhoot Matrix.

Fig. 14 A to H show a Clock Performance Analysis.

Fig. 15 A shows a Reference Working Waveform Analysis.

Fig. 15B shows a Waveform analysis for the divide by zero condition.

Fig. 15C shows a Waveform analysis for the state of different signals when enable (FD Enable) signal is inactive.

Fig. 15D shows a Waveform analysis for the condition when one digit (4 binary bits) hexadecimal dividend is divided by one-digit hexadecimal (4 binary bits) divisor showing complete division. Fig. 15E shows a Waveform analysis the condition when one-digit hexadecimal (4 binary bits) dividend is divided by one-digit hexadecimal (4 binary bits) divisor showing partial division.

Fig. 15F shows a Waveform analysis for the condition when a two-digit hexadecimal (8 binary bits) dividend is divided by one-digit hexadecimal (4 binary bits) divisor showing complete division.

Fig. 15G shows a Waveform analysis for the condition when a two-digit hexadecimal (8 binary bits) dividend is divided by one-digit hexadecimal (4 binary bits) divisor showing partial division. Fig. 15H shows a Waveform analysis of the condition when a two-digit hexadecimal (8 binary bits) dividend is divided by a two-digit hexadecimal (8 binary bits) divisor showing a complete division.

Fig. 151 shows a Waveform analysis for the condition when a two-digit hexadecimal (8 binary bits) dividend is divided by a two-digit hexadecimal (8 binary bits) divisor showing partial division.

Fig. 15J shows a Waveform analysis for the condition when one-digit hexadecimal (4 binary bits) dividend is divided by a unity value divisor.

Fig. 15K shows a Waveform analysis for the condition when a two-digit hexadecimal (8 binary bits) dividend is divided by a unity value divisor.

Fig. 15L shows a Waveform analysis for the condition when the value of dividend and divisor is the same.

Fig. 16 is a Table 1, showing the Element List of Circuit Description Sheet 1.

Fig. 17 is a Table 2, showing the Element List of Circuit Description Sheet 1 and Sheet 2.

Fig. 18 is a Table 3, showing the Element List of Circuit Description Sheet 2 and Sheet 3.

Fig. 19 is a Table 4, showing the Element List of Circuit Description Sheet 3 and Sheet 4.

Fig. 20 is a Table 5, showin the Element List of Circuit Description Sheet 4 and Sheet 5. Fig. 21 is a Table 6, showing the Element List of Circuit Description Sheet 6 and Sheet 7.

Fig. 22 is a Table 7, showing the Element List of Circuit Description Sheet 7 and Sheet 8.

Fig. 23. is a Table 8, showing the Element List of Circuit Description Sheet 8.

Fig. 24 is a Table 9, showing an Element List of USP-Awadhoot Technique.

Fig. 25 is a Table 10, showing a Table of States.

Fig. 26 is a Table 11, showing a Table of Number Representation.

Fig. 27, is a Table 12, showing a Flow Points of Main Circuit Flow Chart.

PET ATT, ED DESCRIPTION OF THE INVENTION

The embodiments of the present invention are disclosed herein with reference to the accompanying drawings and tables. The disclosed embodiments are merely illustrative of the present invention and may take various forms in which the present invention may be practiced. In addition, the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the present invention. In addition, each of the examples given in connection with the various embodiments is intended to be illustrative and not restrictive. Therefore, specific structural and functional details disclosed herein are not limiting but merely as a representative basis for explaining one skill in the art to variously employ the present invention. For example, as used herein, the given embodiment of present invention term multiplexer used to manage residue and FD value be abbreviated as MUX Residue and MUX FD. Thus, the present invention is not limited to the embodiments shown but is it be accorded the widest scope consistent with the principles and features disclosed herein.

The methods and processes described in a present invention relate to hardware and circuit implementation techniques for performing mathematical operations within embedded systems, digital systems, integrated circuits, digital circuits, computer systems, etc. Computer systems may be with and without transitory computer-readable storage mediums or may be any device or non- transitory medium that can store code or data used by a computer or digital, electronic, or embedded system, etc. The non-transitory computer-readable storage medium includes, but is not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs), DVDs (digital versatile discs or digital video discs), or other media capable of storing code and/or data now known or later developed. Furthermore, methods, techniques and processes described in detailed description can be embodied as a code and/or data stored in a non-transitory computer-readable storage medium described above; circuits or integrated circuits can be included in hardware modules. The division is one of the most critical and time-consuming arithmetic operations to represent in machine or hardware. Even though division occurs less frequently amongst arithmetical operations, hardware or system performance is very much dependent on the efficient divider. The basic division technique is represented as a Dividend (Dd) = a Divisor (Dr) * a Quotient (Q) + a Remainder (R). The present invention describes the novel technique of hardware and circuit implementation of division. Fig. 1 A and Fig. IB represent the basic idea of the novel USP- Awadhoot algorithm/technique used for divider hardware and circuit implementation. Fig. 1A represents the functional block diagram of USP- Awadhoot Technique to provide details about the various process involved in the present invention divider based on USP- Awadhoot Technique. It shows that the complete technique is subdivided into three stages of operation: a pre-processing circuit stage, a processing circuit stage, and a post-processing circuit stage. Fig. IB is a schematic block diagram of proposed divider based on the USP- Awadhoot technique used as a reference to develop hardware and circuit implementation of divider in the present invention. It indicates that the common steps of the pre-processing circuit stage are implemented with the separate hardware and circuit implementation for the dividend and the divisor. Fig.2 to Fig.9 represent hardware and circuit implementation of the USP-Awadhoot technique.

The embodiments of the present invention used hexadecimal numbers, as shown in Fig. 26 table 11 illustrating table of number representation to perform binary division. The main advantage of utilizing hexadecimal numbers is the compact bit representation pattern as, on the other hand, there are more possibilities for both read and write errors when working with large digital systems. One common way of overcoming this problem is arranging the binary numbers into a particular fixed arrangement. Furthermore, the hexadecimal number makes it easy for computation by reducing complexity in the conversion method. In the present invention, the Dividend (Dd), the Divisor (Dr), the Quotient (Q), and the Remainder or the Residue (R) are presented in the hexadecimal pattern. As per the functional block diagram of USP- Awadhoot Technique expressed in Fig. 1 A; Fig. 2 represents the input or pre-processing circuit stage of the present invention. Fig. 9 represents the final or output stage or post-processing circuit stage of the present invention.

In an embodiment of the present invention, the Dividend grouping circuit plays a vital role in providing variable latency features in the USP-Awadhoot division technique. The Dividend grouping circuit depends on the Number of Zeros cancellations circuit. After performing grouping of dividend, iterations, and condition check circuit work on each individual group in a sequence. The last iteration, which is nothing but the last dividend group, formulates the Quotient (Q) as a result and residue as Remainder (R). In various embodiments of the present invention, provide a divider circuit, which divides dividend by divisor. Another embodiment of the present invention provides a technique/algorithm for dividing two integer numbers, but it is not restricted to using other formats like floating-point and complex numbers. Finally, some present invention embodiments provide details regarding the USP-Awadhoot division technique and detail circuit flow of variable clock divider circuit. Time and area are two basic requirements of divider implementation; therefore, some embodiments of the present invention involve speeding up division operations by reducing the latency per iteration and/or reducing the number of iterations per division. Therefore, the following detailed description consists of three parts. In the first part, the divider circuit based on the USP-Awadhoot technique according to the present invention is described. In the secord part, a detailed description of the Awadhoot matrix steps involved in the USP-Awadhoot technique is described and in the thid part the working examples are described.

Referring now to Fig. 1A, a Functional Block Diagram of the USP-Awadhoot Technique depicts the basic concept used for dividing dividend by divisor according to an embodiment of the present invention. The technique is sectaries in 398, 399, 400, 401, 402, 403, 404, and 405 eight main steps named as dividend and divisor selection circuit, new divisor and flag digit selection circuit, modified divisor and NZC selection circuit, dividend grouping circuit, summation point, iteration, condition check circuit and result step in the hardware and circuit implementation used in accordance with an embodiment of the present invention. Some of the main steps have many sub-steps as a part of them. For example, the embodiment of the present invention divider represents its division as follows.

Dividend (Dd) = Divisor (Dr) * Quotient (Q) + Remainder (R) (1) whereas,

D_d = d₂ ... d_k\ ; where " D_d " represents dividend with a maximum size of "k" digits. Q = [¾ 2 R_k- iL where "Q" represents the quotient with a maximum size of "k-1" digits.

D_r = [d₁ cl₂ ... d_k] where "D_r" represents the divisor with a maximum size of "k" digits. R = [r_x r₂ ... r^_₁]; where "R" represents the remainder with a maximum size of "k-1" digits.

ND_r = \ndr-_L ndr₂ ... ndr_m ]; where "ND_r" represents the "New Divisor" with a maximum size of "m" digits. The range is defined as "k-1 < m < k+1".

FD = [fd₁ ]; where "FD" represents the "Flag Digit" with a maximum size of single-digit. represents the "Modified Divisor" with a maximum size of "p" digits. The range is defined as "p < k-1 ".

NZC = [nzc₁ nzc₂ ... nzc_p ]; where "NZC" represents the "Number of Zero" with a maximum size of "p" digits. The range is defined as "p < k-1 ".

ND_d = \ndd₁ ndd₂ ... ndd_k] where "ND_d" represents the "Net Dividend" with a maximum size of "k" digits.

GD_d = [gdd-_L gdd₂ ... gdd_k\ ; where " GD_d " represents the "Gross Dividend" with a maximum size of "k" digits.

Different terms used in the Awadhoot Matrix are expressed where, Product Term termed as "P-Term", Subtract Term termed as "S-Term", Group Quotient termed as "GQ", Additional Quotient termed as "AQ" and Partial Quotient termed as "PQ".

The first step of the USP-Awadhoot technique defines the required input operands in the required width format, thus block 398 of the Fig. 1 A provides dividend and divisor for the present invention after enabling, which are received by hardware and circuit implementation element 2, element 5, element 56, and element 61 of Fig. 2 and Fig. 4 according to the present invention's embodiment. As per Fig. IB schematic block diagram suggests that separate hardware is used for divisor and dividend. Divisor (Dr) is received by Fig. 2 Multiplexer-DRl element 2, and Multiplexer-DR2 element 5 and Dividend (Dd) are received by Fig. 4 MUX Dd l element 56 MUX Dd O elements 61. Received divisor further validated by examining for the invalid condition, i.e., divide by zero. Referring to Fig. 3, ADDER DR ZeroTest element 15 and EQUAL testZeroDr element 22 are used to detect the invalid condition, i.e., divide by zero and activate error signal upon the invalid condition, i.e., divide by zero. MUX_Dd_l element 56, LATCH Dd l element 59, AREG Dd l element 63, MUX Dd O element 61, LATCH Dd O element 65 and AREG Dd O element 67 manage and stores the value of Dividend (Dd).

The second step of the USP-Awadhoot technique derives New Divisor (NDr) and Flag Digit (FD), thus block 399 of the Fig. 1 A indicates New Divisor (NDr) and Flag digit (FD) is derived from the validated divisor of block 398. New Divisor (NDr) is derived by adding (±1) to (±9) integer number into the validated divisor of block 398, resulting in zero at the unit place, and the number, which is added into validated divisor of block 398, is termed as Flag Digit (FD). Referring Fig. 2 SUBTRACTOR FD element 3, MULTIPLIER element 7, MULTIPLEXER FD element 9, ADDER FD MSD element 12 and ADDER NDr element 13 derives New Divisor (NDr) and Flag Digit (FD). We can either add positive/negative numbers from the validated divisor from block 398 to derive New Divisor (NDr), and the number added derives Flag Digit (FD). If the negative number is added to the validated divisor from block 398, then Flag Digit (FD) is negative, and if the positive number is added to the validated divisor from block 398, then Flag Digit (FD) is positive. MUX_NDr element 21 passes the value of New Divisor (NDr) for the next blocks in further stages depending on the presence of the divisor's invalid condition. To keep uniformity in the technique, it is considered to add a positive integer number to the validated divisor from block 398. Referring to Fig.4, MUX NDr SIG element 49, LATCH NDr element 52, and AREG NDr element 57 store and pass the value of New Divisor (NDr).

The third step of the USP-Awadhoot technique derives Modified Divisor (MDr) and Number of Zeros Cancelled (NZC). Thus block 400 of the Figs. 1 A and B indicate Modified Divisor (MDr), and the Number of Zeros Cancelled (NZC) is derived from the New Divisor (NDr) of block 399. To derive Modified Divisor (MDr), cancel out zeros from units place and consecutive places if any consecutive zero(s) is available. After canceling zeros remaining value is termed as Modified Divisor (MDr), and the count of zeros that are canceled out in the process of deriving Modified Divisor (MDr) is/are termed as Number of Zeros Cancelled (NZC). Referring to Fig. 4 and Fig. 5, LESS THAN element 62, MULTIPLEXER element 66, MUX MDR element 71, LATCH MDR element 76, and AREG MDR element 79 manage and store MDr value, derive and store Number of Zeros Cancelled (NZC) and Modified Divisor (MDr).

The fourth step of the USP-Awadhoot technique derives the Dividend groups whose width/size is based on the count of the Number of Zeros Canceled (NZC). Thus the block 401 of the Fig.1 A and B indicate the width or size of each dividend group is equal to the NZC value, which rearranges the Dividend (Dd) available at block 398 into different Dividend groups starting from RHS or units place. The number of Dividend groups is equal to the number of iterations required to perform complete division. We have to make the group as per the Number of Zeros Cancelled (NZC) from RHS to LHS. The width of the group is equal to the value of NZC. In the last group, if the remaining count of digits is less than the required count in groups, add zeros (Stuffing) to the LHS to make it to the required count of digits per group. This zero-stuffing process is done by block 398 of the Fig. 1 A and B. E.g., Dividend: - 46624, NZC = 2 then Dividend grouping: - 04 6624. Here in the last group at LHS, i.e., 4, the count of digits is less than the required count in groups, then add zeros (Stuffing) to the LHS of the digit to make it to the required count of digits per group. So, add one 0 in LHS of 4, i.e., 04, will be the required group value. This zero-stuffing process is carried out at the pre-processing circuit stage of the Fig. 1. Upon obtaining dividend groups, block 402 Fig. 1 passed to rearrange in Awadhoot matrix as express in Fig. 13 to perform individual iteration.

The fifth step of the USP-Awadhoot technique rearranges Dividend groups obtained in block 401, Modified Divisor (MDr), and Flag Digit (FD) from block 400 of the Fig. 1 in a special matrix arrangement termed "Awadhoot Matrix," block 403 of Fig. 1 and details are shown in the Fig.13 according to the present invention's embodiment. At the beginning of the first iteration, Remainder/Residue (Rem-0) and previous Group Quotient (GQ0) values are considered 0. Referring Fig.2 ADDER nlter element 8, MULTIPLEXER N iter element 14, LATCH N iter element 23 and AREG N iter element 24 manages and stores value of iterations.

The sixth step of the USP-Awadhoot technique derives the first iteration with Checking MDr > number from first Dividend Group. If it is true, then the quotient of the first dividend group is 0, and Remainder/Residue for the selected iteration is equaled to the first Dividend Group. Else derive Gross Dividend (GDd). If it is other than the first iteration, then directly derive Gross Dividend (GDd). At blocks 403 and 404, the conversion process starts for the Awadhoot Matrix. Start the first Iteration with Checking MDr > value of first Dividend Group. If it is true, then the quotient of the first dividend group is 0, and the remainder for the next iteration is equaled to the value of the first Dividend Group. Else, derive Gross Dividend (GDd).

The seventh step of the USP-Awadhoot technique derives Gross Dividend (GDd) derived by concatenating remainder and value of the current iteration dividend group. If it is other than the first iteration, then directly derive Gross Dividend (GDd).

The eighth step of the USP-Awadhoot technique derives the Product Term (P-Term) from the product of Flag Digit (FD) obtained at the block 399 of Fig. 1 and previous iteration Group Quotient (GQ) (if it is 1st iteration, then previous Group Quotient (GQO) = 0).

The ninth step of the USP-Awadhoot technique derives Net Dividend (NDd) as per the Awadhoot Matrix expressed in the Fig. 13 by adding Product Term (P-Term) calculated in the eighth step of the current iteration of the Awadhoot Matrix with the Gross Dividend (GDd) value calculated at the seventh step of the current iteration. After deriving Net Dividend (NDd), check for a sign; if the Net dividend is negative, cancel iteration and decrease previous Group Quotient (GQn) by one and redo this iteration. If a Net dividend is positive, then check its value. Blocks 402, 403, and 404 of the Fig. 1 perform calculation, sign investigation, and decision making together as explained in Fig. 13.

The tenth step of the USP-Awadhoot technique derives Subtract Term (S-Term) by multiples of Modified Divisor (MDr) value. The Modified Divisor (MDr) value considered here is supplied by block 400 of Fig. 1. The subtract Term (S-Term) value should be equal to Net Dividend (NDd) value calculated in the ninth step or less and closer possible if equality is not possible.

The eleventh step of the USP-Awadhoot technique derives Group Quotient (GQn) and Remainder/residue (Rem-n) by subtracting the value of Subtract Term (S-Term) from the Net Dividend (NDd) value calculated in the ninth step. Thus, the count of Modified Divisor (MDr) multiples used in the ninth step is termed as Group Quotient (GQn) in Quotient Row, and subtraction result is carry forward in Remainder/residue (Rem-n) row for the next iteration as expressed in the Fig. 13.

The twelfth step of the USP-Awadhoot technique continues to performing the seventh step to the eleventh step of the USP-Awadhoot technique for all Dividend Groups. Block 402 Summing point of the Fig. 1 provides a connection between consecutive iteration required for the Awadhoot Matrix in the USP-Awadhoot technique. In the last iteration of Awadhoot Matrix, check for the Net Dividend (NDd) value from the current iteration providing four possibilities for the Quotient (Q) and Remainder/Residue (R) values calculated in the next step of the USP-Awadhoot techniques.

The thirteenth step of the USP-Awadhoot technique derives the final result calculation for Quotient (Q) and Remainder/Residue (R) values. Partial Quotient (PQ) value is formed by concatenating individual Group Quotients (GQn) starting from LHS to RHS of Awadhoot Matrix as expressed in Fig.13. Remainder/Residue (R) value is the same value obtained in the final iteration of the Awadhoot Matrix. Referring to Fig.3, MUX G Q l, MUX_G_Q_2, MUX G Q l l to MUX_G_Q_1_6 element 35, element 36, and element 29 to element 34 manages the value of Awadhoot Matrix processing depending on the iterations and passes that value to the next iteration. LATCH _G_Q_1 element 39, LATCH _G_Q_2 element 40, AREG G Q l element 41, and AREG G Q 2 element 42 Latches and stores value of G_Q Group Quotient (GQn) of related iteration. As per the Net Dividend (NDd) sign at the last iteration, we can get four possibilities.

First: Net Dividend (NDd) = 0, i.e., Dividend (Dr) is completely divisible by Divisor (Dr) with

Remainder/Residue (R) = 0 and Quotient (Q) = Partial Quotient (PQ).

Second: Net Dividend (NDd) = Divisor (Dr), i.e., Dividend (Dr) is completely divisible by

Divisor (Dr) with Quotient (Q) = Partial Quotient (PQ) + 1 and Remainder/Residue (R) = 0.

Third: Net Dividend (NDd) < Divisor (Dr); final Result/ Quotient (Q) = Partial Quotient and

Remainder/Residue (R) = Value of last iteration NDd.

Fourth: Net Dividend (NDd) > Divisor (Dr); Quotient (Q) = Partial Quotient (PQ) + Additional

Quotient (AQ) and Remainder/Residue (R) = Value obtained during calculation of Additional

Quotient (AQ).

The Additional Quotient (AQ) is derived by initializing count to zero and subtracting Divisor (Dr) from the last iteration Net Dividend (NDd) number and increment count by one. If the subtraction result, i.e., Sub result, is non-zero and greater than or equal to Divisor (Dr), continue subtracting Divisor (Dr) from Sub Result and increment count every time we perform subtraction until we get sub result zero or less than the divisor. If the Sub result is 0 or less than Divisor (Dr), then stop subtraction. This Sub result is termed as a Reminder (R), and the count is termed as Additional Quotient (AQ).

It will be understood by those of skill in the art that different arrangements of logic gates may perform the same logical function or that logic circuits operate using either positive or negative logic signals. Therefore, variations in the arrangement of some of the logic gates or circuits described above should not be considered to depart from the scope of the present invention. Furthermore, while various embodiments of the present invention have been illustrated and described, it will be clear that the present invention is not limited to these embodiments only. Thus, numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art without departing from the spirit and scope of the present invention as described in the claims.

Referring to Fig. 2 to Fig. 9, the circuit schematic is described according to the embodiment of the present invention. Referring now to Fig. 2 Circuit Description Sheet 1, which is also termed as input stage pre-processing circuit stage for the divider, illustrating divider selection circuit part of dividend and divisor selection circuit and new divisor and flag digit selection circuit in accordance with an embodiment of the present invention, the inputs 161, 162, 163, 164, 165, 166 and 167 which are named as the first number as Divisor (Dr), Enable (E), Clock (CLK), Reset (RST), Second number as Dividend (Dd) and Fd Enable respectively are provided for the divider circuit is described in accordance with an embodiment of the present invention.

Referring to Fig. 2, the clock signal (CLK) input represented by line 165 and line 164 receives the reset signal (RST). The signal FD Enable used to enable/disable the module that implements the USP-Awadhoot technique is received by 167. The dividend number is available at input line 166. The divisor number is available at input line 161. The Divisor (Dr) number's most significant bits are sent to Multiplexer-DRl element 2, and the less significant bits are sent to Multiplexer- DR2 element 5. Rom-State selector element 1 outputs a logic "1" while the present state is a valid state belonging to the process, else it outputs a logical "0". When Latch element 4 receives a "1" from element 1, its outputs show the same value currently in its inputs; else, it keeps its previous values. When 163 indicates that the current state is stl, element 2 outputs Dr's current value through bus 168 (MSB of Dr). This value goes to element 4, and because stl is a valid state of the process, element 4 passes this value to 179, reaching register ARE-MSD-DR element 10, which stores it. Element 10 also passes this value to almost all the inputs in element 2, when 163 changes, because present state changes, element 2 keeps this value of Dr except for states stl and stEr. If stEr is the present state, then the value in 171 is passed by elements 2 and 5, which results in Dr = 0. Element 5 pass the value in 161 when stl is the present state, or the value in 179 when the present state is a valid state and not equal to stl and stEr.

180 takes the value from element 5 to Latch element 11, which passes this value if the present state is any valid state of the process. This value goes to AREG-LSD-DR element 17, where it is stored and passed to 170. SUBTRACTOR FD element 3 takes the LSB of Dr and subtracts this value from number zero, and without considering sign, its output is termed as Flag Digit (FD) and goes to MULTIPLEXER FD element 9, which lets that value passes through it if Dr is different from number zero else passes zero. The New Divisor (NDr) is calculated in ADDER NDr element 13, where one input comes from ADDER FD MSD element 12, which sums the FD from element 9 and the value of the product of number 10 by the MSB of Dr, this multiplication is done in order to put these bits with the correct ponderation before adding them, this is equivalent to a concatenation of both numbers, the result of this operation goes through bus 198. ADDER DR ZeroTest element 15 takes the MSB and the LSB of Dr and adds them; this result goes to EQUAL testZeroDr element 22, where are compared with number zero, this result goes through bus 201. If a value in 201 is false, then MUX_NDr element 21 passes the value in bus 198 to 200, else the value in bus 199 goes to 200. The true value in bus 201 indicates that the divisor is zero and indicates zero error for division by zero divisor.

ADDER nlter element 8 adds 1 to n iter (counts iterations of the process) and passes this value to MULTIPLEXER N iter element 14 through bus 177; this happens for state stl3. The value of n iter also goes through bus 175. For state st3, element 14 passes the value 1 for n iter, and for the state, st5 passes the value 2. For other states, element 14 passes the previous value stored in register AREG_N_iter element 24, which receives from LATCH_N_iter element 23 the current value of element 14 when ROM - State selector element 16 is in one of the valid states of the process. MULTIPLIER element 18, together with ADDER element 19, concatenate the MSB and LSB of Dr in one number. MULTIPLIER element 20 together with ADDER element 26 concatenate MSB and LSB in one number. The result of concatenation goes from element 19 to LESS THAN element 25, where it is compared with NDd (NDd < Dr). Line 187 takes this result to let MULTIPLEXER element 27 passes the value in bus 188 to bus 189 if this comparison is false or the value in bus 190 if the comparison is true. The value in bus 189 is the new value of DR1. This comparison's result is later also used to select the next state. A true value in 187 indicates that the Net Dividend (NDd) is less than Divisor (Dr); with this, the residue for the operation is NDd, and the next state will be stl 9. A false value indicates that the Net Dividend (NDd) is greater than Divisor (Dr), then it is necessary to calculate the residue and Additional Quotient (AQ) according to the USP-Awadhoot technique, and the next state will be st20a. The value in DR1 is Dr as one number. DR1 is then used to calculate the Additional Quotient (AQ).

Referring now to Fig.4, Circuit Description Sheet 3, which is also termed as input stage 2 for the divider, illustrating dividend selection circuit part of dividend and divisor selection circuit and modified divisor and number of zeros canceled selection circuit in accordance with an embodiment of the present invention. The MUX NDr SIG element 49 receives the value of bus 200. This value is the New Divisor (NDr). The output of element 49 goes to LATCH NDr element 52, and the output of element 52 goes to AREG NDr element 57, which stores the value of NDr and feeds this value to most of the inputs of element 49 through bus 199. Elements 49, 52, and 57 manage and store the value of NDr. The ROM - State selector element 50 worked as in charge of enabling element 52 for all the valid states of the process. Bus 163, present state, selects appropriate input from element 49. For most states, the NDr value does not change. But for stl, if Dr is not equal to zero, it will pass the value from bus 200, the calculated NDr.

For stEr element 49 sets its output to zero. Bus 199 takes the value of NDr to LESS THAN element 62, and NDr is compared with 100. Its result is taken to selector port of MULTIPLEXER element 66, through bus 242, which passes the value of MSB of NDr if this comparison is true, else passes the value 1, and this value is considered the Modified Divisor (MDr) value, according to the USP-Awadhoot technique to find the value of MDr. Value of MDr goes through bus 244. In one of the inputs of MUX Drl element 51, the value DR1 from bus 189 is received. When bus 163 present state is stl7, this value is transferred to the output of element 51. When bus 163 is stEr, the output of element 51 is 0.

For other valid states, element 51 keeps the current value of Drl using LATCH Drl element 55 and AREG Drl element 58 to store the value of Drl. Element 58 passes the currently stored value of Drl through bus 190 to element 51 and other parts of the circuit. ROM - State selector element 54 allows element 55 to pass the value of Drl to element 58 for any valid state of the process. MUX Dd l element 56, LATCH Dd l element 59, and AREG Dd l element 63 manage and store value of MSB of the Dividend (Dd). MUX Dd O element 61, LATCH Dd O element 65, and AREG Dd O element 67 manage and store the value of LSB of the Dividend (Dd). Elements 56 and 61 output the value 0 when bus 163 is the state stEr. When bus 163 present state is stl, they pass the value received from bus 166. For others, valid states they keep the current value.

ROM - State selector element 53 enables element 59 when bus 163 is one of the valid states of the process. ROM - State selector element 60 enables element 65 when bus 163 is one of the valid states of the process. The output of element 63 goes through bus 236 to MULTIPLIER element 68 to get the product of MSB of Dd by 10 in order to be added to LSB of Dd and get the concatenation of both values. The product goes through bus 246. Element 58 output, bus 190, is used as the subtrahend for SUBTRACTOR element 64, where the minuend is bus 240, and its result goes through bus 250, as part of the process to find Additional Quotient (AQ), st20b of the USP- Awadhoot technique. Bus 250 reaches one input of MULTIPLEXER element 69. The other input of this element is bus 240 that carries the current value stored of temp. If the value of line 253 is True, then element 69 passes the value from bus 250; else passes the value of bus 240; this value will be the new value of temp and goes through bus 251. Multiplexer element 70 receives the buses 240 and 186. Depending on line 187 value, it passes value in bus 240 if it is true or the value in bus 186 if it is false. Its output goes through bus 252. The value in temp is later used to calculate the residue according to the USP-Awadhoot technique.

Referring to Fig. 3, Circuit Description Sheet 2, also termed the status check stage, illustrates the dividend grouping circuit and iteration and condition check circuit. The dividend groups and quotients of the dividend groups termed Group Quotient (GQn) are stored and updated. G_Q element in the circuit is related to Group Quotient (GQn); these groups are part of the USP- Awadhoot technique. The width of dividend groups is related to the number of zeroes canceled during obtaining Modified Divisor (MDr). In the embodiments of the present invention, the element details are explained for two dividend groups, but the USP-Awadhoot technique can be used with more dividend groups like 4, 6, etc., depending on the input data size. The elements MUX G Q l element 36, LATCH G Q l element 40, and AREG G Q l element 42 manage and store the value of Group Quotient 1 (GQ1), the quotient obtained for the most significant groups of dividend digits. Rom State selector element 37 enables element 40 allow to pass the value in 220 from element 36 to element 42 through 222 for all valid states. The elements MUX G Q 2 element 35, LATCH G Q 2 element 39, and AREG_G_Q_2 element 41 manage and store the value of Group Quotient 2 (GQ2), which is the quotient obtained for the less significant groups of dividend digits. Rom State selector element 38 enables element 39 to let pass the value in 218 from element 35 to element 41 through 223 for all valid states except stEr. Element 35 and 36 are set to zero when st3 is present at 163. When MDr is greater than the value of the first dividend group, then in state st5, element 36 also sets zeroes for its outputs according to USP- Awadhoot technique, which means that Modified divisor (MDr) is greater than the value of the first dividend group. Also, when stEr is present, element 36 has zero in its output. For any value of bus 175, MUX_G_Q_ 1 1 element 32, MUX_G_Q_1_2 element 33, and MUX_G_Q_1_3 element 34 pass the value that is already present in element 36. It represents the number of iterations, except when this value is 1, which means that the process is currently running iteration number one and, according to the USP-Awadhoot technique, dividend group number one is being evaluated. MUX_G_Q_2_1 element 29, MUX_G_Q_2_2 element 30, and MUX_G_Q_2_3 element 31 pass the value that is already present in element 35, for any value of bus 175, which is the number of iterations, except when this value is 2, which means that the process is currently running iteration number two and, according to USP- Awadhoot technique, dividend group number two is being evaluated. Element 36 puts zero as the value present at its output, coming from element 34 when the number of iterations is one in bus 175 and the present state is st8 in bus 163. Element 33 passes the actual value of the first Group Quotient (GQ1) less by one, this value comes from SUBTRACTOR element 47 through bus 212, and element 36 selects this value as the new Group Quotient (GQn) when the present state is stl 1. Element 47 is also used when the second iteration is being processed. MUX_G_Q_10R2 element 43 selects which value goes to element 47, depending on the current iteration number. If the iteration number is one, then select bus 216, which is the value present in the first Group Quotient (GQ1). But if the number of iterations is two or higher than one, then selects bus 207, which is the value of the second or further group (s) quotient. According to USP- Awadhoot technique, in order to find a Group Quotient (GQn), it is necessary to multiply the Modified Divisor (MDr) by the current iteration Group Quotient (GQn) and compare this product with the value of Net Dividend (NDd) if the product is less than Net Dividend (NDd) then the current value of Group Quotient (GQn) is increased by one, this is done through ADDER element 28 which feeds this value to elements 35 and 36 through elements 30 and 36 respectively, and the multiplication and comparison are executed again, if the comparison results in a product greater than Net Dividend (NDd) then the value of Group Quotient (GQn) is decreased by one, and the process of increasing current Group Quotient (GQn) stops, this value goes to elements 35 and 36 through elements 31 and 35 respectively. And if the comparison results than both values are equal, then the increase of Group Quotient (GQn) value also stops, and the current Group Quotient (GQn) value is not modified. MULTIPLEXER element 44 passes the value of the current second Group Quotient (GQ2) or the results of this value less one, which is coming from 47, and MULTIPLEXER element 45 does the same for the second Group Quotient (GQ2). These values reach MULTIPLEXER element 48, which passes Group Quotient one or two (GQ1 or GQ2) depending on the current number of iterations. This value is passed through bus 228 and used in multiplication with MDr in order to calculate Residue / Remainder, according to USP- Awadhoot technique.

Referring now to Fig. 5 Circuit Description Sheet 4, which is also termed an intermediate stage, illustrating modified divisor and number of zeros canceled selection circuit and residue or remainder circuit part of result circuit according to an embodiment of the present invention. This part work as in charge of managing the Modified Divisor (MDr) value, calculates residue to be passed to other stages, and passes the values of the dividend groups. MUX MDR element 71 passes the value of MDR coming from bus 244 when the present state is st3 to bus 258. For other states, element 71 passes the value stored in AREG MDR element 79, and this value comes from LATCH MDR element 76. Element 76 takes the value from bus 258 when ROM - State selector element 72 receives from bus 163 any valid state of the process used in the USP- Awadhoot technique. MULTIPLIER element 83 takes the value of MDr from bus 206. It multiplies it with the value of bus 228, Group Quotient (GQn), and this product goes to SUBTRACTOR element 88, where it is used as the subtrahend. The minuend is the Net Dividend (NDd) value coming from bus 186 in order to calculate the residue (state stl 1). LATCH temp element 77 and AREG temp element 80 store the value of signal temp. This signal is used to calculate the Additional Quotient (AQ) according to the USP- Awadhoot technique. The stored value of temp in element 80 goes through bus 240 to MUX TEMP element 75, which will pass this same value to its output for any valid state except for states stl 1, passes a value from bus 252, and for state st20b, passes a value from bus 251. Value from 252 is the same temp value if NDd < Dr else; this value is NDd. According to USP- Awadhoot technique, which is detailed for the final iteration, if the last NDd is less than Dr then NDd is the residue. Else Additional Quotient (AQ) needs to be calculated. Value in 251 if DR1 is less or equal to temp value, then 251 is temp value - DR1 else value in 251 is current temp value. ROM - State selector element 73 enables element 77 to pass the value from bus 261 to bus 264, element 80, for any valid state of the process. Bus 240 also goes to LESS THAN EQUAL element 85, and if bus 190 (DR1) <= bus 240 (temp) then in MULTIPLEXER element 87 let pass current residue value from bus 269, else element 87 passes temp value through 271 as the new value for residue according to USP- Awadhoot technique, state st20b. MULTIPLEXER element 89 passes the residue value to the next stages. EQUAL element 84 evaluates bus 186 (NDd) and bus 185 (Dr) and sends the result through bus 267 and reaches element 89. If NDd = Dr, then 89 passes 0 as residue, also selects next state as st21 in other parts of the circuit, else next state will be stl7, and element 89 passes the current value of residue through bus 273. LATCH G Dd element 86 and AREG G Dd residue element 90 stores the value of the first dividend group, this value goes through bus 274, the output of element 90, and this bus is the same as bus 278 and goes to most of the inputs of MUX G Dd element 82, which passes this value to his output, bus 279, for all valid states of the process except when the present state is st3. For this state, element 82 takes the value from bus 265 as the value for the first dividend group. ROM - State selector element 81 enables element 86 to pass the value in its input to its output, bus 275, which goes to element 90. Line 242 indicates to the MULTIPLEXER element 78 if it has to pass the value from ADDER element 74, which is the two digits of Dr when line 242 is zero or passes the value of the first digit of Dr, when line 242 is one. Line 242 is one when the value of NDr is less than 100. The output of element 78 goes to bus 265. MULTIPLEXER element 91 passes Dd 4 LSB to bus 277 when line 242 is one else passes 0.

Referring now to Fig. 6, Circuit Description Sheet 5 is also termed an intermediate stage, a part of the processing circuit stage, illustrating a circuit that manages and stores the second Dividend Group and Remainder/Residue value. MUX Residue element 92 updates and pass the value of residue to its output, bus 280, LATCH Residue element 96 receives this value and passes it to AREG Residue element 98 where it is stored. Element 96 passes the value when ROM - State selector input present state is any valid state of the process. Element 92 passes a zero value when the present state is stl2, stl6, or stEr. For most of the valid states of the process, the value of residue is kept. When the present state is st5, element 96 passes the value of the first dividend group coming through bus 274. When the present state is stl l, element 96 passes the value calculated from NDd - current iteration Group Quotient (GQn) * MDr. When the present state is stl 5, the value coming to element 96 can be zero if NDd = Dr, else it is the current value of residue. When the present state is stl 9, element 96 passes the value of NDd coming through bus 186. When the present state is st20b, what is coming from bus 271, which if Drl<=temp is the current value of residue else is the temp value. MUX_G_Dd_2 element 95 manages the value of the second group dividend. For almost all valid states, element 95 passes the current value of the second dividend group except when the present state is st3. For this case, element 95 passes the value coming through bus 277, which is the LSB of Dd when NDr < 100, else the value is zero. LATCH_G_Dd_2 element 97 receives the output from element 95 and passes it to AREG_G_Dd_2 element 99 for storing. This element passes this value for almost all the inputs of element 95. ROM - State selector element 94 enables element 97 for all valid states of the process. MULTIPLEXER element 100 passes the value of the first dividend group when the number of iterations bus 175 is one and passes the value of the second dividend group when the number of iterations is two. MULTIPLIER element 101 multiplies the value of residue by 10 in order to add this result with the value at the output of element 100, and this addition is done in ADDER element 103, concatenating residue with the value of dividend group, which is termed as Gross Dividend (GDd) of dividend group. This result goes through bus 293. MUX FD element 104 manages the value of FD. For almost all valid states of the process outputs, the current value of FD. When the present state is stl, element 104 passes the value coming from MULTIPLEXER element 102. This value coming from the calculation of FD in stl (zero when LSB of Dr are zeroes) or the calculation of 10 minus the value of LSB of Dr. ROM - State selector element 105 enables the latch used for FD for all valid states of the process.

Referring now to Fig. 7 Circuit Description Sheet 6, which is also termed as an intermediate stage as another part of the processing circuit stage, illustrating the part of the circuit that manages the value of the gross dividend, stores value of FD, and manages and stores values of NDd and value of n, i.e., iteration count. MUX Gross Gd element 106 manages the value of the Gross Dividend (GDd) of the dividend group. Element 106 gives the current value of Gross Dividend (GDd) of dividend group as output for almost all valid states except when the present state is st6. It passes the value coming from bus 293, which is the calculation of Gross Dividend (GDd) of dividend group, according to the USP-Awadhoot technique, i.e., concatenates residue generated by previous dividend group with a value of current dividend group. LATCH Gross Gd element 111 and AREG Gross Gd element 114 stores the current value of Gross Dividend (GDd) of the dividend group. The output of element 114 goes through bus 299.

Element 106 receives this output in all but one of its inputs, selected for present state st6. ROM - State selector element 108 enables element 111 to pass the value coming from element 106 to element 114 for all valid states of the process. SUBTRACTOR element 107 subtracts one from the value of the number of iterations coming from bus 175. MULTIPLEXER element 110 receives this result, and according to this value, let pass the value from bus 216, which is the first Group Quotient (GQ1), when the output of element 107 is one of the values coming from bus 207, which is the second Group Quotient (GQ2) when the output of element 107 is two. LATCH FD element 109 and AREG FD element 112 store the value of FD. The operation to get NDd for the number of iteration different than one, then the Gross dividend (GDd) of the dividend group + FD * Group Quotient (GQn) (n iteration -1). When the number of iterations is different from one, it is done by MULTIPLIER element 113, which multiplies the previous Group Quotient (GQn) by FD and ADDER element 115, which adds this result with Gross Dividend (GDd). This result goes through bus 304 to the input selected by default of MULTIPLEXER element 116, the only case where element 116 passes the value present in its other input, coming from bus 299, is when the value of bus 175 is one. The result from element 116 goes to one input of MUX NDd element 117, which for the rest of its inputs has the current value stored of NDd. Only when the present state is st7, element 117 takes the value from element 116 and passes it to its output. For the rest of the valid states, element 117 passes the currently stored value of NDd. LATCH NDd element 122 and AREG NDd element 124 store the value of NDd. The output of element 124 goes through bus 186 to all but one of the inputs of element 117. ROM - State selector element 119 enables element 122 to pass the value from element 117 to element 124 for all valid states of the process. MULTIPLEXER element 118 passes the value one or two to MUX n element 120. It passes the value two when its select input is one, else passes value one. The select input is the value coming from line 242. LATCH n element 123 and AREG n element 125 store n value, which is the number of dividend groups. The output of element 125 goes through bus 317 to all but one of the inputs of element 120. Element 120 passes the current value of n for all valid states of the process, except for state st3 when it passes the value coming from element 118. ROM - State selector element 121 enables element 123 to pass the value from element 120 to element 125 for all valid states of the process.

Referring now to Fig. 8, Circuit Description Sheet 7 is also termed the pre-output stage or a part of the post-processing circuit stage. This part of the circuit manages and stores the finite state machine's state and helps manage the Additional Quotient (AQ) value. MUX next st element 139 manages the value of the state in the finite state machine that controls the process; also, this element receives the signal from the input FD enable. The output of element 139 goes through bus 339 to the D input of AREG next st element 141, which stores this value as the value of the next state. This value goes through bus 345. Element 141 also receives the signal reset in its clear input. If signal reset is one, then the output of element 141 is zero, taking the process to state stO; this is an asynchronous reset. The select input of element 139 is connected to bus 163, which carries the value of the present state. Depending on the present state, an input of element 139 is selected, and that input carries the value for the next state that will be the value of the present state in the next cycle. The default selected value is 0. When the Select value is zero, input 10 is selected. This input carries the value of FD enable, which could be zero. The division module is not enabled, or one, and then the division module is enabled. When value one is in 10, then this value goes to bus 163 through element 141, this produces than element 139 selects input II in the next cycle, else zero value goes to 163. This value determines which input will be selected for the next cycle; if it is zero, then the selected input is still 10; else selected input will be II. Input II receives its value from MULTIPLEXER element 134, which can pass the value of state st3 or stEr, depending on the value of line 201. If Divisor (Dr) is zero, then line 201 will select stEr, the value to be passed to element 139; else, the value will be the value of st3. If the value received by element 139 is stEr, then input 121 is selected where the value for stEr is set, making that the next state is also stEr. When the value received by element 139 is st3, then input 12 is selected where the value comes from MULTIPLEXER element 131, which passes the value of st5 if MDr is greater than first group dividend else passes the value of st6, GREATER THAN element 126 does this comparison. If the present state is st5, then element 139 selects 13, which, in the next cycle, passes the value st6. When the present state is st6, then input 14 of element 139 is selected, which has the value of st7, and the element passes it for the next state.

When the value of the present state is st7, then input 15 of element 139 is selected, which is connected to the output from MULTIPLEXER element 132 in association with GREATER THAN EQUAL element 127. Element 127 generates a control signal to pass the value of the iteration's state number. If the comparison result of element 127 is less than the number of group dividends, element 132 passes the st8 state value; else, MULTIPLEXER element 132 passes the stl4 state value. When the value of state st8 is the present state, element 139 selects input 16, which has the value for state st9. When the value of state st9 is the present state, element 139 selects input 17, which has the value coming from MULTIPLEXER element 133, which passes the value of state stlO when the value calculated from the multiplication of the current Group Quotient (GQn) by MDr is less than NDd, LESS THAN element 129 does this comparison. Its output goes to the select input of element 133. If this calculated value is greater than NDd, element 133 passes the value of state stl l, GREATER THAN element 128 does this comparison. Its output goes to MULTIPLEXER element 130, which takes its value to element 133. Still, if the calculated value is equal to NDd, then element 133 passes the value of state stl2. When the present state is stlO, then element 139 selects input 18, which has the value of state st9. When the present state is stl 1, then element 139 selects input 19, which has the value of state stl3. When the present state is stl2, then element 139 selects input 110, which has the value of state stl3. When the present state is stl3, then element 139 selects input II 1 which has the value of state st6. When the present state is stl4, then element 139 selects its input 112 which has the value of ROM - State selector element 135, which passes the value of state stl 5 when NDd is not equal to zero or state stl6 when NDd is zero. The value of NDd comes through bus 186.

When the present state is stl 5, then element 139 selects its input 113 which has the value coming from MULTIPLEXER element 136, which is the value of state st21. When NDd current value is equal to Dr else, the value is state stl 7. When the present state is stl6, then element 139 selects its input 114 which has the value of state st21. When the present state is stl 7, then element 139 selects its input 115 which has the value coming from MULTIPLEXER element 137, which passes the value of state stl 9 when NDd is less than Dr else passes the value of state st20a. When the value of the present state is stl9, then element 139 selects its input 116 which has the value of state st21. When the value of the present state is st20a, then element 139 selects its input 117 which has the value of state st20b. When the value of the present state is st20b, then element 139 selects its input 118 which has the value coming from MULTIPLEXER element 138, which is the value of state st20a; the value of DR1 is less than or equal to the value of temp else the value is state st21. When the value of the present state is st21, then element 139 selects its input 119 which has the value of state st22. When the value of the present state is st22, then element 139 selects 120, which has the value of state st22. When the value of the present state is stEr, element 139 selects its input 121 which has the value of state stEr. The default value selects input 122 of element 139, which has the value of zero. ADDER element 140 adds one to the value of the Additional Quotient (AQ). MULTIPLEXER element 143 selects the new value of Additional Quotient (AQ) coming from element 140 when line 253 is one else keeps the old one. MULTIPLEXER element 142 outputs the value one when line 267 is one else output the current value of Additional Quotient (AQ) coming from bus 340.

Referring now to Fig. 9 Circuit Description Sheet 8 is also termed the output stage as another part of the post-processing circuit stage. This part of the circuit manages and stores the value of Additional Quotient (AQ) and stores and validates the system's output. MUX AQ element 145 manages the value of Additional Quotient (AQ). For most of the valid states, the element 145 passes the current value of Additional Quotient (AQ) to its output, except for states stl4, stl6, stl9, stEr, for this state, the output of element 145 is zero, and for states stl 5 the value comes from bus 344, and for state st20b the value comes from bus 343. The output of element 145 goes to the input of LATCH AQ element 146, which passes this value to AREG AQ element 147 for storing. ROM - State selector element 144 enables element 146 for any valid state of the process. ADDER - AQ Partial Result element 148 adds the Additional Quotient (AQ), which is obtained from element 147, to the partial result (Concatenation values of all iteration Group Quotient (GQn)s) coming from bus 216 in order to calculate the result, the Quotient (Q). The output signal valid ouput is set when the component OR Validator of output element 156 receives a one from EQUAL element 149 or EQUAL element 150. Element 149 outputs a one when the present state is st22. Element 150 outputs a one when the present state is stEr. ROM - State selector element 151 enables Output latch - Results in element 157 when the present state is st21 or stEr. MULTIPLEXER - Result element 152 passes the value from element 148 if the present state is st21; for any other value of the present state, this element passes the value zero. This value goes to the input of element 157. MULTIPLEXER - Residue element 153 passes the value of the calculated residue when the present state is st21, sending this value to Output latch - Residue element 159, which outputs this result when ROM - State selector element 155 enables it. Element 155 enables element 159 when the present state is st21 or stEr. Output register - Error element 158 outputs a zero value unless set by ROM - State selector element 154. Element 154 sets element 158 when the present state is state stEr.

Referring now to Fig. 10 FSM state diagram depicting the states involved in the proposed concept used for dividing dividend by divisor in accordance with an embodiment of the present invention. The inputs are the Dividend (Dd) and Divisor (Dr), besides the control inputs (reset, fd enable and clock). The FSM stages for the proposed circuit comprising of stO: The device stays in stO until fd enable is 1 and RST = 0, and it can return to stO at any moment when RST = 1 (asynchronous Reset). stl: Takes the data from the inputs and stores each input. The most significant bits are stored as a hexadecimal integer number. The less significant bits are stored as another hexadecimal integer in an array of integer elements for the dividend; the same happens for the divisor. In this state, FD is found where only the less significant divisor element is taken into account. After this, NDr is calculated. Also, if the divisor is zero in this state, then stEr is selected as the next state, or else st3 is selected. st2: not used currently, reserved for future improvements. st3: NZC and MDr are obtained. Depending on NZC, we have one, two, or multiple dividend groups (G_Dd). If MDr is greater than first G_Dd, then the next state is st5, and the number of iterations is set to 2; else st6 is selected, the number of iterations is set to 1. st4: not used currently, reserved for future improvements. st5: First element of the array G_Q, where the partial results are stored, is set to 0 because MDr > first G_Dd and the residue is the first element of G_Dd, and the number of iterations (n iter) is increased to 2. The next state is st6. st6: Gross Gd is calculated by multiplying the residue by 10 and adding the G Dd(n iter); this is like concatenate these numbers. The next state is st7. st7: NDd is calculated. If n iter =1 then NDd = Gross Gd else NDd = Gross Gd + FD*G_Q(n_iter-l). G_Q is an array where Group Quotient (GQn)s are stored. The next state is stl4 if n iter >= than the number of groups; else Next state is st8. st8: G Q(n iter) =0. The next state is st9. st9: GQ MDR = G Q(n iter) *MDr. If GQ MDR < NDd, then the next state is stlO else, if GQ MDR > NDd, then the next state is stl 1 else stl2. stlO: G Q(n iter) = G Q(n iter) + 1. The next state is st9. stll: G Q(n iter) = G_Q(n_iter)-l because the previous gave a bigger result that expected. The residue is then NDd - G Q(n iter) *MDr. The next state is stl3. stl2: Residue is zero. The next state is stl3. stl3: n inter = n iter + 1. The next state is st6. stl4: Starts calculation of Additional Quotient. AQ = 0. If NDd = 0 then next state is stl6 else stl5. stl5: If NDd = Dr then Residue = 0, AQ =1 and next state is st21 else next state is stl7. stl6: Residue = 0, AQ = 0. The next state is st21. stl7: If NDd < Dr then next state is stl9 else st20a and DR1 = Dr. stl8: not used currently, reserved for future improvements. stl9: Residue = NDd, AQ = 0 next state is st21. st20a: Just used to set next state as st20b. st20b: If DR1 <= temp then temp = temp - DR1, AQ = AQ+1, next state is st20a else Residue = temp and next state is st21. st21: To get the result, the value G_Q (1) + AQ is converted to a logic vector. Same with the residue. st22: To hold the result values until reset is activated or new set of input operands are provided. stEr: Error output is set 1. Next st is stO. When present state is stEr or st22 then valid_output = 1.

Referring now to Fig. 11, Main Circuit Flow chart and Fig. 12 Sub Circuit Flow explains signal flow through a complete divider circuit according to an embodiment of the present invention. The complete flow of the circuit is divided into two groups of processes; one is termed the main group, representing the main process of the conversion according to an embodiment of the present invention described in Fig. 11. Another group of the process is termed a subprocess of finding out Remainder/Residue and Additional Quotient (AQ) according to an embodiment of the present invention described in Fig. 12. Main circuit flow and subcircuit flow are derived from the basic idea explained in Fig.1 for dividing dividend by divisor according to an embodiment of the present invention. After providing all inputs, at step 416 circuit obtains the Divisor (Dr) and Dividend (Dd), then Divisor (Dr) undergoes the condition check for invalid condition, i.e., divide by zero. Upon detecting this stage, it indicates an error signal 418 derives from signal 457. In a false case, Divisor (Dr) is passed by 458 to step 419, where circuit obtains Flag Digit (FD) and New Divisor (NDr) follows the basic concept of obtaining Flag Digit (FD) and New Divisor (NDr) with respect to the Fig. 1 A step 399. Later in step 420, NDr and FD are used to obtain Modified Divisor (MDr), and the Number of Zeros Cancelled (NZC) follows the basic concept of obtaining Modified Divisor (MDr) and Number of Zeros Cancelled (NZC) with respect to the Fig. 1 A step 400. In step 421 of Fig. 11, based on the procedure given in Fig. 1A, step 401, the circuit performs dividend grouping depending on the count of NZC. The count of iteration required for conversion is equal to the count of groups have made based on the count of the Number of Zeros Cancelled (NZC). In step 422 of the Fig. 11, Dividend (Dd), Flag Digit (FD), and Modified Divisor (MDr) are arranged into the special tabular arrangement, which is named Awadhoot matrix, as shown in Fig. 13. Before starting up with the iteration process of the Awadhoot matrix, it sets the previous iteration Group Quotient (GQO) and previous Remainder / Residue (Rem-0) to the default value of zero to confirms that there is no previous remainder and quotient value at the initial stage or beginning stage.

Referring now to Fig. 13 Awadhoot Matrix explains the special tabular arrangement used by the circuit to perform division of Dividend (Dd) by Divisor (Dr) in accordance with an embodiment of the present invention. The special arrangement of rows and columns is termed as Awadhoot matrix, where each column represents a single iteration, and rows represent the process of conversion, which is the same for every iteration collectively termed as Common Calculation Process of iteration in Awadhoot Matrix. The common calculation process of iteration in Awadhoot Matrix is divided into fixed steps. Each step is given a specific name represented by an individual row in the Awadhoot matrix. Referring to Fig. 13 Awadhoot Matrix, every individual row from top to bottom is named after its specific process, which it performs as the top row is the first row named as iteration, which indicates the count of iteration in process, which is also referred to as column number. The second row is named the Dividend Grouping value, which shows the value of the dividend group used in every iteration.

The third row is named as Remainder / Residue (Rem-n), which shows the value of remainder for every iteration. The remainder value for the current iteration is obtained from the previous iteration. At initial consider remainder (Rem-0) equals to zero for the first iteration, which indicates no previous data at the beginning of conversion. The fourth row is named as Gross Dividend (GDd). Gross Dividend represents the concatenation of the value of remainder with the value of Dividend Group for the current iteration, i.e., Remainder (Rem-n) is starting from the resultant number connects the value of Dividend Group of the current iteration. The fifth row named as Product Term, which is obtained by-product of Flag Digit (FD) and previous iteration Group Quotient (GQn-1), shows the value of the product of Flag Digit (FD) and previous iteration Group Quotient (GQn-1), which is added to the Gross Dividend (GDd). The sixth row is named Net Dividend (NDd), which shows the result of adding product value derived from FD and GQn- 1 with Gross Dividend (GDd). The seventh row is named Subtract Term formed by multiple MDr whose value is less than or equal to Net Dividend (NDd) of the current dividend group. The value of Subtract Term is subtracted from the Net Dividend (NDd) of the current iteration. It is needed to check the value of MDr multiples should be less than the value of Net Dividend (NDd) before performing subtraction. The eighth row is the last row and named Group Quotient (GQn), which shows the value equals the count of multiple MDr, which is used in the previous row. It is considered as a Group Quotient (GQn) of the current dividend group, and the resultant value of subtraction is termed as Remainder or Residue for the next iteration. The result, i.e., Quotient (Q), is obtained by concatenating all Group Quotient (GQn) terms from the first iteration to the last iteration depending on the number of iterations or columns, i.e., result = Concatenate (Q1Q2.... Qn). The subtraction of multiple of MDr from NDr is considered the remainder in the next iteration. In the last iteration or column, we perform a process up to Net Dividend (NDd) row. Upon checking the condition for the last iteration value present at Net Dividend (NDd), the Quotient (Q) is obtained from the Partial Quotient (PQ), formed by concatenating all Group Quotients (GQn).

Step 423 of the Fig. 11 common calculation process of iteration started with concatenating remainder obtained from the previous iteration and the value of the present iteration dividend group. At the beginning of the first iteration, the previous remainder is considered zero representing the conversion process's initial condition. Later in the next iterations, this remainder value gets updated based on the previous iteration subtraction of Subtract Term from NDd. After setting initial conditions, the circuit stage checks for the MDr condition, where it finds whether MDr is greater than the Gross Dividend (GDd) of the current iteration or not. At this step, the circuit finds out the condition whether MDr is smaller than the value of current iterations Gross Dividend (GDd) or not. If MDr appears to be greater than the value of Gross Dividend (GDd), then signal 463 connects to step 424 of Fig.11, where it sets the Group Quotient of that iteration (GQn) to zero and GDd is transmitted to Remainder / Residue (Rem - n). After updating Qn and Rem-n values, it increases the iteration number by one or activates the next iteration to perform the Common Calculation Process of iteration as mentioned in Awadhoot matrix by signal 465 to summing point 425 of the Fig.11. Suppose the circuit verifies that MDr is not greater than Gross Dividend (GDd). In that case, signal 464 connects to step 425 of Fig.11 to perform the Common Calculation Process of iteration as mentioned in the Awadhoot matrix. Step 426 of the Fig.11 performs concatenation of previous remainder and value of dividend group of the current iteration. Later concatenated result is applied to step 427 by signal 467 obtain Net Dividend (NDd) as per the procedure mentioned in Awadhoot Matrix in accordance with an embodiment of the present invention.

At step 428 of Fig. 11, the circuit checks the iteration number, and if it comes to the last iteration, then it performs a condition check on obtained Net Dividend (NDd) through steps 438 to 447; this condition check is required when the circuit is working in the last iteration where we perform procedure up to Net Dividend (NDd). If NDd appears to be equal to zero, then step 438 sets Residue / Remainder and Additional Quotient (AQ) value to zero in step 439. If NDd appears to be equal to zero, then step 440 sets Residue / Remainder equals zero and Additional Quotient (AQ) value to one in step 441; else, step 443 activates the subprocess step 444 to find out the value of Residue / Remainder and Additional Quotient (AQ). Step 449 to 454 sub-process obtained Additional Quotient (AQ) and Remainder / Residue value. During subprocess, initialize count reference to zero, keeping track of how many times subtraction is performed, then subtract Divisor (Dr) from the last iteration Net Dividend (NDd) value and increment count by value one. If the subtraction result, i.e., sub result, is non-zero and equal or greater than divisor (Dr), continue subtracting Divisor (Dr) from Sub Result and increment count every time. We perform subtraction until we get the sub result zero or less than the divisor. If the sub result is zero or less than Divisor (Dr), then stop subtraction. This Sub result is termed as Remainder (R) / Residue, and the count is termed as Additional Quotient (AQ). To achieve the result, this Additional Quotient (AQ) is added with a value of Partial Quotient (PQ) obtained from concatenating Group Quotients (GQn) from group quotient row reading from LHS to RHS. Later the output 493 of Net Dividend (NDd) passes to final step 448 for calculating result by concatenating Group Quotients (GQn) as shown in Awadhoot Matrix. If step 428 of the Fig.11, circuit checks that iteration is not a final iteration, then the output is fed to step 429 to find out Group Quotient (GQn) and Residue/Remainder (Rem- n) of that iteration through step 430 to 437. Steps 430 431,432, 434, 436, and 437 are used to find out exact multiple of Modified Divisor (MDr), which is less than or equal to the value of Net Dividend (NDd) of current iteration to perform subtraction from current iteration Net Dividend (NDd) to obtain current iteration Group Quotient (GQn) and Residue / Remainder (Rem-n). Upon obtaining the current iteration Group Quotient (GQn) and Residue / Remainder (Rem-n), step 435 increases iteration count and connects the process at step 425 to perform the Common Calculation Process of iteration as mentioned in the Awadhoot matrix in accordance with an embodiment of the present invention. During the last iteration of the Awadhoot matrix procedure, when the NDd value is zero, Residue / Remainder (Rem-n) obtained is termed as Remainder (R); else, it will be derived from the Additional Quotient (AQ) calculation. If the NDd value is zero in the last iteration, then the final result or Quotient (Q) is equal to the Partial Quotient (PQ) obtained by the concatenating Group Quotient (GQn)s. Else final result or Quotient (Q) is derived from the Additional Quotient (AQ) process. Remainder / Residue (Rem-n) value in the last iteration or as explained in the Additional Quotient (AQ) calculation is the same as the Remainder (R), whereas, in the waveforms, it is represented as Rem Residue signal. Similarly, the Quotient (Q) is formed by concatenating all Group Quotients (GQn), or as explained in the Additional Quotient (AQ) calculation, and the waveforms it is represented by the Q Result signal. Referring now to Fig.14. t is -H. Clock performance analysis illustrates the clock cycles required to execute a particular combination of operands (divisor, dividend) by the proposed divider circuit based on the USP-Awadhoot algorithm. To represent the data in a common format, we distinguish the dividend range in three sections showing a low range of dividend values in the first region named as dividend range 00, suggesting that the dividend had a half-filled four-bit values or one digit lower hexadecimal values; a mid-range of dividend values in the second region named as dividend range 80, suggesting the range from half-filled four-bit values to six-bit value or lower two-digit hexadecimal values; a high range of dividend values in the third region named as dividend range FF, suggesting the range from six-bit values or lower two-digit hexadecimal values to full eight-bit values or higher two-digit hexadecimal values. During each clock cycle processing unit can perform basic operations like fetching instruction or data, accessing memory, reading, or writing data.

In many cases, the processing unit requires multiple clock cycles to complete a single process. Depending on the occurrence of clock cycles, the processing unit's frequency is calculated, which is also termed as cycles per second or frequency. Here the clock frequency is considered system frequency or divider's working frequency. The clock frequency is also termed as a reference point to execute different instructions during particular operation implementation. The frequency of a processing unit is also known as the processor's clock speed. At the same time, the clock speed is important in determining the processor's overall performance. Therefore, it indicates that the study of clock cycles required for particular conversion is important. A comparative study of clock performance analysis of the broad range of dividend and divisor is presented in Fig. 14. A-H. A complete range of two dividend group divisor-dividend operands range, i.e., 65K combinations, is considered and presented a clock performance analysis in the present embodiment of the invention. The number of operand combinations depends on the input operands width, i.e., divisor and dividend width.

The results generated from this clock performance analysis states that the present invention required a variable number of clock cycles to perform division operations on the particular operands provided at a particular time. It shows that the proposed divider circuit requires the lowest clock cycles (0 clock cycles) when operands show invalid conditions. The invalid condition suggests that the divisor value is zero, and the division by zero is giving an indefinite condition causing to generate the invalid condition. An exception to the invalid condition exists with dividend value zero; when the input operands value indicated dividend and divisor values both are zero, then the proposed divider circuit takes a little bit more clock cycles (17 clock cycles) to finish the execution. The considerable reason behind this tells us that the circuit first executes the detection of dividend value to indicate it as non-zero value, and if it detects dividend as zero value, then it sets the temporary output to zero and then checks for the divisor for a non-zero value. If it detects a non-zero value, then the final answer is zero, but in the case of zero, the final result has to change to an invalid result by generating an error signal which requires extra clock cycles to execute error signal generation.

The highest clock cycles required for computing operands are two hundred and seventy-five clock cycles for the lowest divisor and highest dividend value combination, indicating requirements of more iterations to complete before reaching the final result. When the divisor value is nearer to the dividend value, then the count of clock cycles required to execute division is less, and the required values of average maximum clock cycles stay in the range of twenty-eight to sixty-three clock cycles. When the distance between divisor value and dividend value is less, then the required average lowest clock cycle value stays in the range of thirteen to twenty-four clock cycles. The lowest clock cycles (7 clock cycles) are required when the divisor value is unity; in this case, as the dividend value is prior confirmed to be a non-zero value and no iteration is performed, the final result value is calculated directly after confirming the divisor value is unity. Mid-range operand combinations show the clock requirement in the range of fifteen to thirty-five clock cycles. The divider circuit clock performance clearly shows the variable latency due to variable clock cycles required for different operand combinations in the proposed divider implementation and execution.

Referring now to Fig. 15A to Fig. 15L illustrates the waveform analysis of the invention under various input operand conditions. Waveform analysis studies the nine-signal data to provide a clear idea about the proposed divider's working condition based on the USP-Awadhoot division algorithm. The nine signals, such as reference the clock (CLK), dividend (Dd), divisor (Dr), enable (Fd enable), quotient (Q Result), the remainder (Rem Residue), computation completion acknowledgment (Valid O/P), error (Error) and reset (RST) required for waveform analysis are distributed into five different groups depending on the nature of signal: reference group, I/P operands group, control group, O/P results group and indicator group. As discussed in the previous section of circuit clock performance analysis, different dividend and divisor combinations require the different clock cycles to operate; reference group clock signal (CLK) provides the timing reference signal for computation execution. The reference clock signal's period value is dependent on the working frequency; thus, the higher the frequency lower the clock period value. I/P operands group consists of the dividend (D_d) and the divisor (Dr) signals indicating the dividend and divisor value. The Control group consists of enable (Fd enable) and reset (RST) signals to provide start and end control of the computation process. The indicator group consists of computation completion acknowledgment (Valid O/P) and error (Error) signal, indicating the completion of computation and alerting about any invalid working condition or wrong execution. The last and important is that the O/P results group consists of the quotient (Q Result) and remainder (Rem Residue) signal providing the quotient value and remainder due to the division operation performed by the proposed divider based on the USP-Awadhoot algorithm. Fig.15. A indicates the proposed divider's reference working waveform diagram concerning the initial working condition. The proposed divider's initial working waveform is mainly sectorized into an idle state, the initialization state, the operation state, and the next state. The idle state shows the proposed divider circuit's non-working or stationary condition and beginning state when just a power supply is provided to the circuit after shutting down. In the idle state, the clock signal (CLK) continues to generate the reference signal, value of I/P operands group's dividend (Dd), and divisor (Dr) signals are in high impedance tri-state condition. Control group signals enable (Fd enable) and reset (RST) both possess low logic values suggesting no operation. Similarly, the value of indicators group and O/P results group's quotient (Q Result) and remainder (Rem Residue) signals are in high impedance tri-state condition suggesting stationary work condition. The initialization state indicates the next stage after applying the enable (Fd enable) control signal to the proposed divider. In the initialization state, the proposed circuit resets the O/P results group signal value to the initial values of 00H, suggesting no result at starting later it fetches the dividend (Dd) and divisor (Dr) data values from input data lines and stores them in input operand registers for further computation as described in previous sections, and indicators group's computation completion acknowledgment (Valid O/P) and error (Error) signals are set to logic low values indicating no computation operation is performed yet. The reset (RST) signal value is set to low logic, indicating an inactive reset signal which allows continuing computation process to execute division operation and compute final O/P result values. The proposed divider circuit computes the quotient (Q Result) during the operation state, and the remainder (Rem Residue) signals final value. After completing the computation operation, depending on data computation completion, acknowledgment (Valid O/P) and error (Error) get updated and validates the computation and O/P results, values are correct or incorrect. At any instance, if a logic high signal activates a reset (RST) signal, then the proposed divider circuit suspends its current state of computation operation and resets it to the initialization state. Thus, depending on the control group signals' values, the proposed divider circuit is ready to execute the next state. Fig.15. B illustrates the waveforms of the proposed divider circuit in the divide by zero condition, giving the idea about different signal states during this condition's execution. Divide by zero is a special division condition, and it is named as an invalid condition. The proposed circuit performed the initialization of the quotient during the computation of divide by zero condition (Q Result). Initially, the remainder (Rem Residue) signals to zero value, later in the operation state of the computation circuit quotient (Q Result) state doesn’t change, but remainder (Rem Residue) signal and error (Error) signal is generated along with computation completion acknowledgment (Valid O/P) signal. It shows that the computation process on operands is completed. An error is encountered due to the presence of an invalid condition. Thus, we get zero states on quotient (Q Result) and remainder (Rem Residue) signals at the end of the computation. Fig.15. C illustrates the waveforms of the proposed divider circuit when the enable (Fd enable) signal is inactive. Fd enable signal is and controlling input for the proposed circuit to control the execution of the proposed divider circuit. Fd enable is an active-high logic signal. When Fd enable has a low logic signal makes this control signal inactive, and the circuit does not provide any results even after the input operand data bus is available with dividend and divisor data.

Fig. 15D. illustrates the waveforms of the proposed divider circuit in condition one-digit hexadecimal dividend (four-digit binary) is divided by one digit hexadecimal (four-digit binary) divisor showing complete division condition with zero remainder. During this condition, the width of both dividend and divisor is the same. After applying Fd enable active high logic signal data available on the input, the operands data bus is transferred to the dividend and divisor registers, and further computation proceeds with the operation state. Once the result is calculated, output data is presented at quotient (Q Result) and remainder (Rem Residue) signals and stored in respective registers for further transmission. After that, the computation completion acknowledgment (Valid O/P) signal is activated, indicating the completion of the computation. Furthermore, suppose reset (RST) signal is activated in between execution of this state. In that case, computation stops working and resets the dividend and divisor register data from the input operand data bus. If the operand data is unchanged, it repeats the same execution process; else, it applies different processes depending on the nature of input operand data. Fig. 15E illustrates the waveforms of the proposed divider circuit in condition one-digit hexadecimal dividend (four-digit binary) is divided by one-digit hexadecimal (four-digit binary) divisor showing incomplete division condition with the non-zero remainder. During this condition, the working is the same as discussed in the previous condition except for the remainder's non-zero value.

Fig. 15F illustrates the waveforms of the invention in the condition of two-digit hexadecimal dividend (eight-digit binary) is divided by one-digit hexadecimal (four-digit binary) divisor showing complete division condition with zero remainder. During this condition, the working is the same as discussed in one-digit hexadecimal dividend (four-digit binary) is divided by one digit hexadecimal (four-digit binary) divisor showing complete division condition with zero remainder except for the width of dividend is more than that of the divisor. Similarly, Fig. 15G illustrates the waveforms of the proposed divider circuit in condition two-digit hexadecimal dividend (eight-digit binary) is divided by one-digit hexadecimal (four-digit binary) divisor showing incomplete division condition with the non-zero remainder. During this condition, the working is the same as discussed in the previous condition except for the tristate condition between quotient (Q Result) and the remainder (Rem Residue) signals initialization and finalization value calculation. As the dividend's width is higher than that of the divisor, it requires more iterations, as discussed in the previous section giving computations conditions where its results are in tristate condition for a certain period. Figs. 15H and I illustrate the waveforms of the proposed divider circuit in condition two-digit hexadecimal dividend (eight-digit binary) divided by two-digit hexadecimal (eight-digit binary) divisor showing complete division condition with zero remainder and incomplete division condition with the non-zero remainder. The basic working of this condition is the same as that of one-digit hexadecimal dividend and divisor with the same width, except the tristate between for the tristate condition between quotient (Q Result) and the remainder (Rem Residue) signals initialization and finalization value calculation. Figs. 15J and K illustrate the waveforms of the proposed divider circuit in the condition the divider value is set to unity and Fig. 15L illustrates the waveforms of the proposed divider circuit in the condition when both dividend and divisor values are the same. With the help of all working conditions, we can understand the proposed divider circuit's timing behavior with respect to the states of different signals during particular computation.

WORKING EXAMPLES Example 1: - 28 ÷ 7 = 4

Iteration 1

Iteration 2

In last iteration net dividend must always be less than divisor or zero. Here last Net Dividend (NDd) is 14 which is greater than Divisor (Dr) i.e. 7. So that to get final result and remainder, we can use following method.

To get the final result and remainder, we have to perform the following process:

Subtract Divisor (Dr) from last iteration net dividend (NDd) number and increment count by one. If the subtraction result, i.e., Sub result, is non-zero and greater than divisor (Dr), continue subtracting Divisor (Dr) from Sub Result and increment count every time we perform subtraction until we get sub result zero or less than the divisor.

If the Sub result is 0 or less than Divisor (Dr), then stop subtraction.

This Sub result is termed as a Remainder (R), and the count is termed as Additional Quotient (AQ). This Additional Quotient (AQ) is added with the number from the Quotient row reading from LHS to RHS to achieve the final result.

Last count Sub result = 0 Count = 2

.·. Quotient (Q) = 2 + 2 = 4 and Remainder (R) = 0

Answer - 28 / 7 = 4 Example 2: - 3657 ÷ 69 = 53

Iteration 1

Iteration 2 Iteration 3 Iteration 4

Iteration 5

Number in Quotient Row - 052 = 52 and

Net dividend = 69 which is equal to divisor (Dr) so we have to add 1 in quotient Answer = 52+1 = 53 and remainder = 0

Answer - 3657 / 69 = 53

Example 3: - (1000 0001) _b ÷ (1001) _b = (1001) _b

Iteration 1

Iteration 2

Iteration 3

As Net Dividend (NDd) is equal to the Divisor (Dr) which is not equal to zero or less than Divisor (Dr) in last iteration. So final result can be calculated either method 1 or method 2

0000 1001 ÷ 0000 1001 = 0001

Answer = 0000 1000 + 0001 = 0000 1001 = (1001)

Remainder = (0000) _b

Claims

1. A computer-implemented method of dividing a Dividend (Dd) with a Divisor (Dr), where said Dividend (Dd) = said Divisor (Dr) * a Quotient (Q) + a remainder (R); the method comprising generating said Quotient (Q) by iteratively selecting and performing an operation for each iteration, wherein said Dividend (Dd) is normalized by stuffing Zero(s) at a most significant bit (MSB) to match with a bit width requirement of the circuit and a New Divisor (NDr) value is derived by adding to said Divisor (Dr) a positive or negative integer number 1 to 9 which is termed as a Flag Digit (FD) to get a zero at a least significant bit and calculating a Modified Divisor (MDr) by canceling out zero(s), retaining a Number of Zeros Canceled (NZC) value from the least significant bit and consecutive bits of said New Divisor (NDr) if any consecutive zero(s) is (are) available and generating a normalized Dividend (Dd) value by rearranging said Dividend (Dd) into multiple Dividend Groups, from said most significant bit towards said least significant bit or vise a versa, whose bit width or size is defined by said Number of Zeros Canceled (NZC) value and the Modified Divisor (MDr) value, said Flag Digit (FD) value, said multiple Dividend Groups value are iteratively processed, wherein said number of iteration operations performed is equal to said number of Dividend Groups formed; wherein said iterative processing starts based on said Dividend Group value formed of most significant bit(s) as the first iteration and an iteration counter tracks the count of the Awadhoot Matrix iteration under operation where Awadhoot Matrix is an arrangement to hold and control the flow of Modified Divisor (MDr) value, Flag Digit (FD) value, Dividend Groups value of each iteration, Gross Dividend (GDd) value, P - Term value, Net Dividend (NDd) value, S - Term value, and Group Quotient (GQn) value in a sequence and the last iteration operations performed up to said Net Dividend (NDd) value where a comparator compares said Net Dividend (NDd) value and Divisor (Dr) value deriving four possibilities of a Quotient (Q) and said Remainder / said Residue (R) calculation as:

First: said Net Dividend = 0, i.e., said Dividend (Dr) is completely divisible by said Divisor (Dr) with said Remaindersaid Residue (R) = 0 and said Quotient (Q) = said Partial Quotient (PQ) formed by concatenating individual Group Quotients (GQn) of Dividend Groups starting from LHS to RHS of Awadhoot Matrix;

Second: said Net Dividend = said Divisor (Dr), i.e., said Dividend (Dr) is completely divisible by said Divisor (Dr) with said Quotient (Q) = said Partial Quotient (PQ) + 1 and said Remainder/said Residue (R) = 0; Third: said Net Dividend < said Divisor (Dr); said Quotient (Q) = said Partial Quotient and said Remainder/said Residue (R) = Value of NDd at the last iteration;

Fourth: said Net Dividend > said Divisor (Dr); Said Quotient (Q) = said Partial Quotient (PQ) + an Additional Quotient (AQ) and said Remainder/said Residue (R) = Value obtained during calculation of Additional Quotient (AQ) where an Additional Quotient (AQ) is derived by initializing count to zero and subtracting Divisor (Dr) from the last iteration Net Dividend (NDd) number and increment count by one. If the subtraction result, i.e., Sub result, is non-zero and greater than or equal to Divisor (Dr), continue subtracting Divisor (Dr) from Sub Result and increment count every time we perform subtraction until we get sub result zero or less than the divisor. If the Sub result is 0 or less than Divisor (Dr), then stop subtraction. This Sub result is termed as as Reminder (R), and the count is termed as Additional Quotient (AQ) and wherein a set of operations during said iterations comprising: a Gross Dividend (GDd) operation, concatenating previous iteration remainder value and the value from the selected Dividend Group if the Modified Divisor (MDr) value is less than the selected Dividend Group value and proceeds for the next operation else the circuit selects the Group Quotient (GQn) value of the selected iteration as Zero and shifted the selected Dividend Group value to the Remainder (Rem-n); a Product Term (P-Term) operation, multiplying said Flag Digit (FD) value and said Group Quotient (GQn) from the previous iteration; if the selected iteration is the first iteration, then previous Group Quotient (GQO) is considered as zero; a Net Dividend (NDd) operation, adding said Product Term (P-Term) value and said Gross Dividend (GDd) value of the selected iteration; a Sign Check operation, performing a negative sign verification of said Net Dividend (NDd) operation; in case of negative sign, cancel the iteration operation and decrease previous Group Quotient (GQn) by one and restart the operation of the selected iteration; a Subtract Term (S-Term) operation multiplying said Modified Divisor (MDr) value by a multiplier number such that resultant product value is less than or equal to said Net Dividend (NDd) value of the selected iteration; a Group Quotient (GQn) operation, storing said multiplier number value from said Subtract Term (S-Term) operation, which is represented as the Group Quotient (GQn) value in the selected iteration operation, and performs subtraction of said Subtract Term (S-Term) value from the of said selected iteration Net Dividend (NDd) value where the result of subtraction is stored as the Remainder (Rem-n) of the selected iteration referred to the next iteration; a Partial Quotient (PQ) operation, recombining or concatenating all Group Quotient (GQn) values together from the most significant bit Dividend group to the least significant bit Dividend Group;

An Additional Quotient (AQ) operation, initializing said counter to zero and subtracting said Divisor (Dr) from said Net Dividend (NDd) value of the last iteration and incrementing count by one; continue subtracting said Divisor (Dr) from result until said subtraction result is zero or less than the divisor and subtraction result is termed as a Reminder (R), and the count is termed as an Additional Quotient (AQ).

2. A method of dividing a Dividend (Dd) by a Divisor (Dr) for use in an embedded system, in a digital system, in an integrated circuit (IC), in a digital circuit, in a computer system; wherein said Dividend (Dd) = said Divisor (Dr) * a Quotient (Q) + a remainder (R); said method comprising: receiving said Dividend (Dd) and said Divisor (Dr); rearranging said Dividend (Dd) by pre stuffing or concatenating zero(s) at the most significant bit (MSB); generating a New Divisor (NDr) value is by adding to said Divisor (Dr) a positive or negative integer number 1 to 9 which is termed as a Flag Digit (FD) to get a zero at a least significant bit; obtaining a Modified Divisor (MDr) by canceling out zeros from units place and from consecutive places of said New Divisor (NDr) if any consecutive zero(s) is (are) available; generating dividend groups wherein for each dividend group, size of a group is equal to the count of NZC; arranging said Modified Divisor (MDr), Flag Digit (FD), and said Dividend groups in an Awadhoot Matrix, arranged to hold and control the flow of said Modified Divisor (MDr) value, said Flag Digit (FD) value, said Dividend Groups value of each iteration, said Gross Dividend (GDd) value, a P - Term value, a Net Dividend (NDd) value, a S - Term value, and Group Quotient (GQn) value in a sequence where the count of dividend groups is equal to the number of required iterations; generating a Gross Dividend (GDd), a Product Term, a Subtract Term and a Net Dividend (NDd) by considering remainder, present iteration value of dividend group, said Flag Digit (FD), and previous iteration Group Quotient; generating a Partial Quotient by concatenating Group Quotient (GQn) of all iterations starting from LHS (MSB) to RHS (LSB); generating a Quotient (Q) and said Remainder (R) of division, derived from the value of partial quotient and last iteration Net Dividend (NDd) of Awadhoot matrix

3. The method of claim 2, comprising providing said Dividend (Dd) and said Divisor (Dr) depending on invalid state condition, later arranging said Dividend (Dd) and said Divisor (Dr) by pre stuffing or concatenating zero.

4. The method of claim 3, comprising providing a New Divisor (NDr) and a Flag Digit (FD), wherein said Flag Digit (FD) is equal to the count of ones which is added or subtracted from said Divisor (Dr) to obtain said New Divisor (NDr).

5. The method of claim 4, comprising of providing a Modified Divisor (MDr) and a count of

Number of Zeros Cancel (NZC) wherein count of Number of Zeros Cancel (NZC) out from said New Divisor (NDr) to obtain said Modified Divisor (MDr).

6. The method of claim 5, comprising setting dividend groups from RHS (LSB) to LHS (MSB) based on the value of the number of zeros cancel out from said New Divisor (NDr) to achieve variable latency and stuffing zero in the LHS (MSB) dividend group to make it to the required count per dividend group.

7. The method of claim 6, comprising arranging said Modified Divisor (MDr), said Flag Digit

(FD), and value of dividend groups for obtaining a residue/a remainder (R) for the next iteration.

8. The method of claim 7, comprising obtaining a Gross Dividend (GDd) by concatenating remainder with the value of dividend group of the current iteration n.

9. The method of claim 8, comprising generating a Product Term by multiplying said Flag Digit

(FD) with Group Quotient from the previous iteration.

10. The method of claim 9, comprising generating said Net Dividend (NDd) by adding a Product Term with a Gross Dividend (GDd) of the current iteration.

11. The method of claim 10, comprising generating a Subtract Term by multiplying said Modified Divisor (MDr) by itself until the product remains less than or equal to said Net Dividend (NDd).

12. The method of claim 11, comprising generating a Group Quotient by subtracting said Subtract Term from said Net Dividend (NDd) of the current iteration.

13. The method of claim 12, comprising obtaining a Partial Quotient by concatenating said Group Quotient of all iteration starting from LHS (MSB) to RHS (LSB).

14. The method of claim 13, comprising obtaining a Final result / said Quotient (Q) based on said Partial Quotient (PQ) and four conditions of said Net Dividend (NDd) value available at last iteration: First: said Net Dividend (NDd) = 0, i.e., said Dividend (Dr) is completely divisible by said Divisor (Dr) with said Remainder = 0 and said Quotient (Q) = said Partial Quotient (PQ);

Second: said Net Dividend (NDd) = said Divisor (Dr); i.e., said Dividend (Dr) is completely divisible by said Divisor (Dr) with said Quotient (Q) = said Partial Quotient (PQ) + 1 and said Remainder = 0;

Third: said Net Dividend (NDd) < said Divisor (Dr); said Quotient (Q) = said Partial Quotient (PQ) and said Remainder = a Value of said NDd from the last iteration;

Fourth: said Net Dividend (NDd) > said Divisor (Dr); said Quotient (Q) = said Partial Quotient (PQ) + an Additional Quotient (AQ) and said Remainder = a Value obtained during calculation of additional quotient; where an Additional Quotient (AQ) is derived by initializing count to zero and subtracting Divisor (Dr) from the last iteration Net Dividend (NDd) number and increment count by one. If the subtraction result, i.e., Sub result, is non zero and greater than or equal to Divisor (Dr), continue subtracting Divisor (Dr) from Sub Result and increment count every time we perform subtraction until we get sub result zero or less than the divisor. If the Sub result is 0 or less than Divisor (Dr), then stop subtraction. This Sub result is termed as as Reminder (R), and the count is termed as Additional Quotient (AQ).

15. A computer program product configured to perform the method as disclosed in claim 1.

16. A non-transitory computer-readable storage medium storing instruction that, when executed by an integrated circuit (IC) or processing device, cause an integrated circuit (IC) or processing device to carry out a method as disclosed in claim 1.