CN214409954U - Multiplication circuit in SSD master control chip - Google Patents
Multiplication circuit in SSD master control chip Download PDFInfo
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- CN214409954U CN214409954U CN202120314445.2U CN202120314445U CN214409954U CN 214409954 U CN214409954 U CN 214409954U CN 202120314445 U CN202120314445 U CN 202120314445U CN 214409954 U CN214409954 U CN 214409954U
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Abstract
The utility model discloses a multiply operation circuit in SSD main control chip, multiply operation circuit includes position selector, compensation value memory, partial product arithmetic element, shift register and buffer adder, the input and the multiplier end of position selector are connected, the number of times output and the compensation value memory of position selector, shift register and buffer adder are connected, the result output and the partial product arithmetic element of position selector are connected, the input and the multiplicand end of partial product arithmetic element are connected, the output and the shift register of compensation value memory are connected, shift register's output with the input of buffer adder is connected. The utility model discloses can avoid producing the negative value in the multiplier operation result to a large amount of benefit sign indicating number arithmetic circuit have been reduced. Thereby greatly reducing the hardware implementation cost of the algorithm.
Description
Technical Field
The utility model relates to a SSD main control chip operation technical field with higher speed especially relates to multiplication circuit in SSD main control chip.
Background
SSD (Solid State Disk) data storage has gradually become the primary storage medium for consumer device data storage and cloud storage. The SSD master control chip is used as the brain of the SSD storage device, and the durability and the performance of the SSD hard disk are directly determined by the error correction performance and the encryption and decryption performance of the SSD master control chip. Therefore, the encryption and decryption circuit in the SSD master control chip is optimized to have great significance. At present, the use of a radix-four-booth (radix-4-booth) multiplier of the SSD is common, but a negative number may occur in a partial product after table lookup in an original algorithm, so that a complement circuit needs to be designed to complete subtraction operation when each partial product is added in circuit implementation, thereby causing a rise in circuit cost.
Disclosure of Invention
Therefore, a multiplication circuit in the SSD master control chip needs to be provided, and the problem that negative numbers may appear in partial products after table look-up each time when the SSD storage device is encrypted and decrypted at present is solved, so that a complement circuit needs to be designed to complete subtraction operation when each partial product is added when the circuit is realized, and the circuit cost is increased.
In order to achieve the above object, the present invention provides a multiplication circuit in SSD main control chip, including the following units:
the input end of the bit selector is connected with a multiplier end, the frequency output end of the bit selector is connected with the compensation value memory, the shift register and the cache adder, the result output end of the bit selector is connected with the partial product operation unit, the input end of the partial product operation unit is connected with a multiplicand end, the output end of the partial product operation unit is connected with the shift register, the output end of the compensation value memory is connected with the shift register, the output end of the shift register is connected with the input end of the cache adder, and the output end of the cache adder is connected with the output end of the multiplication operation circuit;
the compensation value memory stores compensation values-1 < (N +1), the partial product operation unit stores preset tables and obtains corresponding partial products according to preset table matching, and the tables are as follows:
further, the partial product operation unit comprises a table look-up unit and a splicing combination unit, the table look-up unit stores the table, the output end of the table look-up unit is connected with the splicing combination unit, and the output end of the splicing combination unit is connected with the shift register.
Furthermore, the table look-up unit further stores a complement, the partial product operation unit further comprises a first adder, the output end of the splicing combination unit is connected with the shift register through the first adder, and the complement output end of the table look-up unit is connected with the first adder.
Furthermore, the SSD main control chip further includes a patch selection unit and a second adder, an input end of the patch selection unit is connected to the operation precision end, an output end of the patch selection unit is connected to the second adder, an output end of the multiplication circuit is connected to the second adder, and an output end of the second adder is connected to the operation result end.
Furthermore, the patch selection unit comprises a plurality of precision patches and a gate, the precision patches are connected with the input end of the gate, the control end of the gate is connected with the operation precision end, and the output end of the gate is connected with the second adder.
Further, the compensation value is-1 < (N +1) and then an additional value greater than 0 is subtracted, and each partial product in the table is also added with the additional value respectively.
Different from the prior art, the technical scheme provides an optimized design circuit of the radix-four-Booth multiplication algorithm, and the circuit can remove the possibility of negative numbers of partial products after table look-up in the original algorithm every time, so that subtraction is not needed when each partial product is added in the circuit implementation, and a large number of complementary code operation circuits are reduced. The utility model discloses an all partial products add the completion back, do a unified subtraction at last, subtract all partial products owed negative number at last. Thereby greatly reducing the hardware implementation cost of the algorithm.
Drawings
Fig. 1 is a circuit diagram of multiplication according to the present invention;
FIG. 2 is a circuit diagram of a partial product operation unit according to the present invention;
fig. 3 is a circuit diagram of an embodiment of the multiplication circuit according to the present invention.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1 to fig. 3, the present embodiment provides a multiplication circuit in an SSD main control chip, which is used for optimizing a conventional radix-four-booth multiplier. The operation formula of the existing radix-four-Booth multiplier is as follows:
the original operation table is shown in table 1:
table 1: original operation table of radix-four-Booth multiplier
In the original radix-four booth algorithm, a negative En, such as-2, -1, may occur, and then a complement needs to be calculated for partial product accumulation.
In order to avoid the condition of negative En, the utility model provides a multiply operation circuit in SSD main control chip, including following unit: the input end of the bit selector is connected with a multiplier end, the frequency output end of the bit selector is connected with the compensation value memory, the shift register and the cache adder, the result output end of the bit selector is connected with the partial product operation unit, the input end of the partial product operation unit is connected with a multiplicand end, the output end of the partial product operation unit is connected with the shift register, the output end of the compensation value memory is connected with the shift register, the output end of the shift register is connected with the input end of the cache adder, and the output end of the cache adder is connected with the output end of the multiplication operation circuit; the compensation value memory stores compensation values of-1 < (N +1), wherein 1< (N +1), namely 1 bit in the compensation values is left-shifted by N +1 bits. The partial product operation unit stores a preset table and obtains a corresponding partial product according to preset table matching, wherein the table is as follows 2:
table 2: the utility model discloses a four-radix booth multiplier operation table
In the partial product of table 2, the part in the braces { } is a partial product expression, a comma inside the brace "," for distinguishing front and rear different bit components, and the label 1 'represents 1 bit, N' represents N bit, b0 represents bit 0, b1 represents bit 1, up to the following bit inversion, Y [ N-1] represents the nth bit of the multiplicand Y, and Y [ N-1:0] represents the values of N-1 bit to 0 bit of the multiplicand Y. For example, the expressions { Y [ N-1], -Y [ N-1:0],1' b1} are used, i.e., the N-1 bit value of Y is taken, the N-1 bit to 0 bit value of Y is inverted, and 1 bit 1 constitutes the partial product E. If Y is 000111, the result of this expression is: 01110001. the complement indicates whether a complement plus 1 is required in subsequent operations. The partial product e (result) represents the result of pre-adding the offset value, excluding the operation of adding the complement. Is formulated as follows:
result＝En*Y+1＜＜(N+1))
the circuit of the above embodiment is particularly suitable for operationThe operation method of portion can adopt the utility model provides a multiplication method in SSD master control chip, including following step: the device is used for operating an input multiplicand Y and an input multiplier X, wherein the multiplicand Y and the multiplier X are binary values, bit widths of the multiplicand Y and the multiplier X are N bits, most significant bits of the multiplier Y and the multiplier X are sign bits, and other bits except the most significant bits represent the size of the values. The multiplicand Y and multiplier X here can be input into the SSD host chip of the present invention by an external chip or generated internally by the SSD host chip. The bit selector sequentially obtains the magnitude of each adjacent three-digit value in the binary number of the multiplier X according to the input multiplier and outputs the magnitude to the partial product operation unit, and outputs the number i corresponding to each adjacent three-digit, wherein the value of i is an integer from ((N +1)/2) -1 to 0, and N is the digit of the multiplier X. Adjacent three-digit numerical position according to X2i+1、X2i、X2i-1Determination of said X2i+1Is the 2i +1 th bit of a multiplier X, said X2iIs the 2i bit of a multiplier X, said X2i-1Is the 2i-1 bit of the multiplier X; x-1And is deemed to be 0. And the partial product operation unit obtains a corresponding partial product according to the table lookup 2 of the numerical values of the adjacent three bits and outputs the partial product to the shift register.
If N is a multiplier X of 6, i has the values 2, 1 and 0, and the bit selector selects the highest adjacent three-digit number X5、X4、X3Outputting the value of i as 2, and then selecting the next group of adjacent three-digit X3、X2、X1Outputting the value, simultaneously outputting the value of i as 1, and finally selecting three-digit X1、X0、X-1And outputs the value, and simultaneously outputs the value of i as 0. The partial product operation unit outputs a corresponding partial product according to the input three-digit number and the multiplicand Y.
And during table look-up operation, the compensation value memory can process and output the compensation value preferentially, and the compensation value memory outputs the compensation value after acquiring the input change of the times i.
And the shift register shifts the input compensation value or partial product according to the frequency i, and the compensation value or partial product is shifted to the left by 2i bits and then input to the buffer adder. When the compensation value is firstly input into the shift register, the shift register firstly carries out shift operation on the compensation value and inputs the result into the buffer adder. After the partial product is input to the shift register, the shift register performs shift operation and inputs the result to the buffer adder.
And the cache adder acquires the shifted value, performs addition operation and caches the value, and outputs a cached result after performing addition operation after acquiring the value with the number of times of 0. The buffer adder performs 6 additions of the results, including the offset shift result and the partial product shift result when i is 2, 1, and 0.
The utility model discloses ultimate algorithm formula is as follows:
the partial product E in the table of the utility model is a compensation value added with 1< (N +1) first, and the negative possibility of partial product after table look-up in the original algorithm can be removed, so that subtraction is not needed when each partial product is added when the circuit is realized, and a large amount of complement operation circuits are reduced. The utility model discloses an all partial products add the completion back, do a unified subtraction at last, subtract all partial products owed negative number at last. Thereby greatly reducing the hardware implementation cost of the algorithm.
In some embodiments, to implement the partial product result logic operation, the partial product operation unit includes a table lookup unit and a splicing combination unit, the table lookup unit stores the table, an output end of the table lookup unit is connected to the splicing combination unit, and an output end of the splicing combination unit is connected to the shift register. And the splicing and combining unit is used for splicing and combining the partial products according to the table 2 to generate a final partial product result.
In order to realize the complement operation, the table look-up unit also stores complement, the partial product operation unit also comprises a first adder, the output end of the splicing combination unit is connected with the shift register through the first adder, and the complement output end of the table look-up unit is connected with the first adder. And the first adder is used for adding the complement to the result of the splicing combination unit and then outputting the result to realize the complement operation.
In order to realize precision compensation, the SSD main control chip further includes a patch selection unit and a second adder, an input end of the patch selection unit is connected to the operation precision end, an output end of the patch selection unit is connected to the second adder, an output end of the multiplication circuit is connected to the second adder, and an output end of the second adder is connected to the operation result end. And the second adder is used for adding the multiplication result and the precision patch result and outputting an operation result to realize precision compensation.
Furthermore, the patch selection unit comprises a plurality of precision patches and a gate, the precision patches are connected with the input end of the gate, the control end of the gate is connected with the operation precision end, and the output end of the gate is connected with the second adder. The gate can select the corresponding precision patch according to the result of the operation precision end, and then the second adder adds the patch value to the multiplication result and outputs the result to realize the precision patch.
The utility model discloses in, the numerical value size of offset value can be and is greater than 1< < (N +1), then the offset value is-1 < < (N +1) and subtracts an additional value that is greater than 0 again, every partial product in the table also adds respectively the additional value. This also ensures that no negative number condition will occur when looking up the table.
In some embodiments, the high order bits need to be extended when accumulation is performed, and the high order bits of the result of the accumulation calculation are compensated to 0 regardless of the negative number. This makes it possible to apply high-order arithmetic operations.
It should be noted that, although the above embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, the changes and modifications of the embodiments described herein, or the equivalent structure or equivalent process changes made by the contents of the specification and the drawings of the present invention, directly or indirectly apply the above technical solutions to other related technical fields, all included in the scope of the present invention.
Claims (6)
- The multiplication circuit in the SSD master control chip is characterized by comprising the following units:the input end of the bit selector is connected with a multiplier end, the frequency output end of the bit selector is connected with the compensation value memory, the shift register and the cache adder, the result output end of the bit selector is connected with the partial product operation unit, the input end of the partial product operation unit is connected with a multiplicand end, the output end of the partial product operation unit is connected with the shift register, the output end of the compensation value memory is connected with the shift register, the output end of the shift register is connected with the input end of the cache adder, and the output end of the cache adder is connected with the output end of the multiplication operation circuit;the compensation value memory stores compensation values-1 < (N +1), and the partial product operation unit stores preset tables and obtains corresponding partial products according to preset table matching.
- 2. The multiplication circuit in an SSD master control chip of claim 1, wherein: the partial product operation unit comprises a table look-up unit and a splicing combination unit, the table look-up unit stores the table, the output end of the table look-up unit is connected with the splicing combination unit, and the output end of the splicing combination unit is connected with the shift register.
- 3. The multiplication circuit in an SSD master chip of claim 2, wherein: the table look-up unit further stores a complement, the partial product operation unit further comprises a first adder, the output end of the splicing combination unit is connected with the shift register through the first adder, and the complement output end of the table look-up unit is connected with the first adder.
- 4. The multiplication circuit in an SSD master control chip of claim 1, wherein: the SSD master control chip further comprises a patch selection unit and a second adder, wherein the input end of the patch selection unit is connected with the operation precision end, the output end of the patch selection unit is connected with the second adder, the output end of the multiplication circuit is connected with the second adder, and the output end of the second adder is connected with the operation result end.
- 5. The multiplication circuit in an SSD master control chip of claim 4, wherein: the patch selection unit comprises a plurality of precision patches and a gate, the precision patches are connected with the input end of the gate, the control end of the gate is connected with the operation precision end, and the output end of the gate is connected with the second adder.
- 6. The multiplication circuit in an SSD master control chip of claim 1, wherein: the compensation value is-1 < (N +1) and then an additional value larger than 0 is subtracted, and each partial product in the table is also added with the additional value respectively.
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| CN112732219A (en) * | 2021-02-04 | 2021-04-30 | 深圳安捷丽新技术有限公司 | Multiplication circuit and method in SSD (solid State disk) master control chip |
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| CN112732219A (en) * | 2021-02-04 | 2021-04-30 | 深圳安捷丽新技术有限公司 | Multiplication circuit and method in SSD (solid State disk) master control chip |
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Address after: No.302, no.6, zone 2, Fuhai Industrial Zone, Fuyong community, Fuyong street, Bao'an District, Shenzhen City, Guangdong Province Patentee after: Shenzhen anjilite New Technology Co.,Ltd. Address before: No.302, no.6, zone 2, Fuhai Industrial Zone, Fuyong community, Fuyong street, Bao'an District, Shenzhen City, Guangdong Province Patentee before: Shenzhen anjili New Technology Co.,Ltd. |
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