EP4350737A1 - Herstellungsverfahren für eine halbleiterstruktur und halbleiterstruktur - Google Patents

Herstellungsverfahren für eine halbleiterstruktur und halbleiterstruktur Download PDF

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Publication number
EP4350737A1
EP4350737A1 EP22924577.4A EP22924577A EP4350737A1 EP 4350737 A1 EP4350737 A1 EP 4350737A1 EP 22924577 A EP22924577 A EP 22924577A EP 4350737 A1 EP4350737 A1 EP 4350737A1
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Prior art keywords
layer
region
isolation layer
isolation
barrier layer
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EP22924577.4A
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English (en)
French (fr)
Inventor
Tonghui Wang
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority claimed from CN202211020370.2A external-priority patent/CN117693184A/zh
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Publication of EP4350737A1 publication Critical patent/EP4350737A1/de
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Definitions

  • the present disclosure relates to, but is not limited to, a manufacturing method of a semiconductor structure and a semiconductor structure.
  • the epitaxial formation of SiGe layer imposes high requirements on the substrate surface, and the contamination or residual oxide layer on the substrate surface will lead to lattice defects of the epitaxial growth such as layer errors, dislocations, or line slipping. Therefore, the substrate needs to be pre-cleaned before the epitaxial growth of the SiGe layer to remove the oxide layer on the substrate surface.
  • the pre-cleaning process will deplete part of the shallow trench isolation (STI) structure, resulting in dishing of the top surface of the STI structure.
  • too deep dishing region between the isolation structure forming the circuit region and the substrate leads to a fault layer, which can easily result in charge leakage from the PMOS devices.
  • STI shallow trench isolation
  • the present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure.
  • a first aspect of the present disclosure provides a manufacturing method of a semiconductor structure.
  • the manufacturing method of a semiconductor structure includes:
  • the isolating lamination layer includes a first isolation layer, a second isolation layer, and a third isolation layer that sequentially cover the first trench, the first isolation layer and the third isolation layer have a same etch selectivity, the first isolation layer and the second isolation layer have different etch selectivity, and the etching off part of the isolating lamination layer in the first region includes:
  • the forming a barrier layer includes:
  • the manufacturing method of a semiconductor structure further includes: cleaning the first region to remove an oxide film on the top surface of the first active region.
  • the removing part of the first isolation layer and part of the third isolation layer includes: etching the barrier layer and the first region until the top surface of the substrate in the second region is exposed, to remove the barrier layer, the part of the first isolation layer in the first region, and the part of the third isolation layer in the first region, where the top surfaces of the first isolation layer, the second isolation layer, and the third isolation layer that are retained in the first trench are basically consistent in height.
  • the forming a barrier layer includes:
  • the manufacturing method of a semiconductor structure further includes:
  • the etching off the barrier layer and part of the isolating lamination layer in the first region includes:
  • the manufacturing method of a semiconductor structure further includes: forming a protective layer covering a top surface of the epitaxial layer, where the protective layer includes a first material.
  • the second region includes a plurality of independent second active regions, adjacent two of the second active regions are isolated by a second trench, the isolating lamination layer is formed in the second trench, and the first active region and the second active region are of different conductive types.
  • the first region includes a P-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) region, and the second region includes an N-channel MOSFET region.
  • PMOSFET metal-oxide-semiconductor field-effect transistor
  • a second aspect of the present disclosure provides a semiconductor structure, including:
  • the first isolation structure includes:
  • the epitaxial layer includes a first material, on a cross-section perpendicular to the top surface of the substrate, concentrations of the first material at the top and bottom of the epitaxial layer are both greater than a concentration of the first material in the middle of the epitaxial layer.
  • the second region includes a plurality of independent second active regions, adjacent two of the second active regions are isolated by a second trench, a second isolation structure is disposed in the second trench, and the first active region and the second active region are of different conductive types.
  • the first region includes a PMOSFET region
  • the second region includes an NMOSFET region.
  • the shallow trench isolation structure is usually presented as an oxide-nitride-oxide (ONO) structure.
  • ONO oxide-nitride-oxide
  • part of the oxide may be removed from the shallow trench isolation structure, a groove is formed in a position of the shallow trench isolation structure close to the active region, and the groove will be deepened during the subsequent process.
  • the depth of the groove is about 15 nm
  • the top of the nitride of the shallow trench isolation structure is higher than the oxide and a turf defect is formed on the top surface of the shallow trench isolation structure.
  • This turf defect is likely to collect charge and form an electron trap, which causes the charge of the PMOS device formed subsequently to spread to the turf and thus leads to the problem of gate oxygen charge leakage, resulting in the degradation of device performance and yield in the semiconductor structure.
  • FIG. 1 is a flowchart of a manufacturing method of a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • FIGs. 4 to 17 are schematic diagrams of various states of a manufacturing method of a semiconductor structure. The manufacturing method of a semiconductor structure is described below with reference to FIGs. 4 to 17 .
  • the semiconductor structure is not limited in this embodiment.
  • the semiconductor structure is described below by taking a dynamic random access memory (DRAM) as an example, but the embodiment is not limited thereto.
  • DRAM dynamic random access memory
  • the semiconductor structure in this embodiment may also be other structures.
  • an exemplary embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, including the following steps: Step S110: Providing a substrate, where the substrate includes a first region and a second region, the first region includes a plurality of independent first active regions, adjacent two of the first active regions are isolated by a first trench, and an isolating lamination layer is formed in the first trench.
  • the substrate 100 may be a semiconductor substrate, and the semiconductor substrate may include a silicon crystal substrate, a germanium (Ge) substrate, a SiGe substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, or the like.
  • the semiconductor substrate may be further doped with ions.
  • the substrate 100 is a silicon crystal substrate.
  • the substrate 100 includes one or more first regions 101, where the first region 101 includes a plurality of independent first active regions 110, the adjacent first active regions 110 are separated by a first trench 120.
  • the substrate 100 also includes a second region 102, where the second region 102 is a region of the substrate 100 other than the first region 101, and a semiconductor device may be formed in the second region 102.
  • the isolating lamination layer 200 includes a multi-layer structure covering the first trench 120.
  • the isolating lamination layer 200 includes a first isolation layer 210, a second isolation layer 220, and a third isolation layer 230 that sequentially cover the first trench 120.
  • the first isolation layer 210 covers a bottom wall and a side wall of the first trench 120
  • the second isolation layer 220 covers the first isolation layer 120
  • the third isolation layer 230 covers the second isolation layer 220 and fills a region unfilled in the first trench 120.
  • the first isolation layer 210 and the third isolation layer 230 have the same etch selectivity, and the first isolation layer 210 and the second isolation layer 220 have different etch selectivity.
  • the first isolation layer 210 and the third isolation layer 230 are made of the same material, and the first isolation layer 210 and the second isolation layer 220 are made of different materials.
  • the materials of the first isolation layer 210 and the third isolation layer 230 may include silicon oxide, and the material of the second isolation layer 220 includes silicon nitride.
  • Step S120 Forming a barrier layer covering a top surface of the second region.
  • the barrier layer 300 may include a single-layer or laminated-layer structure.
  • the barrier layer 300 at least covers the top surface of the second region 102, to prevent the subsequent process of the first region 101 from damaging the device in the second region 102.
  • Step S130 Form an epitaxial layer to cover a top surface of the first active region.
  • the substrate 100 is exposed to the process environment and the surface of the first active region 110 may be oxidized by the environment to form an oxide film 111.
  • the first active region 110 is treated to remove the oxide film 111 from the surface of the first active region 110.
  • the first isolation layer 210 and the third isolation layer 230 are also made of oxides, in the process of removing the oxide film 111, part of the first isolation layer 210 and part of the third isolation layer 230 exposed from the first region 101 are also removed.
  • top surfaces of the first isolation layer 210 and the second isolation layer 230 exposed from the first region 101 are lower than the top surface of the second isolation layer 220, and dishing is formed on the top surface of the isolating lamination layer 200.
  • the first isolation layer 210 is thinner than the third isolation layer 230, resulting in a faster etching speed of the first isolation layer 210, and thus a narrow and deep groove is formed between the first active region 110 and the second isolation layer 220.
  • the epitaxial layer 400 is formed through the following implementations: As shown in FIG. 9 or 15 , the substrate 100 is placed in a reaction chamber, with the top surface of the first active region 110 as the seed crystal, a gas source for forming the epitaxial layer 400 is fed into the reaction chamber, and the epitaxial layer 400 is grown epitaxially in the first active region 110 by chemical vapor deposition process.
  • the material of the epitaxial layer 400 may include silicon, Ge, SiGe, silicon carbide, gallium arsenide, or indium galliumide, and the epitaxial layer 400 may be doped with conductive dopant ions, and the concentrations of silicon at the top and bottom of the epitaxial layer 400 are greater than the concentration of silicon in the middle of the epitaxial layer 400.
  • Step S140 Etching off the barrier layer and part of the isolating lamination layer in the first region, where joints of top surfaces of layers in the isolating lamination layer retained in the first region are basically consistent in height.
  • the process of etching the barrier layer 300 and the process of etching the isolating lamination layer 200 in the first region 101 may be performed simultaneously, or the process of etching the barrier layer 300 is only performed simultaneously with the process of etching the partial part of the isolating lamination layer 200 located in the first region 101.
  • the thickness of the barrier layer 300 can be controlled to adjust the depth by which the isolating lamination layer 200 in the first region 101 is etched, allowing the top surfaces of layers of the isolating lamination layer 200 retained in the first region 101 to be basically consistent in height, as shown in FIG. 17 .
  • part of the isolating lamination layer 200 in the first region 101 may be removed through the following implementations: As shown in FIG. 10 and 16 , first, removing part of the second isolation layer 220, and the top surface of the retained second isolation layer 220 is lower than the top surfaces of the first isolation layer 210 and the third isolation layer 230.
  • the process of etching the second isolation layer 220 has a high etch selectivity, ensuring the heights of the first isolation layer 210 and the third isolation layer 230 remain unchanged in the process of etching the second isolation layer 220.
  • removing part of the first isolation layer 210 and part of the third isolation layer 230, and the top surface of the retained first isolation layer 210, the top surface of the third isolation layer 230, and the top surface of the retained second isolation layer 220 are basically consistent in height.
  • the barrier layer 300 at least includes a material with the same etch selectivity as the material of the first isolation layer 210.
  • the process of etching the barrier layer 300 is at least performed simultaneously with the process of etching part of the first isolation layer 210 and part of the third isolation layer 230 in the first region 101.
  • the thickness of the barrier layer 300 can be adjusted to control the etching depths of the first isolation layer 210 and the third isolation layer 230 in the first region 101, such that the top surfaces of layers of the isolating lamination layer 200 retained in the first region 101 at joints are basically consistent in height.
  • part of the isolating lamination layer in the first region is etched off, allowing the top surface of the isolating lamination layer retained in the first region to be flat with no local protrusion or dishing and no turf defect. This can prevent charge leakage from occurring to the device formed subsequently on the epitaxial layer, thus ensuring good performance and higher yield of the semiconductor structure.
  • this embodiment is an illustration of the above embodiment, and this embodiment includes all the steps of the above embodiment.
  • the difference between this embodiment and the above embodiment is that after the formation of the epitaxial layer, this embodiment also performs the following steps: As shown in FIG. 10 or 16 , the protective layer 410 is formed to cover the top surface of the epitaxial layer 400, the protective layer 410 including a first material.
  • the first material and the material of the first active region 110 are identical.
  • the material of the first active region 110 includes silicon, and the first material also includes silicon.
  • the protective layer 410 is covered on the epitaxial layer 400 for protection, to avoid the damage to the epitaxial layer 400 caused by the subsequent process of etching the barrier layer 300 and the isolation layer 200 exposed from the first region 101, thus ensuring the integrity of the top surface of the epitaxial layer 400 without damage, and avoiding the device formed subsequently on the epitaxial layer 400 leaks electric charge to the epitaxial layer 400.
  • the protective layer 410 is exposed to the process environment, and the first material in the subsequent process will be oxidized by the environment to be an oxide of the first material, and the oxidized protection layer 410 can be removed in the process of etching the isolating lamination layer 200 in the first region 101 without extra adding the step of removing the protective layer 410, thus ensuring that no first material or oxide remains on the formed epitaxial layer 400 while ensuring the simplification of the semiconductor process.
  • an exemplary embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, including the following steps: Step S210: Providing a substrate, where the substrate includes a first region and a second region, the first region includes a plurality of independent first active regions, adjacent two of the first active regions are isolated by a first trench, and an isolating lamination layer is formed in the first trench.
  • the substrate 100 is a silicon crystal substrate
  • the first region 101 includes a PMOSFET region
  • the second region 102 includes an NMOSFET region.
  • the substrate 100 includes one or more first regions 101, where the first region 101 includes a plurality of independent first active regions 110, the adjacent first active regions 110 are separated by a first trench 120.
  • the second region 102 includes a plurality of independent second active regions 130, the adjacent second active regions 130 are isolated by a second trench 140, the first active region 110 and the second active region 130 are of different conductive types.
  • the first active region 110 is of a P-type conductive type, and the first active region 110 is configured to form a PMOS device.
  • the second active region 130 is of an N-type conductive type, and the second active region 130 is configured to form an NMOS device.
  • the isolating lamination layer 200 in this embodiment is the same as that in the foregoing embodiment.
  • the isolating lamination layer 200 includes a first isolation layer 210, a second isolation layer 220, and a third isolation layer 230 that are stacked sequentially.
  • the material of the first isolation layer 210 includes silicon oxide
  • the material of the second isolation layer 220 includes silicon nitride
  • the material of the third isolation layer 230 includes silicon oxide.
  • This embodiment and the foregoing embodiment differ in that the isolating lamination layer 200 fills not only the first trench 120, but also the second trench 140, and the isolating lamination layer 200 is also formed in the second trench 140.
  • the barrier layer 300 is formed through the following implementations: As shown in FIG. 5 , referring to FIG. 4 , first, the initial barrier layer 300a is formed to cover the top surface of the substrate 100, and the initial barrier layer 300a and the first isolation layer 210 have the same etch selectivity.
  • the initial barrier layer 300a may be deposited by atomic layer deposition (ALD).
  • the material of the initial barrier layer 300a can be selected from the same material as the first isolation layer 210.
  • both the materials of the first isolation layer 20 and the initial barrier layer 300a include silicon oxide.
  • the initial barrier layer 300a in the first region 101 is removed to expose the top surface of the first active region 110, and the retained initial barrier layer 300a forms the barrier layer 300.
  • a photoresist layer 350 is formed to cover the top surface of the initial barrier layer 300a in the second region 102.
  • the initial barrier layer 300a exposed from the photoresist layer 350 is removed through the Certas etching process, to expose the top surface of the first active region 110, and the retained initial barrier layer 300a forms the barrier layer 300.
  • the photoresist layer 350 is removed through plasma ashing.
  • the Certas etching process in this embodiment is a chemical dry etching process.
  • the reaction products of the hydrofluoric acid gas and the material of the isolating lamination layer 200 are attached to the top surface of the isolating lamination layer 200, impeding the continuous reaction of the hydrogen fluoride gas with the isolating lamination layer 200. This can mitigate the dishing defect formed in the top surface of the isolating lamination layer 200 during the etching process.
  • the coverage of the photoresist layer 350 can be expanded to ensure that the formed barrier layer 300 can expose the top surface of each first active region 110 and part of the isolating lamination layer 200 in each first active region 110.
  • Step S230 Cleaning the first region to remove an oxide film on the top surface of the first active region.
  • the first region 101 exposed by the barrier layer 300 is etched.
  • the part of 3 nm to 5nm at the top of the first active region 110 is removed, to remove the oxide film 111 oxidized naturally on the top surface of the first active region 110, ensuring that the material on the top surface of the first active region 110 is pure and free of impurities, such that the crystallographic orientation of the first material in the epitaxial layer 400 (described in detail in the subsequent steps) subsequently formed on the top surface of the first active region 110 is the same as the crystallographic orientation of the silicon in the first active region 110.
  • top surfaces of the retained first isolation layer 210 and third isolation layer 230 are higher than the top surface of the second isolation layer 220, and thus a groove is formed between the second isolation layer 220 and the first active region 110.
  • Step S240 Forming an epitaxial layer to cover the top surface of the first active region.
  • the material of the epitaxial layer 400 is SiGe.
  • the substrate 100 is placed in the reaction chamber, and a silicon source gas and a Ge source gas are both fed into the reaction chamber.
  • a silicon source gas and a Ge source gas are both fed into the reaction chamber.
  • dichlorosilane (DCS) or silicon tetrahydroxide (SiH 4 ) can be fed into the reaction chamber as the silicon source gas
  • germanane (GeH 4 ) is fed into the reaction chamber as the Ge source gas.
  • the silicon source gas and the Ge source gas react in the reaction chamber to form SiGe, and the SiGe is deposited on the top surface of the first active region 110 to form the epitaxial layer 400.
  • Step S250 Forming a protective layer to cover the top surface of the epitaxial layer, where the protective layer includes a first material.
  • the epitaxial layer 400 is formed, feeding the Ge source gas into the reaction chamber is stopped, DCS or SiH 4 are continuously fed into the reaction chamber, and hydrogen chloride (HCL) is fed into the reaction chamber. Silicon is deposited on the surface of the epitaxial layer 400 to form the protective layer 410, that is, the first material in this embodiment is silicon.
  • the thickness of the protective layer 410 formed in this embodiment is 2 nm to 3 nm, for example, it may be 2 nm, 2.2 nm, 2.4 nm, 2.5 nm, 2.7 nm, 2.9 nm, or 3 nm.
  • the thickness of the protective layer 410 is within this range.
  • the silicon in the protective layer 410 is sufficient to be completely oxidized by the process environment to form silicon oxide in the subsequent process to etch off the protective layer 410 in the process of etching the first isolation layer 210 and the third isolation layer 230.
  • the protective layer 410 can be formed on the epitaxial layer 400 by adjusting the gas fed into the reaction chamber, without adding equipment to form the protective layer 410, which will reduce production costs and save time costs.
  • Step S260 Removing part of the second isolation layer, where the top surface of the retained second isolation layer is lower than the top surfaces of the first isolation layer and the third isolation layer.
  • the second isolation layer 220 exposed from the first region 101 can be etched by wet etching.
  • the second isolation layer 220 can be etched with hot phosphoric acid (H 3 PO 4 ) at 150°C to 200°C. Part of the second isolation layer 220 is dissolved in the hot phosphoric acid, and then the hot phosphoric acid that has dissolved the part of the second isolation layer 220 is removed, the second isolation layer 220 is etched about 15 nm toward the substrate 100, so that the top surface of the second isolation layer 220 retained in the first region 101 is lower than the top surfaces of the first isolation layer 210 and the third isolation layer 230.
  • H 3 PO 4 hot phosphoric acid
  • Step S270 Etching the barrier layer and the first region until the top surface of the substrate in the second region is exposed, to remove the barrier layer, the part of the first isolation layer in the first region, and the part of the third isolation layer in the first region, where the top surfaces of the first isolation layer, the second isolation layer, and the third isolation layer that are retained in the first trench are basically consistent in height.
  • the barrier layer 300 and the first region 101 are etched by diluted hydrofluoric acid (DHF), to remove the entire barrier layer 300 and part of the first isolation layer 210 and part of the third isolation layer 230 in the first region 101.
  • DHF diluted hydrofluoric acid
  • the first isolation layer 210, second isolation layer 220, and third isolation layer 230 retained in the first trench 120 are basically consistent in height.
  • the top surfaces of the first isolation layer 210, the second isolation layer 220, and the third isolation layer 230 are smoothly connected.
  • the isolating lamination layer 200 retained in the first trench 120 forms a first isolation structure 250
  • the isolating lamination layer 200 retained in the second trench 140 forms a second isolation structure 260
  • the top surface of the first isolation structure 250 is flat without dishing or protrusion defects.
  • the protective layer 410 is exposed to the process environment, and silicon in the protective layer 410 is oxidized to form silicon oxide.
  • the oxidized protective layer 410 is removed by the DHF to avoid damage to the epitaxial layer 400 by the etching process, such that the top surface of the epitaxial layer 400 is flat without deflects. This is conducive to improving the performance and yield of PMOS devices formed on epitaxial layer 400.
  • a material having the same etch selectivity as the first isolation layer and the third isolation layer is used as the barrier layer.
  • the etching speed of the first isolation layer, the third isolation layer, and the barrier layer exposed in the first region is the same.
  • the etching depth of the first isolation layer and the third isolation layer in the first region can be controlled through the process of removing the barrier layer, allowing the top surface of the isolating lamination layer retained in the first region to be flat with no local protrusion or dishing and no turf defect. This provides a good process platform for the POMS device in the first region, ensuing good performance and higher yield of the formed semiconductor structure, thus preventing charge leakage from occurring to the POMS device formed on the epitaxial layer.
  • an exemplary embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, including the following steps: Step S310: Providing a substrate, where the substrate includes a first region and a second region, the first region includes a plurality of independent first active regions, adjacent two of the first active regions are isolated by a first trench, and an isolating lamination layer is formed in the first trench.
  • the substrate 100 provided in this embodiment is the same as the substrate 100 provided in step S210 in the foregoing embodiment, and details are not described herein again.
  • the isolating lamination layer 200 in this embodiment is the same as that in the foregoing embodiment.
  • the isolating lamination layer 200 includes a first isolation layer 210, a second isolation layer 220, and a third isolation layer 230 that are stacked sequentially.
  • the material of the first isolation layer 210 includes silicon oxide
  • the material of the second isolation layer 220 includes silicon nitride
  • the material of the third isolation layer 230 includes silicon oxide.
  • Step S320 Form a first barrier layer, a second barrier layer, and a third barrier layer that are stacked sequentially on the top surface of the substrate.
  • the barrier layer 300 formed in this embodiment is a stack structure with the same etching characteristics as the isolating lamination layer 200.
  • the barrier layer 300 includes a first barrier layer 310, a second barrier layer 320, and the third barrier layer 330 that are stacked on the substrate 100.
  • the etching depths of layers of the isolating lamination layer 200 are adjusted in the subsequent process through the adjustment on the thicknesses of layers of the barrier layer 300.
  • the first barrier layer 310, the second barrier layer 320, and the third barrier layer 330 can be formed sequentially on the top surface of the substrate 100 through the ALD process.
  • the first barrier layer 310 and the first isolation layer 210 have the same etch selectivity
  • the second barrier layer 320 and the second isolation layer 220 have the same etch selectivity
  • the first barrier layer 310 and the third barrier layer 330 have the same etch selectivity.
  • the material of the first barrier layer 310 includes silicon oxide
  • the material of the second barrier layer 320 includes silicon nitride
  • the material of the third barrier layer 330 includes silicon oxide.
  • the thickness of the second barrier layer 320 is greater than the total thickness of the first barrier layer 310 and the third barrier layer 330, reserving margin for the depth increase caused by the process impact on the first isolation layer 210 and the third isolation layer 230.
  • the thickness of the first barrier layer 310 is 6 nm
  • the thickness of the second barrier layer 320 is 12 nm
  • the thickness of the third barrier layer 330 is 5.5 nm.
  • Step S330 Etching the first region to remove the third barrier layer in the first region and the second barrier layer in the first region.
  • first forming a photoresist layer 350, which covers the third barrier layer 330 in the second region 102.
  • the third barrier layer 330 exposed from the photoresist layer 350 is removed through the Certas etching process, to expose the second barrier layer 320 in the first region 101, and then the photoresist layer 350 is removed through plasma ashing, to expose the third barrier layer 330 in the second region 102.
  • the second barrier layer 320 of the first region 101 is removed by hot phosphoric acid, to expose the first barrier layer 310 of the first region 101.
  • Step S340 Etching off the third barrier layer in the second region and the first barrier layer in the first region, to expose the top surface of the first active region.
  • the first barrier layer 310 in the first region 101 and the third barrier layer 330 in the second region 102 are removed through the Certas etching process.
  • both the first barrier layer 310 and the third barrier layer 330 are made of silicon dioxide.
  • the oxide film 111 formed naturally on the surface of the first active region 110 is also removed, without cleaning off the oxide film 111 on the surface of the first active region 110, which reduces the process steps.
  • Step S350 Forming an epitaxial layer to cover the top surface of the first active region.
  • step S240 of forming the epitaxial layer 400 in the foregoing embodiment are the same as those in step S240 of forming the epitaxial layer 400 in the foregoing embodiment, which is not described herein again.
  • Step S360 Forming a protective layer to cover the top surface of the epitaxial layer, where the protective layer includes a first material.
  • the steps of forming the protective layer 410 in this embodiment are the same as those in step S250 of forming the protective layer 410 in the foregoing embodiment, which is not described herein again.
  • Step S370 Etching off the second barrier layer in the second region and part of the second isolation layer in the first region, where the top surface of the second isolation layer retained in the first trench is lower than the top surfaces of the first isolation layer and the third isolation layer.
  • the second barrier layer 320 in the second region 102 and the second isolation layer 220 in the first region 101 are wet etched by hot phosphoric acid, to remove the entire second barrier layer 320 in the second region 102.
  • the etching is stopped when the top surface of the first barrier layer 310 in the second region 102 is exposed.
  • the second isolation layer 220 in the first region 101 is etched towards the substrate 100 by approximately 12 nm to 15 nm, such that the top surface of the second isolation layer 220 retained in the first region 101 is lower than the top surfaces of the first isolation layer 210 and the third isolation layer 230.
  • Step S380 Etching off the first barrier layer in the second region and part of the first isolation layer and part of the third isolation layer in the first region, where the top surfaces of the first isolation layer, the second isolation layer, and the third isolation layer that retained in the first trench are basically consistent in height.
  • the first barrier layer 310 in the second region 102 and part of the first isolation layer 210 and part of the third isolation layer 230 in the first region 101 are etched off by DHF. Such etching is stopped when the top surface of the substrate 100 in the second region 102 is exposed. After etching, the first isolation layer 210, the second isolation layer 220, and the third isolation layer 230 that are retained in the first trench 120 are basically consistent in top surface height. In addition, the etching process with DHF also removes the protective layer 410, exposing the top surface of the epitaxial layer 400.
  • a lamination structure having the same etching characteristics as the layers of the isolating lamination layer is used as a barrier layer.
  • the etching depth of each layer of the isolating lamination layer can be adjusted subsequently through the adjustment on the thickness of each layer of the barrier layer, such that the top surface of the isolating lamination layer retained in the first region has no turf defects, thus improving a good process platform for forming the PMOS device in the first region and preventing charge leakage from subsequently occurring to the PMOS device formed on the epitaxial layer.
  • the semiconductor structure includes a substrate 100, a first isolation structure 250, and an epitaxial layer 400.
  • the substrate 100 includes a first region 101 and a second region 102.
  • the first region 101 includes a plurality of independent first active regions 110, and adjacent first active regions 110 are isolated by a first trench 120.
  • the first isolation structure 250 is disposed in the first trench 120, where in a direction from the wall of the first trench 120 to its center, the first isolation structure 250 includes a structure of multiple layers sequentially covering the first trench 120, and joints of top surfaces of the layers of the first isolation structure 250 are basically consistent in height.
  • the first isolation structure 250 includes a first isolation layer 210, a second isolation layer 220, and a third isolation layer 230 that sequentially cover the first trench 120.
  • the first isolation layer 210 covers a bottom wall and part of a side wall of the first trench 120.
  • the second isolation layer 220 covers the first isolation layer 210
  • the third isolation layer 230 covers the second isolation layer 220
  • the top surfaces of the first isolation layer 210, the second isolation layer 220, and the third isolation layer 230 are basically consistent in height.
  • the epitaxial layer 400 includes a first material, and in a cross-section perpendicular to the top surface of the substrate 100, the concentration of silicon at the top and bottom of the epitaxial layer 400 is greater than that in the middle of the epitaxial layer 400.
  • the second region 102 includes a plurality of independent second active regions 130, adjacent second active regions 130 are isolated by a second trench 140.
  • a second isolation structure 260 is disposed in the second trench 140, the first active region 110 and the second active region 130 have different conductive types.
  • the first region 101 includes a PMOSFET region
  • the second region 102 includes an NMOSFET region.
  • the first active region 110 is of a P-type conductive type, and the first active region 110 is configured to form a PMOS device.
  • the second active region 130 is of an N-type conductive type, and the second active region 130 is configured to form an NMOS device.
  • the top surface of first isolation structure 250 has no dishing or protrusion defects, which can avoid charge leakage of the device on the epitaxial layer 400 to the first isolation structure 250 caused by the formation of electron traps due to the defects at the top of the first isolation structure 250, thus ensuring good electrical performance of the semiconductor structure.
  • central In the description of the present disclosure, it is to be noted that the terms “central”, “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “inner”, “outer”, etc. indicate azimuthal or positional relations based on those shown in the drawings only for ease of description of the present disclosure and for simplicity of description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation and be constructed and operative in a particular orientation, and thus may not be construed as a limitation on the present disclosure.
  • first, second, etc. as used in the present disclosure may be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.
  • the identical elements are denoted by the identical or similar reference numerals. For clarity, many parts in the accompanying drawings are not drawn to scale. In addition, certain well-known parts may not be shown. For brevity, a structure obtained after several steps may be described in one figure. Numerous specific details of the present disclosure are described below, for example, structures, materials, dimensions, processes, and techniques of devices in order to provide a clearer understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.
  • part of the isolating lamination layer in the first region is etched off, such that the top surface of the isolating lamination layer retained in the first region has no turf defects, which can avoid charge leakage of the device formed on the epitaxial layer, and ensure that the formed semiconductor structure has excellent performance and higher yield.

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EP22924577.4A 2022-08-24 2022-10-11 Herstellungsverfahren für eine halbleiterstruktur und halbleiterstruktur Pending EP4350737A1 (de)

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CN202211020370.2A CN117693184A (zh) 2022-08-24 2022-08-24 半导体结构的制作方法及半导体结构
PCT/CN2022/124615 WO2024040712A1 (zh) 2022-08-24 2022-10-11 半导体结构的制作方法及半导体结构

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