EP4327233A1 - Acheminement avec pénalisation non stricte de pixels sur un trajet trouvé - Google Patents

Acheminement avec pénalisation non stricte de pixels sur un trajet trouvé

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Publication number
EP4327233A1
EP4327233A1 EP22718463.7A EP22718463A EP4327233A1 EP 4327233 A1 EP4327233 A1 EP 4327233A1 EP 22718463 A EP22718463 A EP 22718463A EP 4327233 A1 EP4327233 A1 EP 4327233A1
Authority
EP
European Patent Office
Prior art keywords
pixel
pixels
circuit path
candidate
path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP22718463.7A
Other languages
German (de)
English (en)
Inventor
Matus Lipka
Kenneth Reneris
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsoft Technology Licensing LLC
Original Assignee
Microsoft Technology Licensing LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Technology Licensing LLC filed Critical Microsoft Technology Licensing LLC
Publication of EP4327233A1 publication Critical patent/EP4327233A1/fr
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3947—Routing global
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/04—Constraint-based CAD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3953—Routing detailed

Definitions

  • Routing a circuit design involves determining the design in accordance with routes for metal wires which electrically connect circuit elements to produce routed circuits that perform desired functions.
  • routing wires of a large circuit design can take several days using present routing techniques. To exacerbate the process, a detailed routing operation is not always guaranteed to succeed, and the process has to start over.
  • FIG. 1 depicts a simplified block diagram of a system environment according to certain embodiments.
  • FIG. 2 shows a highly simplified illustration of a circuit design.
  • FIG. 3 shows an illustrative chip partitioned into a grid of pixels for routing.
  • FIG. 4 shows operations for processing a net in accordance with the present disclosure.
  • FIG. 5 shows operations for routing in accordance with the present disclosure.
  • FIGs. 6A, 6B, 6C, 6D illustrate an example of a routing sequence in accordance with aspects of the present disclosure.
  • FIGs. 7A, 7B, 7C, 7D, 7E illustrate an example of a routing sequence that continues from FIG. 6D in accordance with aspects of the present disclosure.
  • FIGs. 8A, 8B illustrate an example of a routing sequence that continues from FIG. 7E in accordance with aspects of the present disclosure.
  • FIGs. 9A, 9B illustrate an example of a routing sequence that continues from FIG. 8B in accordance with aspects of the present disclosure.
  • FIG. 10 shows an illustrative computing system adapted in accordance with the present disclosure.
  • FIG. 1 illustrates various stages in the design and fabrication process of an integrated circuit (IC) in accordance with some embodiments of the present invention.
  • An initial stage in the process is the determining requirements and needs stage 12, where the requirements and needs of the customers who use the IC are identified. IC design can then proceed to the next stage.
  • the IC design stage 14 typically begins with the electronic design automation (EDA) process.
  • EDA can begin with the system design stage 102 which includes designing the functionality to be provided or performed by the IC.
  • Logic design and functional verification 104 includes developing the logic modules using suitable design specification tools such as VHSIC (Very High Speed Integrated Circuits) Hardware Description Language (VHDL), Verilog code, and the like, and verifying the design for functionality and operating response.
  • Synthesis and design 106 includes translating or otherwise converting the VHDL or Verilog code to a netlist, which specifies components of a circuit design and their interconnections.
  • Design planning 108 includes constructing a high-level floorplan (global routing) to determine placement of the major blocks of logic comprising the IC.
  • Placement and routing 110 includes placement of the circuit elements and routing interconnections between the circuit elements, sometimes referred to as detailed routing. This aspect of the design process is discussed in more detail below.
  • Functional verification 112 includes verifying operation of the IC to ensure the design meets the functional requirements of the IC.
  • the IC fabrication stage 16 can commence to produce finished chips.
  • FIG. 2 shows an illustrative example of a circuit design to demonstrate a typical routing operation.
  • Circuit design 200 includes circuit blocks 202a-202e, which include objects such as cells (devices, wires, etc.), macros, and the like depending on the level of hierarchy in the design.
  • Blocks 202a-202e can be interconnected by circuit paths 204 between pins (terminals) 206 on the blocks. Pins that are electrically connected together are grouped into nets, for example, nets 208a, 208b.
  • a netlist contains a list of nets that comprise the circuit design.
  • routing aspect of the placement and routing operation 110 The job of routing is to route circuit paths in the circuit design so that pins that belong to the same net are electrically connected together by the routed circuit paths.
  • net 208a represents the electrical connection of pins on blocks 202a and 202d.
  • Net 208b likewise, electrically connect together the pins on blocks 202c, 202d, and 202e. Routing creates a topology that meets design constrains used to assure that various electrical and functional goals are met, such as timing requirements, capacitive coupling constraints, power consumption, among other constraints.
  • superconducting wires in a superconducting circuit behave fundamentally like inductors. Accordingly, restricting inductance effects from flux that is projected from flux sources within the superconducting circuit impose additional constraints.
  • IC chip 300 which contains circuit design 302, can be divided into a grid of pixels 304.
  • the grid is a volume of pixels. Pixel locations on the grid can be identified by appropriate grid coordinates.
  • Blocks 202 (FIG. 2) comprising the circuit design are placed relative to the pixels.
  • pins 206 of the blocks are defined relative to the pixels. Pixels correspond to grid points on the metal layer where the pins are placed. For example, the cross-hatch shading in pixel 304d represents the pin (or a portion of the pin) of a placed block (not shown). Pixels also correspond to the placement of cells comprising a circuit path that connects two pins.
  • a given pixel 304e can have adjacent pixels in the north (N), east (E), south (S), and west (W) compass directions.
  • the given pixel can have adjacent pixels on the adjacent metal layers in the up (U) and down (D) directions.
  • FIG. 4 the discussion will now turn to a high level description of routing circuit paths in a circuit design in accordance with the present disclosure.
  • computer executable program code which when executed by a processor (e.g., 1002, FIG. 10) in a computer system (e.g., 1000), can cause the computer system to perform routing in accordance with FIG. 4.
  • the computer system can receive a net.
  • the net can be read in from a previously generated netlist.
  • a net comprises the set of pins among circuit blocks in the circuit design that are electrically connected.
  • the routing operation determines (finds) circuit paths for each pair of pins in a given net.
  • the computer system can select two pins in the net to be routed to define a circuit path that connects the two pins.
  • the pins are placed relative to a grid of pixels, and as such lie on pixels in the grid.
  • the pixel associated with one pin can be designated the start pixel.
  • the pixel associated with the other pin can be designated the end pixel. Routing attempts to find a circuit path between the start pixel and the end pixel.
  • the computer system can find a circuit path between the start pixel and the end pixel. Details of this operation are discussed below in connection for FIG. 5. In accordance with the present disclosure, if a circuit path is found, it is assessed to determine whether the path is acceptable. Accordingly, at this point, the circuit path can be deemed to be a candidate circuit path.
  • a candidate circuit path is found in operation 406 then the computer system can proceed to operation 410. If a circuit path is not found, this represents a failure to route this particular path in the net (operation 506, FIG. 5). Further processing of the net can terminate in order to address the failed route; e.g., re-route a previously placed circuit path, redo the placement, etc.
  • the computer system can evaluate the candidate circuit path to determine if the path is acceptable in terms of one or more constraints on the electrical characteristics of the circuit path.
  • constraints can be described and adhered to during routing.
  • constraints that require excessive computational effort and thus may not be practical to assess during routing.
  • Other constraints cannot be computed until the route is fully computed.
  • superconducting wires need to serve as an inductor with narrow target inductance ranges. These inductance characteristics cannot be assessed until after the circuit path has been routed.
  • the computer system can proceed to operation 414. If the candidate circuit path is not acceptable (rejected) then the computer system can proceed to operation 416 to penalize the pixels comprising the candidate circuit path.
  • the penalty value can be a positive integer value.
  • a pixel that has not been penalized can have a penalty value of O'. When a pixel is penalized, its penalty value can be incremented.
  • pixels can be assigned to multiple candidate circuit paths during the routing process. A pixel can be penalized each time it is on a candidate circuit path that is rejected. A pixel with a higher valued penalty value means the pixel has been penalized more than a pixel with a lower penalty value.
  • the penalty value can be used to select pixels when routing a circuit path between the start and end pixels.
  • the computer system can mark the pixels on the accepted circuit path as being on or otherwise belonging to a circuit path. As will be explained below in connection with FIG. 5, such pixels can be deemed "hard obstructions" for the purpose of routing. It is noted that hard obstructions can be other things in the circuit such as gates, anything that we have to avoid during routing, in addition to previously routed wires. Processing can return to operation 404 to select the next pair of pins in the net and route a circuit path between the selected pair of pins. If all circuit paths in the net have been routed (an empty net), processing can be deemed complete.
  • the computer system can penalize the pixels on the rejected circuit path. In some embodiments, for example, the computer system can increment the penalty value of each pixel in the set of pixels comprising the rejected circuit path. Processing can return to operation 406 to determine another candidate circuit path between the start and end pixels.
  • FIG. 5 the discussion will now turn to a high level description of routing a circuit path in accordance with the present disclosure.
  • computer executable program code which when executed by a processor (e.g., 1002, FIG. 10) in a computer system (e.g., 1000), can cause the computer system to perform routing in accordance with FIG. 5.
  • the computer system can add the start pixel from operation 404 in FIG. 4 as the first on the circuit path.
  • the start pixel can be stored in a table that represents the set of pixels comprising the path.
  • the start pixel serves as the first lead pixel on the circuit path.
  • a lead pixel represents the front of the circuit path, leading a path toward the end pixel.
  • the routing process determines the circuit path iteratively, identifying pixels on the path one pixel at a time. In a given iteration, a pixel is identified with respect to the lead pixel. When a pixel is identified, that pixel becomes the lead pixel for the next iteration.
  • the computer system can build or otherwise obtain a list of pixels that are adjacent to the lead pixel to begin the process of identifying the next pixel on the circuit path.
  • the adjacent pixels represent candidates for selection as the next pixel on the circuit path.
  • adjacent pixels are those pixels in the compass directions relative to the lead pixel.
  • adjacent pixels also include pixels in the adjacent metal layers in the Up and Down directions.
  • the list of adjacent pixels can exclude pixels that are marked or otherwise deemed to be hard obstructions.
  • a pixel can be deemed to be a hard obstruction if the pixel is already associated with a circuit object.
  • a circuit object can be a piece of a previously placed circuit path (e.g., operation 412, FIG.
  • the computer system can select an adjacent pixel from the list that has the lowest penalty value as a candidate for the next lead pixel in the path.
  • additional tie breaking criteria can be used to select from those pixels. For example, a criterion can be to choose the pixel that is closest to the end pixel. Another criterion can be to choose the pixel based on an electrical characteristic; for example, lowest computed inductance. Criteria can be considered in sequence until a the tie is broken, in combination, and so on.
  • the computer system can add the selected pixel to the set of pixels comprising the circuit path, thus extending the path. The selected pixel can now be deemed the new lead pixel on the path for the next iteration.
  • FIGs. 6A-6D, 7A-7E, 8A-8B, and 9A-9B show sequences for routing a circuit path to illustrate various aspects of the operations in FIGs. 4 and 5. References to FIGs. 4 and 5 are made in parentheses.
  • FIGs. 6A-6D, 7A-7E, 8A-8B, and 9A-9B show a simple circuit design on IC chip 600. The chip is represented as a grid of pixels 602. Coordinates have been added for convenience to reference pixels on the grid.
  • FIG. 6A shows an initial configuration of the grid with hard obstructions represented by the filled pixels.
  • the start pixel is pixel [h, 6] and is identified as 's' and the end pixel is pixel [b, 6] and is identified as 'g'.
  • FIG. 6 A illustrates routing a circuit path from 's' to 'g'.
  • the routing process begins with setting the start pixel at [i, 6] to be the initial lead pixel, (operation 502), creating the set of pixels comprising the circuit path, which initially contains:
  • the set of pixels of the partially routed circuit path contains: [i, 6], [h, 6]
  • [f, 6] As the lead pixel, there are two candidate pixels that are adjacent to [f, 6], namely north-direction pixel [e, 6] and east-direction pixel [f, 5], (operation 504). Both pixels are tied with same smallest penalty value, namely O'.
  • the tie breaker is based on the pixel that is closest to the end pixel at [b, 6] Accordingly, pixel [e, 6] is selected over [f, 5] because [f, 5] is further away from the end pixel, (operation 508).
  • Pixel [e, 6] becomes the new lead pixel and is added to the set of pixels.
  • the partially routed circuit path contains:
  • pixels [d, 6] and [c, 6] are then added to the set of pixels.
  • pixel [c, 6] is added and becomes the lead pixel, the next selected pixel will be [b, 6]
  • the routing process can terminate because the selected pixel is the same as the end pixel, (decision point 512).
  • the fully routed circuit path comprises the set of pixels:
  • FIG. 7A shows that the pixels on the rejected circuit path can be penalized, (operation 416).
  • each pixel in the set of pixels comprising the rejected circuit path :
  • FIG. 7A shows the penalized pixels having a penalty value of T.
  • FIG. 7B illustrates routing another circuit path from 's' to 'g' in the presence of the penalized pixels, (operation 406).
  • the routing process begins with setting the start pixel [i, 6] as the initial lead pixel to create the set of pixels comprising the circuit path, which initially contains:
  • FIG. 7B shows the partially routed circuit path from 's' to the lead pixel [f, 6] [0048]
  • FIG. 7C continues the routing with [f, 6] as the lead pixel.
  • FIG. 7D shows the routing advances to pixel [f, 4],
  • [f, 4] is the lead pixel and pixels adjacent to [f, 4] include pixels [e, 4] (north), [g, 4] (south), and [f, 3] (west). Given that these pixels have the same smallest penalty value, namely 'O', the tie breaker can be based on the pixel that is closest to the end pixel at [b, 6] Accordingly, pixel [e, 4] is selected (operation 508) and becomes the new lead pixel that is added to the set of pixels:
  • FIG. 7E shows the fully routed circuit path comprising the set of pixels:
  • FIG. 8A shows that each pixel in the set of pixels comprising the rejected circuit path is penalized by incrementing their respective penalty values:
  • FIG. 8B shows the outcome of routing a circuit path based on the configuration shown in FIG. 8A. It can be seen that the newly routed circuit path is the same as the previously rejected circuit path shown in FIG. 6D, namely:
  • the circuit path in FIG. 8B is obtained because when the routing process reaches pixel [f, 6] as the lead pixel, the choices for the next pixel are [f, 5] and [e, 6] Both pixels have the same penalty value, T, and given that the tie breaker is based on the pixel that is closest to the end pixel, then pixel [e, 6] is chosen because it is closer to the end pixel at [b, 6], thus resulting in the same circuit path as shown in FIG. 6D. Given that the path in FIG. 6D was rejected, the path shown in FIG. 8B will also be rejected.
  • FIG. 9A shows the penalty values after penalizing the routed circuit path shown in FIG. 8B.
  • FIG. 9B shows the fully routed circuit path.
  • the list of candidate pixels for lead pixel [e, 3] includes [d, 3], [e, 4], and [e, 2] Only pixels [d, 3] and [e, 2] are considered for selection because they have the lowest penalty value (O') of the three candidates; or stated differently pixel [e, 4] is excluded because it has the highest penalty value among the candidates.
  • the selected pixel is [d, 3], given that the tie breaker is based on the pixel that is closest to the end pixel of [b, 6]
  • penalty values allows pixels that are on a rejected path to remain as candidates for consideration when re routing a circuit path to find an alternate to the rejected circuit path.
  • conventional routing algorithms eliminate from consideration pixels on a rejected path. In some situations, this restriction on pixels can result in one or more un-routable circuit paths that requires ripping up previously routed paths or previously placed devices, thus significantly increasing design turnaround times.
  • FIG. 6D shows that with conventional routing algorithms if the routed path is rejected, the set of pixels comprising the path would be eliminated from consideration for re-routing purposes. As a result, a circuit path between 's' and 'g' would not be possible. The circuit design would have to be re-worked and circuit paths re routed. However, as can be seen in FIG. 7C, rather than eliminating those pixels, routing in accordance with the present disclosure allows the pixels to be re-used, but with a penalty value so that they are less desirable (softly discouraged) as compared to non- penalized or lesser penalized pixels.
  • FIG. 7C rather than eliminating those pixels
  • Routing in accordance with the present disclosure can significantly reduce the routing process because the use of penalty value allows for more alternate paths to considered than without the use of penalty values. Rather than preventing all pixels on a rejected path to be searched, the present disclosure allows some of those pixels to be considered to find a route when, otherwise, no other routes can be found.
  • FIG. 10 depicts a simplified block diagram of an example computer system 1000 according to certain embodiments.
  • Computer system 1000 can be used to perform routing in accordance with the present disclosure.
  • computer system 1000 includes one or more processors 1002 that communicate with a number of peripheral devices via bus subsystem 1004.
  • peripheral devices include data subsystem 1006 (comprising memory subsystem 1008 and file storage subsystem 1010), user interface input devices 1012, user interface output devices 1014, and network interface subsystem 1016.
  • Bus subsystem 1004 can provide a mechanism that enables the various components and subsystems of computer system 1000 to communicate with each other as intended. Although bus subsystem 1004 is shown schematically as a single bus, alternative embodiments of the bus subsystem can utilize multiple busses.
  • Network interface subsystem 1016 can serve as an interface for communicating data between computer system 1000 and other computer systems or networks.
  • User interface input devices 1012 can include a keyboard, pointing devices (e.g., mouse, trackball, touchpad, etc.), a touch-screen incorporated into a display, audio input devices (e.g., voice recognition systems, microphones, etc.) and other types of input devices.
  • pointing devices e.g., mouse, trackball, touchpad, etc.
  • audio input devices e.g., voice recognition systems, microphones, etc.
  • input device is intended to include all possible types of devices and mechanisms for inputting information into computer system 1000.
  • User interface output devices 1014 can include a display subsystem, a printer, or non-visual displays such as audio output devices, etc.
  • the display subsystem can be, e.g., a flat-panel device such as a liquid crystal display (LCD) or organic light-emitting diode (OLED) display.
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • output device is intended to include all possible types of devices and mechanisms for outputting information from computer system 1000.
  • Data subsystem 1006 includes memory subsystem 1008 and file/disk storage subsystem 1010 represent non-transitory computer-readable storage media that can store program code and/or data, which when executed by processor 1002, can cause processor 1002 to perform operations in accordance with embodiments of the present disclosure.
  • Memory subsystem 1008 includes a number of memories including main random access memory (RAM) 1018 for storage of instructions and data during program execution and read-only memory (ROM) 1020 in which fixed instructions are stored.
  • RAM main random access memory
  • ROM read-only memory
  • File storage subsystem 1010 can provide persistent (i.e., non-volatile) storage for program and data files, and can include a magnetic or solid-state hard disk drive, an optical drive along with associated removable media (e.g., CD-ROM, DVD, Blu-Ray, etc.), a removable flash memory-based drive or card, and/or other types of storage media known in the art.
  • a magnetic or solid-state hard disk drive an optical drive along with associated removable media (e.g., CD-ROM, DVD, Blu-Ray, etc.), a removable flash memory-based drive or card, and/or other types of storage media known in the art.
  • computer system 1000 is illustrative and many other configurations having more or fewer components than system 1000 are possible.
  • an apparatus includes one or more computer processors and a computer-readable storage medium having computer executable instructions that control the one or more computer processors to perform routing of circuit paths on a plurality of pixels associated with a circuit design, including computer executable instructions that control the one or more computer processors to: identify, from among the plurality of pixels, a start pixel associated with a first integrated circuit (IC) device, wherein each of the plurality of pixels is associated with a penalty value; identify, from among the plurality of pixels, an end pixel associated with a second IC device; add pixels, from among the plurality of pixels, to a set of pixels that represent a candidate path between the start pixel and the end pixel; and make a determination to reject or accept the candidate path based at least on electrical characteristics of the candidate path, wherein adding pixels includes identifying one or more adjacent pixels that are adjacent to a previously added pixel on the candidate path; selecting, from the one or more adjacent pixels, a pixel that is associated with a smallest penalty value
  • the computer-readable storage medium further has instructions that control the one or more computer processors to add the start pixel to the set of pixels as a first pixel in the set of pixels; and designate the start pixel as the initial lead pixel on the candidate circuit path.
  • the computer-readable storage medium further has instructions that control the one or more computer processors to increase a penalty value associated with each pixel on the rejected candidate circuit path in response to a determination to reject the candidate circuit path.
  • the computer-readable storage medium further has instructions that control the one or more computer processors to identify a set of pixels that constitutes a second candidate circuit path, including allowing pixels that are on the rejected candidate circuit path to be on the second candidate circuit path in response to a determination to reject the candidate circuit path.
  • the computer-readable storage medium further has instructions that control the one or more computer processors to select from the one or more adjacent pixels a pixel that is closest to the end pixel in response to there being more than one adjacent pixel that is associated with the smallest penalty value.
  • adjacent pixels include pixels that are at North, East, South, and West directions relative to the lead pixel.
  • Adjacent pixels can further include pixels that are at Up and Down directions relative to the lead pixel.
  • a method includes designating a start pixel, among a plurality of pixels on a circuit design, associated with a first integrated circuit (IC) device in the circuit design, wherein each of the plurality of pixels is associated with a penalty value; designating an end pixel, among the plurality of pixels, associated with a second IC device in the circuit design; determining, from among the plurality of pixels, a set of pixels that constitutes a candidate circuit path between the start pixel of the first IC device and the end pixel of the second IC device; and determining electrical characteristics of the candidate circuit path; and making a determination to reject or accept the candidate circuit path based on the electrical characteristics, wherein determining a set of pixels includes: (a) identifying one or more adjacent pixels that are adjacent to a lead pixel on the candidate circuit path; (b) selecting, from the one or more identified adjacent pixels, a pixel that is associated with a smallest penalty value; (c) adding the selected pixel to the set of pixels that constitute
  • the penalty value represents the number of times a pixel has been on a rejected candidate circuit path.
  • the method further includes: adding the start pixel to the set of pixels as a first pixel in the set of pixels; and designating the start pixel as the initial lead pixel on the candidate circuit path.
  • the method further includes, in response to a determination to reject the candidate circuit path, increasing a penalty value associated with each pixel on the rejected candidate circuit path.
  • the method further includes, in response to a determination to reject the candidate circuit path, identifying a set of pixels that constitutes a second candidate circuit path, including allowing pixels that are on the rejected candidate circuit path to be on the second candidate circuit path.
  • operation (b) includes, in response to there being more than one pixel that is associated with the smallest penalty value, selecting a pixel that is closest to the end pixel.
  • adjacent pixels include pixels that are at North, East, South, and West directions relative to the lead pixel.
  • adjacent pixels further include pixels that are at Up and Down directions relative to the lead pixel.
  • a non-transitory computer-readable storage medium having stored thereon computer executable instructions, which when executed by a computer device, cause the computer device to: identify, from among the plurality of pixels, a start pixel associated with a first integrated circuit (IC) device in a circuit design, wherein each of the plurality of pixels is associated with a penalty value; identify, from among the plurality of pixels, an end pixel associated with a second IC device; add pixels, from among the plurality of pixels, to a set of pixels that represent a candidate path between the start pixel and the end pixel; and make a determination to reject or accept the candidate path based at least on electrical characteristics of the candidate path, wherein adding pixels includes: identifying one or more adjacent pixels that are adjacent to a previously added pixel on the candidate path; selecting, from the one or more adjacent pixels, a pixel that is associated with a smallest penalty value, wherein the penalty value corresponds to a number of times the pixel has been associated with a rejected candidate
  • the computer executable instructions which when executed by the computer device, further cause the computer device to: add the start pixel to the set of pixels as a first pixel in the set of pixels; and designate the start pixel as the initial lead pixel on the candidate circuit path.
  • the computer executable instructions which when executed by the computer device, further cause the computer device to increase a penalty value associated with each pixel on the rejected candidate circuit path in response to a determination to reject the candidate circuit path.
  • the computer executable instructions which when executed by the computer device, further cause the computer device to identify a set of pixels that constitutes a second candidate circuit path, including allowing pixels that are on the rejected candidate circuit path to be on the second candidate circuit path in response to a determination to reject the candidate circuit path.
  • adjacent pixels include pixels that are at North, East, South, West, Up, and Down directions relative to the lead pixel.

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Abstract

Selon l'invention, l'acheminement d'un trajet de circuit comprend la sélection de pixels sur le trajet de circuit d'après au moins des valeurs de pénalité associées aux pixels. Des pixels situés sur un trajet de circuit rejeté sont pénalisés en augmentant leurs valeurs de pénalité. Le réacheminement un trajet de circuit rejeté permet à des pixels situés sur des trajets précédemment rejetés d'être pris en considération lors du réacheminement du trajet de circuit rejeté, plutôt que d'être absolument éliminés.
EP22718463.7A 2021-04-20 2022-04-01 Acheminement avec pénalisation non stricte de pixels sur un trajet trouvé Pending EP4327233A1 (fr)

Applications Claiming Priority (2)

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US17/235,878 US11461529B1 (en) 2021-04-20 2021-04-20 Routing with soft-penalizing pixels on a found path
PCT/US2022/022979 WO2022225674A1 (fr) 2021-04-20 2022-04-01 Acheminement avec pénalisation non stricte de pixels sur un trajet trouvé

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EP4327233A1 true EP4327233A1 (fr) 2024-02-28

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WO2019035854A1 (fr) * 2017-08-16 2019-02-21 Kla-Tencor Corporation Apprentissage machine par rapport à des mesures de métrologie
KR102610060B1 (ko) * 2018-11-30 2023-12-06 에이에스엠엘 네델란즈 비.브이. 제조성에 기초한 패터닝 디바이스 패턴을 결정하기 위한 방법

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