EP4203029A3 - Hybrid bonded stacked memory with tsv - Google Patents

Hybrid bonded stacked memory with tsv Download PDF

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Publication number
EP4203029A3
EP4203029A3 EP22205535.2A EP22205535A EP4203029A3 EP 4203029 A3 EP4203029 A3 EP 4203029A3 EP 22205535 A EP22205535 A EP 22205535A EP 4203029 A3 EP4203029 A3 EP 4203029A3
Authority
EP
European Patent Office
Prior art keywords
chiplet
tsv
stacked memory
hybrid bonded
bonded stacked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP22205535.2A
Other languages
German (de)
French (fr)
Other versions
EP4203029A2 (en
Inventor
Xavier F. BRUN
Sanka Ganesan
Debendra Mallik
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of EP4203029A2 publication Critical patent/EP4203029A2/en
Publication of EP4203029A3 publication Critical patent/EP4203029A3/en
Pending legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Embodiments disclosed herein include chiplet modules and die modules. In an embodiment, a chiplet module comprises a first chiplet, where the first chiplet comprises a first active surface. In an embodiment the chiplet module further comprises a second chiplet, where the second chiplet comprises a second active surface. In an embodiment, the chiplet module further comprises a hybrid bonding interface between the first chiplet and the second chiplet, where the hybrid bonding interface electrically couples the first chiplet to the second chiplet.
EP22205535.2A 2021-12-23 2022-11-04 Hybrid bonded stacked memory with tsv Pending EP4203029A3 (en)

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Citations (3)

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US20200013754A1 (en) * 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US20210118858A1 (en) * 2019-10-18 2021-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated Circuit Package and Method
US20210134778A1 (en) * 2019-11-05 2021-05-06 Yangtze Memory Technologies Co., Ltd. Bonded three-dimensional memory devices and methods for forming the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
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US20200013754A1 (en) * 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US20210118858A1 (en) * 2019-10-18 2021-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated Circuit Package and Method
US20210134778A1 (en) * 2019-11-05 2021-05-06 Yangtze Memory Technologies Co., Ltd. Bonded three-dimensional memory devices and methods for forming the same

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