EP4082049A1

EP4082049A1 - Diode comprising at least two passivation layers, in particular formed of dielectrics, which are locally stacked to optimise passivation

Info

Publication number: EP4082049A1
Application number: EP20833924.2A
Authority: EP
Inventors: David Vaufrey; Corentin LE MAOULT
Original assignee: Commissariat a lEnergie Atomique CEA; Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Current assignee: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date: 2019-12-26
Filing date: 2020-12-24
Publication date: 2022-11-02
Also published as: WO2021130368A1; FR3105880A1; FR3105880B1; US20230030098A1; CN114868263A

Abstract

The diode (100) comprises a stack (101) of semiconductor layers and an active area (102) arranged within the stack (101). The stack (101) comprises a side surface (103). The diode (100) comprises a first passivation layer (107) and a second passivation layer (108), the first passivation layer (107) being in contact with the side surface (103), the second passivation layer (108) being in contact with the side surface (103). The second passivation layer (108) is partially formed on the first passivation layer (107).

Description

DIODE CONTAINING AT LEAST TWO LAYERS OF PASSIVATION, IN PARTICULAR FORMED OF DIELECTRIC, LOCALLY SUPERIMPOSED TO OPTIMIZE PASSIVATION Technical field of the invention

The technical field of the invention relates to diodes, preferably light emitting diodes, and more particularly light emitting diodes based on inorganic semiconductors. More particularly, the invention relates to a diode comprising a stack of semiconductor layers, the stack comprising a side surface and the diode comprising an active zone arranged within the stack.

State of the art

It is known from the state of the art how to manufacture a light-emitting diode comprising a stack of semiconductor layers. The light-emitting diode has an active zone located in the stack and in which the charge carriers recombine during operation of the light-emitting diode. The stack of semiconductor layers is generally passivated on its side flanks using a passivation layer. These lateral flanks can be formed by faces parallel or substantially parallel to the direction of flow of the current in the stack. Such a passivation layer has the advantage of limiting the electrical, optical or opto-electronic parasitic effects at the edge of the light-emitting diode. These limitations are advantageous because they make it possible to improve the performance of the light-emitting diode. The existing passivation processes for light-emitting diodes do not make it possible to optimize the efficiency of these light-emitting diodes. Indeed, it is observed that the efficiency of light-emitting diodes remains dependent on their dimensions, that is to say that the efficiency of a light-emitting diode decreases monotonously with its dimensions. Object of the invention

The object of the invention is to improve the passivation of a diode in order to improve its efficiency.

To this end, the invention relates to a diode comprising: - a stack of semiconductor layers, the stack comprising a side surface,

an active zone arranged within the stack, this diode comprising a first passivation layer and a second passivation layer, the first passivation layer being in contact with the side surface, the second passivation layer being in contact with the side surface. The second passivation layer 108 is formed in part on the first passivation layer 107.

This makes it possible to respond to a problem of improving the passivation of the diode. Consequently, it also makes it possible to tend towards an efficiency of the diode, when it is light emitting, independent of its dimensions by more specifically passivating parts of the light emitting diode. For a current diode, improving its passivation makes it possible to limit the presence of currents linked to recombinations on the sides of the diode.

The diode may further include one or more of the following characteristics:

the stack comprises a layer of doped semiconductor material of the first type and a layer of doped semiconductor material of the second type, and the diode is such that: the first passivation layer is in contact, at the lateral surface, with the layer of doped semiconductor material of the first type; the second passivation layer is in contact, at the lateral surface, with the active zone; the active area is arranged between the layer of doped semiconductor material of the first type and the layer of doped semiconductor material of the second type, or the active area is arranged at a junction between the layer of semiconductor material doped of the first type and the layer of doped semiconductor material of the second type; B

the diode comprises a third passivation layer, the third passivation layer being in contact, at the side surface, with the layer of doped semiconductor material of the second type;

- the first passivation layer is formed from a first dielectric material and the second passivation layer is formed from a second dielectric material;

- the third passivation layer is formed from a third dielectric material;

the diode is such that the first dielectric material has an electrical conductivity that is at least three orders of magnitude lower than the electrical conductivity of the doped semiconductor material of the first type and that the second dielectric material has an electrical conductivity that is at least three orders of magnitude lower. minus three orders of magnitude to the electrical conductivity of the semiconductor material forming the active zone; - the diode is such that the active area comprises an intrinsic semiconductor material and that the band offset between the valence band of the intrinsic semiconductor material and the valence band of the second dielectric material is strictly greater than 3 kT / q , and that the band offset between the conduction band of the intrinsic semiconductor material and the conduction band of the second dielectric material is strictly greater than 3kT / q, with k the Boltzmann constant, T the ambient temperature in Kelvin, q a constant corresponding to the elementary charge in coulombs;

- the third dielectric material has an electrical conductivity at least three orders of magnitude lower than the electrical conductivity of the doped semiconductor material of the second type;

- the diode is such that the first type being the N type, the band offset between the conduction band of the first dielectric material and the conduction band of the doped semiconductor material of the first type is strictly greater than 3 kT / q, and that the second type being the P type, the band offset between the valence band of the third dielectric material and the valence band of the doped semiconductor material of the second type is strictly greater than 3 kT / q, with k the constant of Boltzmann, T the ambient temperature in Kelvin, q a constant corresponding to the elementary charge in coulombs, - the diode is such that the second type being the N type, the band offset between the conduction band of the third dielectric material and the conduction band of the doped semiconductor material of the second type is strictly greater than 3 kT / q, and that the first type being the P type, the band offset between the valence band of the first dielectric material and the valence band of the doped semiconductor material of the first type is strictly greater than 3 kT / q, with k the constant of Boltzmann, T the ambient temperature in Kelvin, q a constant corresponding to the elementary charge in coulombs.

The invention also relates to a method of manufacturing a diode as described, the manufacturing process comprising:

- a step of forming a stack of semiconductor layers, part of said stack being intended to form an active area of the diode,

a step of forming and passivation of a side surface of the stack of semiconductor layers, said step of forming and passivation of the side surface comprising a formation of a first passivation layer and a formation of a second passivation layer, the first and second passivation layers being in contact with the side surface, the second passivation layer being formed in part on the first passivation layer. The manufacturing process may include one or more of the following characteristics:

the step of forming and passivation of the side surface comprises successively: a first etching step carrying out an etching of the stack so as to form a first part of the side surface; a step of depositing a first dielectric material so as to form the first passivation layer, the first passivation layer covering the first part of the side surface; a second etching step carrying out an etching of the first dielectric material deposited and of the stack so as to form a second part of the side surface; a step of depositing a second dielectric material so as to form the second passivation layer, the second passivation layer covering the second part of the side surface and being in contact with the first passivation layer; - Preferably the first and second parts are formed by different materials;

- The manufacturing process comprises: a first processing step applied to the first part of the side surface before the implementation of the step of depositing the first dielectric material; a second processing step applied to the second part of the side surface before the implementation of the step of depositing the second dielectric material; the first processing step and the second processing step being different; - the first treatment step comprises a step of cleaning the first part and / or a step of surface etching of the first part and / or a step of grafting elements on the first part;

- the second processing step comprises a step of cleaning the second part and / or a step of surface etching of the second part and / or a step of grafting elements on the second part;

- the step of forming and passivation of the side surface comprises: a third etching step carrying out an etching of the second dielectric material deposited and of the stack so as to form a third part of the side surface; a step of depositing a third dielectric material so as to form a third passivation layer, the third passivation layer covering the third part of the side surface and being in contact with the second passivation layer;

- Preferably the third part is formed by a material different from the material forming the second part; - the manufacturing process includes a third processing step applied to the third part of the side surface before the implementation of the step of depositing the third dielectric material;

- the third processing step comprises a step of cleaning the third part and / or a step of surface etching of the third part and / or a step of grafting elements on the third part;

the manufacturing process is such that the step of forming the stack of semiconductor layers is such that the stack comprises a layer of doped semiconductor material of the first type and a layer of semiconductor material. doped conductor of the second type, the first part of the side surface being delimited by a portion of said layer of doped semiconductor material of the first type, and the second part of the side surface being delimited by a portion of the active area;

the active area is arranged between the layer of doped semiconductor material of the first type and the layer of doped semiconductor material of the second type, or the active area is arranged at a junction between the layer of semiconductor material. doped conductor of the first type and the layer of doped semiconductor material of the second type;

the third part of the lateral surface is delimited by a portion of the layer of doped semiconductor material of the second type.

Other features and advantages will become apparent from the detailed description which follows.

Brief description of the drawings

The invention will be better understood on reading the detailed description which follows, given solely by way of non-limiting example and made with reference to the accompanying drawings and listed below.

Figure 1 illustrates schematically, in cross section, a diode according to a particular embodiment of the invention for which the diode is preferably a light emitting diode.

Figure 2 illustrates schematically, in cross section, a variant of the diode according to a particular embodiment of the invention for which the diode is preferably a light emitting diode.

Figure 3 is a cross-sectional view showing the formation of a stack for manufacturing the diode of Figure 1.

FIG. 4 illustrates, in a cross-sectional view, the section of FIG. 3 at the end of a step of etching the stack. FIG. 5 illustrates, in a cross-sectional view, the section of FIG. 4 at the end of a step of depositing a first dielectric material.

Figure 6 illustrates, in a cross-sectional view, the section of Figure 5 after another step of etching the stack.

Figure 7 illustrates, in a cross-sectional view, the section of Figure 6 at the end of a step of depositing a second dielectric material.

Figure 8 illustrates, in a cross-sectional view, the section of Figure 7 after another step of etching the stack.

Figure 9 illustrates, in a cross-sectional view, the section of Figure 8 at the end of a step of depositing a third dielectric material.

FIG. 10 illustrates, in a cross-sectional view, an etching step, applied to the section of FIG. 9, making it possible to form openings in particular in the third dielectric material.

FIG. 11 illustrates a sequence of steps of the manufacturing process according to a particular embodiment of the invention.

In these figures, the same references are used to designate the same elements.

detailed description

By “substantially parallel” is meant parallel to plus or minus 30 degrees.

By “between two values”, it is understood that the limits defined by these two values are included in the range of values considered.

By "different materials" is meant materials that are different in their composition, although they may contain one or more elements in common.

By “based on” when speaking of a device such as a diode based on a material, it is understood that this material predominates in the composition of this device. The invention relates to a diode 100, particular embodiments of which are illustrated in FIGS. 1 and 2. Diode 100 comprises a stack 101 of semiconductor layers. The diode 100 comprises an active zone 102 arranged within the stack 101, that is to say that the active zone 102 forms part of the stack 101. The stack 101 of semiconductor layers comprises a surface 103 lateral.

By "active zone 102 arranged within, that is to say in, the stack 101", it is considered that the stack 101 makes it possible to define this active zone 102, one edge of which can define a corresponding part of the surface. 103 lateral.

The active zone 102 is also called an active region in the technical field of diodes. This is an optically active zone 102 in the sense that the active zone 102 allows, for example, to absorb photons or to emit photons. The active zone 102 is in particular formed by a corresponding semiconductor material.

Thus, the active zone 102 can be configured to allow the recombination of charge carriers from which the emission of electromagnetic radiation, that is to say for example the emission of photons, by the diode 100 results. .

Alternatively, the active zone 102 can be configured to absorb photons, for example by photovoltaic effect, from which the generation of charge carriers by the diode 100 results, these charge carriers then being able to be collected. This results in the production of electricity by the diode 100.

Each charge carrier discussed in the present description may be a first charge carrier or a second charge carrier. The first charge carriers are different from the second charge carriers. For example, the first charge carriers can be holes or electrons, and the second charge carriers can be holes or electrons.

Thus, it follows from what has been described above that the diode 100 is an opto-electronic device. This diode 100 can be a diode light emitting device, a photodiode, a photo-detector, a photovoltaic cell or a laser diode.

Although the active zone 102 is represented schematically by a single block in FIG. 1, this active zone 102 can be:

- formed by intrinsic semiconductor layers then forming the block referenced as active zone 102 in FIG. 1, for example these intrinsic semiconductor layers are formed by quantum multi-wells when the diode 100 has multiple quantum wells , in these intrinsic semiconductor layers the charge carriers can recombine when the diode 100 is a light emitting diode or photons can be absorbed to generate electrons and holes when the diode is a photodiode or a photo-detector,

- formed by a space charge area, shown circled in dotted lines in Figure 2, in a PN junction when the diode 100 includes this PN junction formed by two layers of semiconductor material 109 and 110 of the stack 101 for example P-type doped and N-type doped respectively,

- formed by an intrinsic semiconductor layer, then forming the active zone 102 of FIG. 1, in a P-l-N junction when the diode 100 comprises this P-l-N junction.

In the present description, an intrinsic semiconductor layer is a layer of intrinsic semiconductor material.

The stack 101 of semiconductor layers is preferably defined along an axis A1 of stacking of the semiconductor layers of the stack 101 and represented by a dotted line in FIGS. 1 and 2. This axis A1 is also called, when oriented, "stacking direction". This stacking axis A1 is parallel or substantially parallel to the direction of measurement of the thickness of each of the semiconductor layers of the stack 101 of semiconductor layers.

In particular, the stack 101 of semiconductor layers may include two faces 104, 105 opposite along the stack axis A1. Surface 103 side is preferably formed so as to extend between these two opposite faces 104, 105 and for example so as to connect these two opposite faces 104, 105. By way of example in FIGS. 1 and 2, one of the faces 105 of the stack 101 of semiconductor layers is in contact with a substrate 112 and the other of the faces 104 of the stack 101 of semi-conductive layers. conductive is in contact with an electrode such as for example an anode 113.

Thus, the lateral surface 103 is preferably defined in part by a set of points for which the normal to this lateral face 103, at each of these points of the set of points, is orthogonal to the axis A1 of stacking.

The side surface 103 may have a plurality of faces, each face of the plurality of faces forming a side of the stack 101 of semiconductor layers.

In general, diode 100 comprises a first passivation layer 107 and a second passivation layer 108. The first passivation layer 107 is in contact with the side surface 103. The second passivation layer 108 is in contact with the side surface 103. In other words, the diode 100 comprises a passivation structure 106 comprising the first passivation layer 107 and the second passivation layer 108.

In other words, the side surface 103 may include a first part 103a and a second part 103b. The first passivation layer 107 is then in contact with the first part 103a of the lateral surface 103. The second passivation layer 108 is then in contact with the second part 103b of the lateral surface 103.

The second passivation layer 108 is formed in part on the first passivation layer 107. As a result, another part of this second passivation layer 108 ensures contact between the second passivation layer 108 and the side surface 103. This makes it possible to form a local superposition of the first passivation layer 107 and of the second passivation layer 108, advantageously allowing the presence of the first and second parts 103a, 103b of the lateral surface 103 respectively in contact with the first passivation layer 107 and with the second passivation layer 108. This further allows that the first and second parts 103a, 103b could be surface treated, preferably in different ways, to obtain, for each of these first and second parts 103a, 103b, a passivation optimized for said first or second part. 103a, 103b corresponding.

In other words, the first passivation layer 107 is arranged between the stack 101 and the part of the second passivation layer 108 formed on the first passivation layer 107.

Preferably, the first passivation layer 107 surrounds a part of the stack 101 of semiconductor layers around the stack axis A1 and the second passivation layer 108 surrounds a part of the stack 101 of semi-conductive layers. conductive around the stacking axis A1. This has the advantage of providing passivation around stack 101 of diode 100.

Preferably, the first passivation layer 107 is also in contact with the active zone 102 to ensure that a part of the stack 101 located in the continuity of the active zone 102 is passivated adequately by the passivation layer 107.

The presence of this passivation structure 106 with at least two passivation layers formed by the first and second passivation layers 107, 108 makes it possible to optimize the passivation of the diode 100 and therefore makes it possible to tighten, when the diode 100 is a light-emitting diode, towards an efficiency of the diode 100 independent of its dimensions by more specifically passivating parts of this diode 100. Furthermore, preferably, the presence of these first and second passivation layers 107, 108 can make passivation possible. of the diode 100 in different ways by specific treatments of parts of the lateral surface 103, in particular during the manufacture of the diode 100 as will be described in more detail below.

Furthermore, the first and second passivation layers 107, 108 can make it possible to passivate the lateral surface 103 of the stack 101 differently. when the materials of these first and second passivation layers 107, 108 are different using for example alumina (such as Al2O3) and silicon oxide (such as S1O2) as different materials.

The materials of the first and second passivation layers can be the same, in particular when specific treatments of the first and second parts 103a, 103b of the side surface 103 are carried out during the manufacture of the diode 100.

Thus, unlike a light-emitting diode whose lateral sides are passivated by a single layer of the same material, it is proposed here to use at least two passivation layers which can each be adapted to a specific part of the surface. 103 lateral, thus having the advantage of allowing an adapted and personalized passivation for this specific part.

The result is that the use of these first and second passivation layers 107, 108 advantageously responds to a problem of improving the operation of the diode 100, for example by limiting the trapping of charge carriers at the interface between the side surface 103 and the first and second passivation layers 107, 108 and / or by limiting the reduction in the mobility of charge carriers at the interface between the side surface 103 and the first and second passivation layers 107, 108.

In this description, passivation is understood as the engineering of surface and / or interface defects aimed at fabricating passive surfaces and / or passive interfaces with respect to:

- voluntary external actions such as, for example, the doping of amorphous silicon after passivation of the defects by hydrogen, which makes it possible to fill pendent bonds,

- involuntary external actions such as adsorption or oxidation.

Passivation aims to control the position of the Fermi level at passivated surfaces and / or passivated interfaces. More particularly, within the framework of the diode 100, the passivation achieves a partial or total suppression of the electronic surface or interface states and thus tends to limit all the effects. electrical, optical or opto-electronic interference at the edge of the diode 100, that is to say at the interface between the lateral surface 103 formed by semiconductor materials of the stack 101 and the medium external to the diode 100: the objective being to tend to erase the electrical and / or optical characteristics, limiting the performance of the diode 100, these characteristics being dependent on the interface states of this diode 100. Thus, a passivation within the meaning of the present description is a so-called "electro-optical" passivation.

The term “interface” is understood in the present description to mean a transition zone between two volumes of adjacent materials, it is an abrupt plane marking a discontinuity in the properties of the two adjacent materials but equivalent to a connection region of generally low thickness corresponding for example to an atomic layer thickness.

At the interface of the side surface 103 with a passivation layer, defects can be created, that is, imperfections in addition to dangling bonds. These imperfections can be impurities, vacancies, anti-sites, compositional disorder, surface adsorption or even specific bond angles.

Thus, the passivation is chosen so as to limit, within the diode 100, the defects likely to interact with charge carriers according to a trapping mechanism and / or a diffusion mechanism.

The trapping mechanism, also called the localization mechanism, manifests itself out of equilibrium of the diode 100, that is to say in particular when a voltage is applied to the terminals of the diode 100. The charge carriers trapped by a state d 'interface are no longer available for the desired effect (for example emission of a photon or for example collection of these charge carriers to produce electricity), this unavailability is temporary if the charge carriers are de-trapped after a certain time or definitively if the charge carriers recombine in a non-radiative manner with charge carriers of the opposite sign. The intensity of the phenomenon linked to this trapping mechanism is a function of the density of the interface states and also of the kinetics. exchange of charge carriers with the allowed bands of the semiconductor considered where the trapping takes place (surface recombination speed).

The diffusion mechanism corresponds to the reduction in the mobility of the free charge carriers at the interface of the lateral surface 103 with the passivation structure 106 due to the presence of fluctuations in the surface potential and the diffusion phenomena of the carbon carriers. load at the side surface 103 caused by the roughness and interface loads at this side surface 103.

In the context of the diode 100, the passivated surface using the passivation structure 106 is the lateral surface 103 because the charge carriers circulate mainly parallel or substantially parallel to the stacking axis A1 of said stack 101, of preferably at least in the active zone 102.

In short, the lateral surface 103 may correspond to a surface on which parasitic mechanisms take place in parallel with the electroluminescence when the diode 100 is a light emitting diode.

According to a particular embodiment, the stack 101 of semiconductor layers may comprise a layer 109 of doped semiconductor material of the first type and a layer 110 of doped semiconductor material of the second type. The first passivation layer 107 is in contact, at the lateral surface 103, with the layer 109 of doped semiconductor material of the first type. The second passivation layer 108 is in contact, at the lateral surface 103, with the active zone 102. In other words, the first part 103a of the lateral surface 103 is a portion of the layer 109 of doped semiconductor material of the first type and the second part 103b of the lateral surface 103 is a portion of the active zone 102. Thus, the first passivation layer 107 can passivate the portion of the layer 109 of doped semiconductor material of the first type and the second passivation layer 108 can passivate the portion of the active zone 102. This particular embodiment allows the presence of passivations suitable for contact with the active zone 102, where it is sought to limit the trapping of charge carriers, and for contact with the layer 109 of semi-rigid material. first type doped conductor. The passivation of the active zone 102 at the lateral surface 103 is therefore preferentially a priority because it is the most sensitive. Passivation of the active zone 102 also makes it possible to limit, where appropriate, unwanted radiative recombinations because with a smaller gap; these unwanted radiative recombinations are also called surface SRH (abbreviation of “Shockley-Read-Hall”) recombinations. Moreover, this preferably allows during the manufacturing process to deposit the first and second passivation layers 107, 108 sequentially so as to subject the first and second parts 103a, 103b to different surface treatments. Typically, the first part 103a is protected, after its treatment, by the first passivation layer 107 during the surface treatment of the second part 103b.

Thus, the passivation structure 106 can make it possible to passivate in different ways on the second part 103b the material of the active zone 102, and on the first part 103a the material of the layer 109 of doped semiconductor material of the first type by keeping account of the specific features of each of the layer 109 of doped semiconductor material of the first type and of the active zone 102, in particular, where appropriate, of a difference in composition or of defects to be removed between the material of the layer 109 of doped semiconductor material of the first type and the material of the active zone 102.

The active zone 102 can be arranged between the layer 109 of doped semiconductor material of the first type and the layer 110 of doped semiconductor material of the second type. This may be the case when the active zone 102 is formed of one or more layers, in particular intrinsic semiconductor layers.

Alternatively, the active zone 102 is arranged at a junction between the layer 109 of doped semiconductor material of the first type and the layer 110 of doped semiconductor material of the second type. This may be the case when it is the junction of the layer 109 of doped semiconductor material of the first type with the layer 110 of doped semiconductor material of the second type which makes it possible to form the active zone 102, this active zone 102 corresponds to the space charge zone of said junction forming in particular a PN junction.

Doping of the first type is opposed to doping of the second type. The first type doping can be P type doping (also called P doping) and in this case the second type doping is N type doping (also called N doping), or vice versa.

It follows from what has been described above that it is sought to limit the trapping of charge carriers in the active zone 102 and the SRH recombinations at the level of this active zone 102 in order to ensure a maximum of desired recombinations of carriers of charge if the diode 100 is emissive of electromagnetic radiation, or to maximize the collection of charge carriers generated within the active area 102 when the diode 100 produces electricity. Moreover, during the operation of the diode 100, the second charge carriers can be represented in a majority manner with respect to the first charge carriers. Therefore, preferably: the first type is such that the layer 109 of doped semiconductor material of the first type is adapted to (that is to say configured for) the mobility of the first charge carriers; the second type is such that the layer 110 of doped semiconductor material of the second type is adapted to (i.e. configured for) the mobility of the second charge carriers; the first charge carriers are less numerous, in the active zone 102, than the second charge carriers present in this active zone 102 during the operation of the diode 100, in particular when it is a light-emitting diode based on of GaN. It follows in this case that in addition to the passivation of the active zone 102, the passivation of the layer 109 of doped semiconductor material of the first type takes priority over that of the layer 110 of doped material of the second type and allows to limit the loss of first charge carriers available in the active zone for recombinations with second charge carriers when the diode emits photons. Of course, if the first and second charge carriers are balanced in number within the diode 100, in particular in the active zone 102, then there is no priority in passivating the layer 109 of semi-material. doped conductor of the first type with respect to the layer 110 of doped material of the second type.

The use of different layers has been described above to passivate the stack 101 at the level of the layer 109 of doped semiconductor material of the first type and of the active zone 102. In order to further improve the passivation of the stack 101, the diode 100 may include a third passivation layer 111 as illustrated for example in Figures 1 and 2. The third layer

I I I passivation is in contact, at the side surface 103, with the layer 110 of doped semiconductor material of the second type. In other words, the passivation structure 106 may include this third passivation layer 111. Thus, the lateral surface 103 may comprise a third part 103c corresponding to a portion of the layer 110 of doped semiconductor material of the second type. Thus, the third passivation layer 111 can passivate the portion of the layer 110 of doped semiconductor material of the second type. This makes it possible to adapt the passivation of the stack 101 locally to a particular material such as the doped semiconductor material of the second type of the layer

110 of doped semiconductor material of the second type. This adaptation of the passivation can be achieved by using a particular treatment of the third part 103c as will be described below. The doped semiconductor material of the second type is in particular different from the doped semiconductor material of the first type and may be different at least in part from the material of the active zone 102.

The third passivation layer 111 is preferably formed in part on the second passivation layer 108. As a result, another part of this third passivation layer 111 ensures contact between the third layer

111 passivation and the side 103 surface.

Preferably, the third passivation layer 111 surrounds part of the stack 101 of semiconductor layers around the stack axis A1 in order to participate in the passivation around the stack 101. For example, the first to third passivation layers 107, 108, 111 are arranged so that each is in contact respectively with the first, second and third parts 103a, 103b, 103c of the side surface 103 and to be locally superimposed. For example, in figures 1 and 2:

- at the level where the first passivation layer 107 is in contact with the first part 103a of the side face 103, the first to third layers

107, 108, 111 passivation are successively superimposed,

- at the level where the second passivation layer 108 is in contact with the second part 103b of the side face 103, the second and third layers

108, 111 passivation are superimposed.

It follows from what has been described above that the number of passivation layers is not limited to two or three. Indeed, the passivation structure 106 may include more than three passivation layers each in contact with a particular material to be passivated forming a corresponding part of the lateral surface 103 of the stack 101 of semiconductor layers. This makes it possible, for example, to treat more than three parts of the side surface of the diode 100 differently. In other words, each passivation layer can be intended to allow a passivation process specific to a corresponding material delimiting a part of the side surface 103 of stacking 101.

In fact, the passivation structure 106 can be adapted to make it possible to limit the trapping in all the interfaces between the layers of the stack 101 and the passivation layers, and to limit, if necessary, the unwanted radiative recombinations because with a gap weaker (SRH recombinations).

Preferably, each passivation layer is a layer of electrically insulating material, also called dielectric material, which has an electrical conductivity that is at least three orders of magnitude lower than the electrical conductivity of the material to be passivated in the stack 101. A order of magnitude corresponds to a factor 10. This makes it possible to avoid current leakage through this passivation layer. Consequently, the first passivation layer 107 can be formed from a first dielectric material, the second passivation layer 108 can be formed from a second dielectric material and, if the third passivation layer 111 is present, this third layer 111 passivation can be formed from a third dielectric material.

The first, second and third dielectric materials can be the same, in particular when specific treatments of the first, second and third parts 103a, 103b, 103c of the side surface 103 are carried out during the manufacture of the diode 100. The first ones , second, and where appropriate, third passivation layers 107, 108, 111 can each be a multilayer structure.

In addition, in order to avoid current leaks:

- the first dielectric material may have an electrical conductivity at least three orders of magnitude lower than the electrical conductivity of the doped semiconductor material of the first type,

- the second dielectric material may have an electrical conductivity at least three orders of magnitude lower than the electrical conductivity of the semiconductor material forming the active zone 102,

- Where appropriate, if the third passivation layer 111 is present, the third dielectric material may have an electrical conductivity at least three orders of magnitude lower than the electrical conductivity of the doped semiconductor material of the second type.

Furthermore, the active zone 102 may comprise, or is formed by, an intrinsic semiconductor material. In this case, the band offset between the valence band of the intrinsic semiconductor material and the valence band of the second dielectric material may be strictly greater than 3kT / q, and the band offset between the conduction band of the intrinsic semiconductor material and the conduction band of the second dielectric material can be strictly greater than 3kT / q. This makes it possible to avoid the entrapment of carriers of charge in the second dielectric material and, where appropriate, avoids the surface conduction of the second dielectric material.

If the first type is the N type, the band offset between the conduction band of the first dielectric material and the conduction band of the doped semiconductor material of the first type can be strictly greater than 3kT / q. This prevents electrons from being trapped in the first dielectric material and allows the surface conduction channel of the first dielectric material to not be supplied with charge carriers of the electron type.

If the second type is N type, the band offset between the conduction band of the third dielectric material and the conduction band of the second type doped semiconductor material can be strictly greater than 3kT / q. This prevents electrons from being trapped in the third dielectric material and allows the surface conduction channel of the third dielectric material to not be supplied with charge carriers of the electron type. If the second type is the P type, the band offset between the valence band of the third dielectric material and the valence band of the second type doped semiconductor material can be strictly greater than 3kT / q. This prevents holes from becoming trapped in the third dielectric material and allows the surface conduction channel of the third dielectric material to not be supplied with hole-type charge carriers.

If the first type is the P type, the band offset between the valence band of the first dielectric material and the valence band of the doped semiconductor material of the first type can be strictly greater than 3kT / q. This prevents holes from becoming trapped in the first dielectric material and allows the surface conduction channel of the first dielectric material to not be supplied with hole-type charge carriers.

In “3kT / q”, also noted “3xkxT / q”, k is the Boltzmann constant, T the ambient temperature in Kelvin, q a constant corresponding to the elementary charge in coulombs. The ambient temperature T can be between 300 K and 500 K. An “offset” within the meaning of the present description is a difference. The band offset is in particular, depending on the case, an energy difference between the conduction bands of two materials or an energy difference between the valence bands of two materials.

A particular example of a diode 100 forming a light-emitting diode based on gallium nitride (GaN) is now described. According to this particular example, the stack 101 of semiconductor layers may comprise successively, preferably from the substrate 112 (for example the substrate 112 is a sapphire or silicon substrate) on which the stack 101 is arranged:

- a layer of N-type doped gallium nitride as a layer 110 of doped semiconductor material of the second type and intended for the transport of electrons,

one or more alternations of layers thus forming the active zone 102, each alternation of layers comprising a layer of gallium-indium nitride (InGaN) and a gallium nitride (GaN) layer not intentionally doped, with a proportion of indium to modulate according to the desired emission wavelength of the light-emitting diode,

a layer of P-type doped gallium nitride as a layer 109 of doped semiconductor material of the first type. The top of the stack 101 opposite the substrate 112 is preferably in contact with an anode 113. The N-type doped gallium nitride layer is preferably in contact with a formed electrode, in connection with the particular example, by a cathode 117.

According to this particular example:

the first part 103a is then formed by P-type doped gallium nitride (the P-type dopant can be magnesium) and the first dielectric material forming the first passivation layer 107 can be an aluminum oxide such as Al2O3 or a silicon oxide such as S1O2,

the second part 103b is then formed by the alternation (s) of layers of the active zone 102, and the second dielectric material forming the second passivation layer 108 may be an aluminum oxide such as Al2O3, - the third part 103c is then formed by N-type doped gallium nitride (the N-type dopant can be silicon) and the third dielectric material forming the third passivation layer 111 can be an aluminum oxide such as Al2O3 or a silicon oxide such as S1O2 _.

According to this particular example, the diode 100 can also include:

- between the layer 110 of doped semiconductor material of the second type and the active zone 102, one or more layers of undoped gallium nitride (not shown) to prevent the diffusion of the N-type dopant into the active zone 102, this or these layers of undoped gallium nitride are then barrier layers to the diffusion of dopant,

- between the active zone 102 and the layer 109 of doped semiconductor material of the first type, one or more layers of undoped gallium nitride (not shown) to prevent the diffusion of the P-type dopant into the active zone 102, this or these layers of undoped gallium nitride are then barrier layers to the diffusion of dopant,

- optionally, between the active zone 102 and the layer 109 of doped semiconductor material of the first type, a layer of aluminum-gallium nitride to form an electron blocking layer, the proportion of aluminum in this layer of electron blocking being adapted according to the desired blocking height; this layer of aluminum-gallium nitride can be in contact with the active zone 102 if the active zone 102 is an alternation of undoped InGaN / GaN layers, or can be at a distance from the active zone 102 if the active zone 102 is formed only by a layer of InGaN making it possible to form, for example, a PlN junction.

According to this particular example, the holes are the least present in the active zone 102. In fact, in comparison with the electrons, the holes are less mobile and the ionization energy of the P-type dopant is greater (the density of holes in the active zone 102 is therefore lower and the height of the barrier at the larger injection).

For this particular example, the differences in function and in nature (that is to say in composition) of the layers of stack 101 underline that a single passivation process which is perfectly applicable to all the layers making up the stack 101 of the light-emitting diode 100 proves to be very complicated to define. With the presence of the passivation structure 106 with at least two passivation layers, this makes it possible to best adapt to the nature and the function of the layers of the stack 101 of the light-emitting diode 100.

The invention also relates to a method of manufacturing the diode 100, one embodiment of which is illustrated in FIGS. 1 and 3 to 10. Consequently, what applies to the diode 100 described above can apply. to the manufacturing process of the diode 100 and what applies to the manufacturing process of the diode 100 can be applied to the diode 100 described above which can be obtained according to this manufacturing process. An example of a sequence of steps in this manufacturing process is also shown schematically in Figure 11.

The manufacturing process comprises a step E1 of forming the stack 101 of semiconductor layers, part of said stack 101 being intended to form the active area 102 of the diode 100 (Figure 3). In fact, during the manufacturing process, the stack 101 formed is modified so as to ultimately obtain the diode 100 comprising the stack 101 as modified. Stack 101 is shown between two dotted lines. The manufacturing process includes a step E2 of forming and passivation of the side surface 103 of the stack 101 of semiconductor layers, a particular example of implementation of which is illustrated in Figures 4 to 9.

To facilitate obtaining the diode 100, before forming and passivating the side surface 103 (step E2), it can be formed at the top of the stack 101, for example opposite the substrate 112 on which the substrate rests. base of the stack 101, a layer 114 of a material to form an electrode (for example the anode 113) of the diode 100, then, on this layer 114 of material to form the electrode, a hard mask 115. A lithography step can then delimit in the hard mask 115 a mask called “etching mask 116” which can be used to produce etchings, for example anisotropic, of the stack 101 in a direction parallel to the stack axis A1 (FIGS. 4 to 8).

This step E2 of formation and passivation of the lateral surface 103 comprises a formation E2-1 of the first passivation layer 107 and a formation E2-2 of the second passivation layer 108 (FIGS. 4 to 7), the first and second passivation layers 107, 108 being in contact with the side surface 103 and the second passivation layer 108 being formed in part on the first passivation layer 107. The second passivation layer 108 is then formed after the first passivation layer 107. Thus, step E2 makes it possible to form the passivation structure 106 comprising these first and second layers 107, 108 of passivation. As mentioned above, the formation of two passivation layers in order to passivate the lateral surface 103 makes it possible to improve the passivation locally, preferably by taking into account, during the passivation of the lateral surface 103, the presence of different materials forming this. side surface 103.

It results from the need to form the aforementioned first and second passivation layers 107, 108 to participate in the passivation of the lateral surface 103, a need to find a technical solution to form them at the edge of the stack 101 of the diode 100. For this, step E2 of formation and passivation of the lateral surface 103 may successively comprise:

- a first etching step E2-1-1 (Figures 4 and 11) performing an etching, preferably anisotropic, of the stack 101 so as to form the first part 103a of the side surface 103, the first step E2-1 -1 of etching may partially delimit the periphery of the active zone 102 and may, where appropriate, delimit the electrode such as the anode 113 mentioned above,

a step E2-1-2 of deposition (FIG. 5) of the first dielectric material so as to form the first passivation layer 107, the first passivation layer 107 covering, and therefore being in contact with, the first part 103a of the lateral surface 103, - a second E2-2-1 etching step (FIG. 6) carrying out an etching, preferably anisotropic, of the first dielectric material deposited and of the stack 101 so as to form the second part 103b of the surface 103 lateral and preferably so as to partially delimit, and in particular the remainder of, the periphery of the active zone 102 from the lateral surface 103,

a step E2-2-2 of depositing the second dielectric material so as to form the second passivation layer 108, the second passivation layer 108 covering, and therefore being in contact with, the second part 103b of the side surface 103 and the second passivation layer 108 being in contact with the first passivation layer 107 (FIG. 7).

The first and second parts 103a, 103b of the side surface 103 may be formed by different materials. For example, in the case where the active zone 102 is formed of one or more layers, for example intrinsic semiconductor, the materials of the first and second parts 103a, 103b are different. For example, when the active zone 102 is formed at a junction between the layer 109 of doped semiconductor material of the first type and the layer 110 of doped semiconductor material of the second type, then the second part 103b can be formed by a portion of the layer 109 of doped semiconductor material of the first type and / or by a portion of the layer 110 of doped semiconductor material of the second type: this makes it possible to passivate the parts of the side surface 103 according to their function. This succession of steps makes it possible to easily form a lateral surface 103 in contact with two passivation layers by using simple techniques of microelectronics by implementing etchings, for example using the etching mask 116 and the deposits of the first. and second dielectric materials by conformal deposits. Above all, this also makes it possible to allow different surface treatments of the first part 103a and of the second part 103b, whether this first part 103a and this second part 103b are made of identical or different or partly different materials.

Furthermore, the formation of the first and second passivation layers 107, 108 in the manner as described above has the advantage of forming the first part 103a and then of passivating it using the first passivation layer 107 before to form the second part 103b and then to passivate it using the second passivation layer 108. Thus, during the manufacturing process, this allows the treatment, also called surface treatment, of independent and specific ways of the first and second parts 103a, 103b of the lateral surface 103 in order to improve their passivation and therefore ultimately the overall passivation of the stack 101 of the diode 100. These treatments make it possible to completely or partially eliminate the within the diode 100, the faults mentioned above capable of interacting with charge carriers depending on the trapping mechanism and / or the diffusion mechanism. Therefore, preferably, the manufacturing process comprises a first processing step E2-1-3 applied to the first part 103a of the side surface 103 before the implementation of the step E2-1-2 of depositing the first. dielectric material and a second processing step E2-2-3 applied to the second part 103b of the side surface 103 before the implementation of the step E2-2-2 of depositing the second dielectric material. The first processing step E2-1-3 and the second processing step E2-2-3 are different for treating in different ways the first and second parts 103a, 103b of the side surface 103, for example formed by different materials. Thus, it is for example possible to treat the first and second parts 103a, 103b in different ways by taking into account the semiconductor material which forms the first part 103a and the semiconductor material which forms the second part 103b. In particular, the second processing step E2-2-3 has the advantage of being carried out while the first part 103a is covered by the first passivation layer 107.

Thus, before the formation of the first passivation layer 107, the step E2 of formation and passivation of the side surface 103 may include the first treatment step E2-1-3 to prepare the first part 103a of the side surface 103. in receiving the first passivation layer 107. Before the formation of the second passivation layer 108, the step E2 of formation and passivation of the side surface 103 may include the second treatment step E2-2-3 to prepare the second part 103b of the side surface 103 to receive. the second passivation layer 108, this second processing step E2-2-3 being implemented after the formation of the first passivation layer 107, the first processing step E2-1-3 being different from the second step E2- 2-3 treatment. Preferably, the step E2 of forming and passivation of the lateral surface 103 comprises, so as to form E2-3 the third passivation layer 111 (FIGS. 9 and 11) mentioned above and belonging to the passivation structure 106, a third etching step E2-3-1 carrying out etching of the second dielectric material deposited and of the stack 101 so as to form the third part 103c of the side surface 103 (passage from FIG. 7 to FIG. 8). Furthermore, the step E2 of forming and passivation of the side surface 103 comprises a step E2-3-2 of depositing the third dielectric material so as to form the third passivation layer 111 (FIG. 9), the third layer 111 passivation covering, and therefore being in contact with, the third part 103c of the side surface 103. The third passivation layer 111 is also in contact with the second passivation layer 108. The third part 103c can be formed by a material different from the material forming the second part 103b. In the case of the junction between the layer 109 of doped semiconductor material of the first type and the layer 110 of doped semiconductor material of the second type, the third part 103c may be in the same material as the second part 103b or in the same material as a portion of the second part 103b, this making it possible to passivate the parts of the side surface 103 according to their function. The third part 103c is in particular formed by a material different from the material forming the first part 103a. These steps have the advantage of allowing passivation in a suitable manner of the third part 103c of the lateral surface 103. This also has, where appropriate, the advantage of carrying out specific processing of the second part 103b (by the second processing step E2-2-3) without this specific processing impacting the third part 103c then formed subsequently. to this specific treatment.

Furthermore, the formation of the third part 103c of the lateral surface 103 as described can allow the implementation of a third processing step E2-3-3 applied to the third part 103c of the lateral surface 103 before setting. implementation of step E2-3-2 of depositing the third dielectric material. This third processing step E2-3-3 has the advantage of being carried out while the second part 103b is covered by the second passivation layer 108.

For example, each processing step described in the present description makes it possible to treat an area associated with it, this area being: the first part 103a for the first processing step E2-1-3, the second part 103b for the second step E2-2-3 processing or, where appropriate, the third part 103c for the third processing step E2-3-3. The step of treating a zone makes it possible to improve the passivation of this zone when the corresponding dielectric material (where appropriate first, second or third dielectric material) is deposited on this zone to form the passivation layer passivating this zone. Consequently, each treatment step can comprise one or more of the following steps: a cleaning step making it possible to remove hydrocarbons and / or carbon and / or oxygen which have adsorbed on the associated zone to be treated; a surface etching step for example of a native oxide of the material of the associated area to be treated, this native oxide having formed on the surface of the associated area to be treated (for example this surface etching step is an NH ₄ OH etching if the native oxide is that of indium nitride); a step of selective etching of an amorphous semiconductor having formed on the associated zone to be treated (for example by a TMAH etching step, with TMAH corresponding to tetramethylammonium hydroxide, if the amorphous semiconductor is gallium nitride amorphous); a slow etching step, that is to say sufficiently reproducible to avoid entirely etching the diode, of the material forming the associated area to be treated (for example this etching step is a KOH etching, with KOH corresponding to potassium hydroxide, if the material is GaN, the KOH makes it possible to reveal certain crystalline planes and makes it possible to obtain a very smooth surface when the associated area to be treated contains GaN, therefore a treated area is obtained with much fewer defects structural); a step of grafting elements onto the associated area to be treated aimed at preventing re-adsorption on this area and / or oxidation of this area. An advantage of element grafting is that these elements temporarily balance the area before the material corresponding dielectric is deposited on this zone, the deposition of the dielectric material also ensuring the elimination of the grafted elements.

More generally, each treatment step can make it possible to treat the area associated with it while avoiding the appearance of unsatisfied molecular bonds on said area during the deposition of the corresponding dielectric material on this area.

A surface etching is understood as being a so-called “finishing” etching in order to obtain a surface with a composition and a crystalline structure of the etched material as close as possible to that of a corresponding solid semiconductor material. Thus, in general, the first processing step E2-1-3 may include a step of cleaning the first part 103a and / or a step of surface etching of the first part 103a and / or a step of grafting elements. on the first part 103a. The second processing step E2-2-3 may include a step of cleaning the second part 103b and / or a step of surface etching of the second part 103b and / or a step of grafting elements onto the second part 103b. Where appropriate, the third processing step E2-3-3 may include a step of cleaning the third part 103c and / or a step of surface etching of the third part 103c and / or a step of grafting elements onto the part three 103c. In the context of this paragraph, each etching step makes it possible to remove what is found adsorbed and / or amorphized in the corresponding treated part (first, second or third part 103a, 103b, 103c) of the lateral surface, and makes it possible to smooth and to homogenize the electronic interface of the corresponding treated part of the lateral surface 103 before the deposition of the corresponding dielectric material to avoid creating defects introducing a trap level in the gap of the corresponding material. In the context of this paragraph, each element grafting step, these elements being for example atoms, makes it possible to temporarily block pendant bonds with atoms which are stable from the thermodynamic point of view. These grafted elements can introduce bonds on the corresponding part of the lateral surface 103, but these bonds will be broken during the deposition of the corresponding dielectric material on this. corresponding part of the side surface 103. For example, taking the place of sulfur oxygen can prevent oxidation of a semiconductor material. These atoms can be particularly advantageous sulfur atoms in order to avoid the oxidation of GaN, InGN, AIGaN, GaP, InGaPI, ANnGaP. The bonds of the grafted elements / atoms are broken during the deposition of the dielectric material on the corresponding part of the lateral surface, in this case the deposition can be at high temperature (typically strictly greater than 100 ° C.) with a possible plasma. In fact, in the context of grafted atoms, the graft must have a thermodynamic bond which is stable at room temperature (the room temperature being here in particular equal to 300 Kelvin) to protect the surface on which it is grafted, and this bond must be break at the deposition temperature of the corresponding dielectric material which may be strictly greater than 100 ° C and strictly less than 400 ° C. The cleaning steps referred to in this paragraph can be as described above, that is to say that they can make it possible, in particular each one, to ensure the removal of the hydrocarbons and / or of the carbon and / or of the oxygen having adsorbed, where appropriate, on the first part 103a, on the second part 103b, or on the corresponding third part 103c of the side surface 103.

Preferably, step E1 of forming the stack 101 of semiconductor layers is such that the stack 101 comprises the layer 109 of doped semiconductor material of the first type and the layer 110 of doped semiconductor material. second type. In that case :

- the first part 103a of the lateral surface 103 is delimited by a portion of said layer 109 of doped semiconductor material of the first type, - the second part 103b of the lateral surface 103 is delimited by a portion of the active zone 102,

- Where appropriate, the third part 103c of the lateral surface 103 may be delimited by a portion of the layer 110 of doped semiconductor material of the second type. In this case, the active zone 102 may be arranged between the layer 109 of doped semiconductor material of the first type and the layer 110 of doped semiconductor material of the second type. Alternatively, the active zone 102 can be arranged at a junction between the layer 109 of doped semiconductor material of the first type and the layer 110 of doped semiconductor material of the second type. This structure is very particularly suitable for forming the diode 100. For each of the first and second dielectric materials and, where appropriate, the third dielectric material, the thickness of the corresponding dielectric material and the conditions for its etching will be selected so that the layer of said deposited dielectric material is not completely etched during any etching step likely to follow the deposition of this layer of said dielectric material so that the desired function of the corresponding passivation layer is ensured in diode 100. In short, either the thickness of dielectric material deposited is increased, either the selected etching has a high etching selectivity between the semiconductor of the stack 101 to be etched and the dielectric material, or the etching is made more direct by increasing the voltage of polarization, bias, or by combining all or part of these alternatives.

The characteristics of the first to third dielectric materials in the context of the description of the diode 100 can of course be applied to the manufacturing process. The deposition of each of the first to third dielectric materials is preferably carried out in a conformal manner allowing uniform and non-damaging deposition on the surfaces where it is deposited (that is to say that this deposition tends not to degrade the state. chemical and electronic initial of the surfaces on which it is carried out). Typically, within the finalized diode 100, each passivation layer (in particular each of the first, second and, where appropriate, third passivation layers) has a thickness which is not important, this thickness is at least an atomic layer thickness. Each passivation layer can have a thickness of a few atomic layers to a few hundred nanometers. In fact, the thickness should be sufficient to protect the passivated surface during any subsequent etching and, if necessary, subsequent treatments which may consume part of the passivation layer deposited beforehand.

According to a particular embodiment of the manufacturing process for which the diode 100 to be manufactured is a light-emitting diode based on gallium nitride, in particular according to the particular example described above, the manufacturing process is as for example described below. .

Once the stack 101 has been provided, for example formed on the substrate 112, and topped with a layer 114 of an anode material and then a hard mask 115 (FIG. 3), a lithography is carried out to delimit the etching mask 116 in the hard mask.

The first etching step E2-1-1 can be an ICP etching (abbreviation of “Inductively Coupled Plasma” in English and corresponding in French to inductively coupled plasma) chlorine-argon allowing the hard mask 115 to be etched out of the mask 116. etching, then the anode material to form the anode 113, then the layer 109 of doped semiconductor material of the first type in order to delimit the first part 103a of the lateral surface 103 then formed by gallium nitride doped with type P belonging to the layer 109 of doped semiconductor material of the first type (FIG. 4). This first etching step E2-1-1 is stopped in the active zone 102 (where appropriate in the layer 110 of doped semiconductor material of the second type if one seeks to manufacture the diode 100 of FIG. 2). This first etching step E2-1-1 is in particular carried out anisotropically according to the etching mask 116 in a direction parallel to the stacking axis A1. The first processing step E2-1-3 can then be applied to the first part 103a (in particular in FIG. 4). This first treatment step comprises a step of etching the first part 103a by NH ₄ OH etching or by KOH etching or by TMAH etching or by deoxidizing etching. The deoxidizing etching can be a dilute HF (abbreviation of hydrofluoric acid) etching or a buffered etching oxide etching also known by the abbreviation BOE for BB

“Buffered oxide etch” in English). This first processing step E2-1-3 tends not to consume the etching mask 116 and the anode 113 in order to prevent, subsequently, after the step of depositing the first dielectric material, the first part 103a is not found unencapsulated by the first dielectric material.

The step E2-1-2 of depositing the first dielectric material (figure 5) can make it possible to deposit in a conform manner an aluminum oxide (such as Al2O3) or a silicon oxide (such as S1O2) as the first material dielectric. This first dielectric material can be deposited by ALD (abbreviation of “Atomic Layer Deposition” in English and corresponding in French to atomic layer deposition) or PE-ALD (abbreviation of “Plasma Enhanced Atomic Layer Deposition” in English and corresponding in French plasma assisted atomic layer deposition).

The second etching step E2-2-1 (FIG. 6) can be an ICP chlorine-argon etching making it possible to etch the first dielectric material and the layer 110 of doped semiconductor material of the second type while participating in the delimitation of the zone 102 active by stopping the second etching step E2-2-1 after it has reached the layer 110 of doped semiconductor material of the second type. It follows from this second etching step E2-2-1 that the second part 103b is formed by the material of the active zone 102. This second etching step E2-2-1 tends not to consume the first dielectric material deposited on the first part 103a.

The second processing step E2-2-3 can then be applied to the second part 103b (in particular in FIG. 6). This second processing step E2-2-3 comprises a step of etching the second part 103b by etching using NH ₄ OH and / or (NhU ^ S. Preferably, this second processing step E2-2-3 tends to not to consume the first dielectric material deposited on the first part 103a as well as, preferably, the etching mask 116.

Step E2-2-2 for depositing the second dielectric material (figure 7) can make it possible to deposit an aluminum oxide (such as Al2O3) in a compliant manner. as the second dielectric material. This second dielectric material can be deposited by ALD or PE-ALD.

The third etching step E2-3-1 (FIG. 8) can be an ICP chlorine-argon etching making it possible to etch the second dielectric material and the layer of doped semiconductor material 110 of the second type in order to delimit the third part 103c of the lateral surface 103. It follows from this third etching step E2-3-1 that the third part 103c is formed by N-type doped gallium nitride belonging to the layer 110 of doped semiconductor material of the second type. In particular, the second part 103c is separated from the second part 103b by a part of the layer 110 of doped semiconductor material of the second type.

The third processing step E2-3-3 can then be applied to the third part 103c (in particular in FIG. 8). This third processing step E2-3-3 comprises a step of etching the third part 103c by NH ₄ OH etching or by KOH etching or by TMAH etching. This third processing step E2-3-3 tends not to consume the etching mask 116 and the second dielectric material deposited on the second part 103b of the side surface 103.

The E2-3-2 deposition step of the third dielectric material (Figure 9) can conformally deposit an aluminum oxide (such as AI2O3) or a silicon oxide (such as S1O2) as the third material dielectric. This third dielectric material can be deposited by ALD or PE-ALD.

Then, after the step E2-3-2 depositing the third material, the third passivation layer 111 can be opened in two regions 118, 119 (FIG. 10), in order, on the one hand, to allow the removal of at least one part of the etching mask 116 in order to make the anode 113 accessible and, on the other hand, to allow the formation of the cathode 117 (FIG. 1) in contact with the layer 110 of doped material of the second type.

The present invention applies, preferably, to light-emitting diodes said to be of small dimensions, that is to say to light-emitting diodes of which at least. at least one of the dimensions in the stacking plane of the semiconductor layers is less than or equal to 100 times the greatest length among the diffusion length of an electron or a hole or even an exciton in one of the semi -conductors making up the stack 101. The present invention also applies to matrices of light-emitting diodes, that is to say to the juxtaposition of light-emitting diodes to form a set of light-emitting diodes spatially close, or to the collective formation of light emitting diodes sharing a single backing plate. Although the exemplary embodiments focus on a light-emitting diode based on gallium nitride, the present invention can be transposed to any other inorganic semiconductor and to all light-emitting diode architectures.

In particular, depending on the first type of doping and the second type of doping respectively for the layer 109 of doped semiconductor material of the first type and for the layer 110 of doped semiconductor material of the second type, the electrodes referred to below. front (anode and cathode) can be reversed. Thus, in general, diode 100 may include electrodes configured to cooperate with stack 101. The present invention has industrial application in the field of manufacturing diodes and their use.

Claims

1. Diode (100) comprising:

- a stack (101) of semiconductor layers, the stack (101) comprising a side surface (103),

- an active zone (102) arranged within the stack (101),

- a first passivation layer (107) and a second passivation layer (108), the first passivation layer (107) being in contact with the side surface (103), the second passivation layer (108) being in contact with the lateral surface (103), the second passivation layer (108) being formed in part on the first passivation layer (107), the stack (101) comprising a layer (109) of doped semiconductor material of the first type and a layer (110) of doped semiconductor material of the second type, characterized in that:

- the first passivation layer (107) is in contact, at the side surface (103), with the layer (109) of doped semiconductor material of the first type,

- the second passivation layer (108) is in contact, at the lateral surface (103), with the active zone (102),

- the active zone (102) is arranged between the layer (109) of doped semiconductor material of the first type and the layer (110) of doped semiconductor material of the second type, or the active zone (102) is arranged in the level of a junction between the layer (109) of doped semiconductor material of the first type and the layer (110) of doped semiconductor material of the second type.

2. Diode (100) according to claim 1, characterized in that it comprises a third layer (111) of passivation, the third layer (111) of passivation being in contact, at the surface (103) side, with the layer. (110) of doped semiconductor material of the second type.

3. Diode (100) according to any one of claims 1 to 2, characterized in that the first passivation layer (107) is formed from a first dielectric material and in that the second passivation layer (108) is formed from a second dielectric material.

4. Diode (100) according to claims 2 and 3, characterized in that the third passivation layer (111) is formed of a third dielectric material.

5. Diode (100) according to any one of claims 3 to 4, characterized in that:

- the first dielectric material has an electrical conductivity that is at least three orders of magnitude lower than the electrical conductivity of the doped semiconductor material of the first type,

- the second dielectric material has an electrical conductivity at least three orders of magnitude lower than the electrical conductivity of the semiconductor material forming the active zone (102).

6. Diode (100) according to any one of claims 3 to 5, characterized in that the active zone (102) comprises an intrinsic semiconductor material and in that the band offset between the valence band of the material intrinsic semiconductor and the valence band of the second dielectric material is strictly greater than 3kT / q and in that the band offset between the conduction band of the intrinsic semiconductor material and the conduction band of the second dielectric material is strictly greater than 3kT / q, with k the Boltzmann constant, T the ambient temperature in Kelvin, q a constant corresponding to the elementary charge in coulombs.

7. Diode (100) according to claim 4 and any one of the preceding claims, characterized in that the third dielectric material has an electrical conductivity at least three orders of magnitude lower than the electrical conductivity of the doped semiconductor material. second type.

8. Diode (100) according to claim 4 and any one of the preceding claims, characterized in that:

- the first type being type N, the band offset between the conduction band of the first dielectric material and the conduction band of the doped semiconductor material of the first type is strictly greater than 3 kT / q,

- the second type being the P type, the band offset between the valence band of the third dielectric material and the valence band of the second type doped semiconductor material is strictly greater than 3kT / q, or in that

- the second type being the N type, the band offset between the conduction band of the third dielectric material and the conduction band of the doped semiconductor material of the second type is strictly greater than 3kT / q,

- the first type being the P type, the band offset between the valence band of the first dielectric material and the valence band of the doped semiconductor material of the first type is strictly greater than 3 kT / q, with k the constant of Boltzmann, T the ambient temperature in Kelvin, q a constant corresponding to the elementary charge in coulombs.

9. A method of manufacturing a diode (100), the manufacturing process comprising:

- a step (E1) of forming a stack (101) of semiconductor layers, part of said stack (101) being intended to form an active zone (102) of the diode (100),

- a step (E2) of forming and passivation of a lateral surface (103) of the stack (101) of semiconductor layers, said step (E2) of formation and passivation of the lateral surface (103) comprising a formation (E2-1) of a first passivation layer (107) and a formation (E2-2) of a second passivation layer (108), the first and second passivation layers (107, 108) being in contact with the side surface (103), the second passivation layer (108) being formed in part on the first passivation layer (107), the step (E2) of forming and passivation of the side surface (103) comprising successively:

- a first etching step (E2-1-1) performing an etching of the stack (101) so as to form a first part (103a) of the side surface (103),

- a step (E2-1-2) of depositing a first dielectric material so as to forming the first passivation layer (107), the first passivation layer (107) covering the first part (103a) of the lateral surface (103),

- a second etching step (E2-2-1) carrying out an etching of the first dielectric material deposited and of the stack (101) so as to form a second part (103b) of the lateral surface (103), preferably the first and second parts (103a, 103b) being formed by different materials,

- a step (E2-2-2) of depositing a second dielectric material so as to form the second passivation layer (108), the second passivation layer (108) covering the second part (103b) of the surface ( 103) lateral and being in contact with the first passivation layer (107), the step (E1) of forming the stack (101) of semiconductor layers being such that the stack (101) comprises:

- a layer (109) of doped semiconductor material of the first type,

- a layer (110) of doped semiconductor material of the second type, characterized in that:

- the first part (103a) of the lateral surface is delimited by a portion of said layer (109) of doped semiconductor material of the first type,

- the second part (103b) of the lateral surface is delimited by a portion of the active zone (102), the active zone (102) being arranged between the layer (109) of doped semiconductor material of the first type and the layer (110) of doped semiconductor material of the second type, or the active zone (102) being arranged at a junction between the layer (109) of doped semiconductor material of the first type and the layer (110) of second type doped semiconductor material.

10. The manufacturing method according to the preceding claim, characterized in that it comprises:

- a first processing step (E2-1-3) applied to the first part (103a) of the lateral surface (103) before the implementation of the step (E2-1-2) of depositing the first dielectric material ,

- a second processing step (E2-2-3) applied to the second part (103b) of the lateral surface (103) before the implementation of the step (E2-2-2) of depositing the second dielectric material , the first processing step (E2-1-3) and the second processing step (E2-2-3) being different.

11. The manufacturing method according to the preceding claim, characterized in that:

- the first processing step (E2-1-3) comprises a step of cleaning the first part (103a) and / or a step of surface etching of the first part (103a) and / or a step of grafting elements on the first part (103a),

- the second processing step (E2-2-3) comprises a step of cleaning the second part (103b) and / or a step of surface etching of the second part (103b) and / or a step of grafting elements on the second part (103b).

12. The manufacturing method according to any one of claims 9 to 11, characterized in that the step (E2) of forming and passivation of the side surface (103) comprises:

- a third etching step (E2-3-1) carrying out an etching of the second dielectric material deposited and of the stack (101) so as to form a third part (103c) of the side surface (103),

- a step (E2-3-2) of depositing a third dielectric material so as to form a third passivation layer (111), the third passivation layer (111) covering the third part (103c) of the surface ( 103) lateral and being in contact with the second passivation layer (108), preferably the third part (103c) being formed by a material different from the material forming the second part (103b).

13. The manufacturing method according to the preceding claim, characterized in that it comprises a third step (E2-3-3) of treatment applied to the third part (103c) of the surface (103) side before the implementation of the step (E2-3-2) of depositing the third dielectric material.

14. The manufacturing method according to the preceding claim, characterized in that the third processing step (E2-3-3) comprises a step of cleaning the third part (103c) and / or a surface etching step of the third part (103c) and / or a step of grafting elements onto the third part (103c).

15. The manufacturing method according to claim 12, characterized in that the third part (103c) of the side surface (103) is delimited by a portion of the layer (110) of doped semiconductor material of the second type.