EP4032122A4 - Glass dielectric layer with patterning - Google Patents

Glass dielectric layer with patterning Download PDF

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Publication number
EP4032122A4
EP4032122A4 EP20866247.8A EP20866247A EP4032122A4 EP 4032122 A4 EP4032122 A4 EP 4032122A4 EP 20866247 A EP20866247 A EP 20866247A EP 4032122 A4 EP4032122 A4 EP 4032122A4
Authority
EP
European Patent Office
Prior art keywords
patterning
dielectric layer
glass dielectric
glass
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP20866247.8A
Other languages
German (de)
French (fr)
Other versions
EP4032122A1 (en
Inventor
Jieying KONG
Gang Duan
Srinivas Pietambaram
Patrick Quach
Dilan Seneviratne
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of EP4032122A1 publication Critical patent/EP4032122A1/en
Publication of EP4032122A4 publication Critical patent/EP4032122A4/en
Pending legal-status Critical Current

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    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
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    • B32B17/10192—Coatings of a metallic or dielectric material on a constituent layer of glass or polymer being not continuous, e.g. in edge regions patterned in the form of columns or grids
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
EP20866247.8A 2019-09-18 2020-06-10 Glass dielectric layer with patterning Pending EP4032122A4 (en)

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KR20220062495A (en) 2022-05-17
US20210078296A1 (en) 2021-03-18
US11780210B2 (en) 2023-10-10
BR112022003175A2 (en) 2022-05-17
EP4032122A1 (en) 2022-07-27

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