EP4011030A4 - Configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm - Google Patents

Configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm Download PDF

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Publication number
EP4011030A4
EP4011030A4 EP20850899.4A EP20850899A EP4011030A4 EP 4011030 A4 EP4011030 A4 EP 4011030A4 EP 20850899 A EP20850899 A EP 20850899A EP 4011030 A4 EP4011030 A4 EP 4011030A4
Authority
EP
European Patent Office
Prior art keywords
configuring
execute
instruction set
computer processor
encryption algorithm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP20850899.4A
Other languages
German (de)
French (fr)
Other versions
EP4011030A1 (en
Inventor
Morris Jacob KREEGER
Tianfang Liu
Frederick Furtek
Paul L. Master
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cornami Inc
Original Assignee
Cornami Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/743,257 external-priority patent/US11693662B2/en
Application filed by Cornami Inc filed Critical Cornami Inc
Publication of EP4011030A1 publication Critical patent/EP4011030A1/en
Publication of EP4011030A4 publication Critical patent/EP4011030A4/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/008—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols involving homomorphic encryption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/602—Providing cryptographic facilities or services
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/62—Protecting access to data via a platform, e.g. using keys or access control rules
    • G06F21/6218—Protecting access to data via a platform, e.g. using keys or access control rules to a system of files or objects, e.g. local or distributed file system or database
    • G06F21/6227—Protecting access to data via a platform, e.g. using keys or access control rules to a system of files or objects, e.g. local or distributed file system or database where protection concerns the structure of data, e.g. records, types, queries
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2107—File encryption
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H04L2209/122—Hardware reduction or efficient architectures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Bioethics (AREA)
  • Data Mining & Analysis (AREA)
  • Databases & Information Systems (AREA)
  • Mathematical Analysis (AREA)
  • Health & Medical Sciences (AREA)
  • General Health & Medical Sciences (AREA)
  • Discrete Mathematics (AREA)
  • Algebra (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
EP20850899.4A 2019-08-07 2020-08-05 Configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm Pending EP4011030A4 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201962883967P 2019-08-07 2019-08-07
US16/743,257 US11693662B2 (en) 2018-05-04 2020-01-15 Method and apparatus for configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm
PCT/US2020/044944 WO2021026196A1 (en) 2019-08-07 2020-08-05 Configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm

Publications (2)

Publication Number Publication Date
EP4011030A1 EP4011030A1 (en) 2022-06-15
EP4011030A4 true EP4011030A4 (en) 2023-12-27

Family

ID=74504130

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20850899.4A Pending EP4011030A4 (en) 2019-08-07 2020-08-05 Configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm

Country Status (3)

Country Link
EP (1) EP4011030A4 (en)
CN (1) CN114631284A (en)
WO (1) WO2021026196A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230208610A1 (en) * 2021-12-28 2023-06-29 International Business Machines Corporation Executing an arithmetic circuit using fully homomorphic encryption (fhe) and multi-party computation (mpc)
CN114710371B (en) * 2022-06-08 2022-09-06 深圳市乐凡信息科技有限公司 Method, device, equipment and storage medium for safely signing electronic data

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040236809A1 (en) * 2003-02-17 2004-11-25 Kaushik Saha Method and system for multi-processor FFT/IFFT with minimum inter-processor data communication
US20050166033A1 (en) * 2004-01-26 2005-07-28 Quicksilver Technology, Inc. System and method using embedded microprocessor as a node in an adaptable computing machine
US20120036514A1 (en) * 2001-03-22 2012-02-09 Paul Master Method and apparatus for a compiler and related components for stream-based computations for a general-purpose, multiple-core system
US20150012725A1 (en) * 2001-03-22 2015-01-08 Sviral, Inc. Method and apparatus for a general-purpose, multiple-core system for implementing stream-based computations

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6792441B2 (en) * 2000-03-10 2004-09-14 Jaber Associates Llc Parallel multiprocessing for the fast fourier transform with pipeline architecture
US7653710B2 (en) * 2002-06-25 2010-01-26 Qst Holdings, Llc. Hardware task manager
US10713333B2 (en) * 2015-12-21 2020-07-14 Apple Inc. Fast Fourier transform architecture
US11294851B2 (en) * 2018-05-04 2022-04-05 Cornami, Inc. Reconfigurable reduced instruction set computer processor architecture with fractured cores
US11693662B2 (en) * 2018-05-04 2023-07-04 Cornami Inc. Method and apparatus for configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120036514A1 (en) * 2001-03-22 2012-02-09 Paul Master Method and apparatus for a compiler and related components for stream-based computations for a general-purpose, multiple-core system
US20150012725A1 (en) * 2001-03-22 2015-01-08 Sviral, Inc. Method and apparatus for a general-purpose, multiple-core system for implementing stream-based computations
US20040236809A1 (en) * 2003-02-17 2004-11-25 Kaushik Saha Method and system for multi-processor FFT/IFFT with minimum inter-processor data communication
US20050166033A1 (en) * 2004-01-26 2005-07-28 Quicksilver Technology, Inc. System and method using embedded microprocessor as a node in an adaptable computing machine

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
DOROZ YARKIN ET AL: "Accelerating Fully Homomorphic Encryption in Hardware", IEEE TRANSACTIONS ON COMPUTERS, IEEE, USA, vol. 64, no. 6, 1 June 2015 (2015-06-01), pages 1509 - 1521, XP011580531, ISSN: 0018-9340, [retrieved on 20150508], DOI: 10.1109/TC.2014.2345388 *
RAHMAN MD. MASHIUR ET AL: "Dynamic Range Input FFT Algorithm for Signal Processing in Parallel Processor Architecture", PROCEEDINGS OF THE WORLD CONGRESS ON ENGINEERING AND COMPUTER SCIENCE 2011, 1 January 2011 (2011-01-01), pages 1 - 6, XP055790901, Retrieved from the Internet <URL:http://www.iaeng.org/publication/WCECS2011/WCECS2011_pp530-535.pdf> [retrieved on 20210329] *
See also references of WO2021026196A1 *

Also Published As

Publication number Publication date
CN114631284A (en) 2022-06-14
EP4011030A1 (en) 2022-06-15
WO2021026196A1 (en) 2021-02-11

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