WO2014115005A3 - Vector generate mask instruction - Google Patents

Vector generate mask instruction Download PDF

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Publication number
WO2014115005A3
WO2014115005A3 PCT/IB2013/060815 IB2013060815W WO2014115005A3 WO 2014115005 A3 WO2014115005 A3 WO 2014115005A3 IB 2013060815 W IB2013060815 W IB 2013060815W WO 2014115005 A3 WO2014115005 A3 WO 2014115005A3
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WO
WIPO (PCT)
Prior art keywords
instruction
vector generate
generate mask
mask instruction
mask
Prior art date
Application number
PCT/IB2013/060815
Other languages
French (fr)
Other versions
WO2014115005A2 (en
Inventor
Jonathan David BRADBURY
Timothy Slegel
Eric Mark Schwarz
Robert Frederick ENENKEL
Original Assignee
International Business Machines Corporation
Ibm United Kingdom Limited
Ibm (China) Investment Company Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corporation, Ibm United Kingdom Limited, Ibm (China) Investment Company Limited filed Critical International Business Machines Corporation
Priority to CN201380071241.9A priority Critical patent/CN104937538B/en
Priority to DE112013005466.3T priority patent/DE112013005466T5/en
Priority to GB1513183.2A priority patent/GB2524440B/en
Priority to JP2015553182A priority patent/JP6380955B2/en
Publication of WO2014115005A2 publication Critical patent/WO2014115005A2/en
Publication of WO2014115005A3 publication Critical patent/WO2014115005A3/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053Vector processors
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001Arithmetic instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018Bit or string instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/3004Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30047Prefetch instructions; cache control instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements

Abstract

A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the instruction.
PCT/IB2013/060815 2013-01-23 2013-12-11 Vector generate mask instruction WO2014115005A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201380071241.9A CN104937538B (en) 2013-01-23 2013-12-11 Vector generates mask instruction
DE112013005466.3T DE112013005466T5 (en) 2013-01-23 2013-12-11 Statement "Vector generate mask"
GB1513183.2A GB2524440B (en) 2013-01-23 2013-12-11 Vector generate mask instruction
JP2015553182A JP6380955B2 (en) 2013-01-23 2013-12-11 Computer program, computer system and method for processing VECTOR GENERATE MASK instructions

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/748,538 US9778932B2 (en) 2013-01-23 2013-01-23 Vector generate mask instruction
US13/748,538 2013-01-23

Publications (2)

Publication Number Publication Date
WO2014115005A2 WO2014115005A2 (en) 2014-07-31
WO2014115005A3 true WO2014115005A3 (en) 2014-12-24

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2013/060815 WO2014115005A2 (en) 2013-01-23 2013-12-11 Vector generate mask instruction

Country Status (6)

Country Link
US (2) US9778932B2 (en)
JP (1) JP6380955B2 (en)
CN (1) CN104937538B (en)
DE (1) DE112013005466T5 (en)
GB (1) GB2524440B (en)
WO (1) WO2014115005A2 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10866807B2 (en) 2011-12-22 2020-12-15 Intel Corporation Processors, methods, systems, and instructions to generate sequences of integers in numerical order that differ by a constant stride
US10223111B2 (en) 2011-12-22 2019-03-05 Intel Corporation Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset
US9778932B2 (en) 2013-01-23 2017-10-03 International Business Machines Corporation Vector generate mask instruction
US9823924B2 (en) 2013-01-23 2017-11-21 International Business Machines Corporation Vector element rotate and insert under mask instruction
US9715385B2 (en) 2013-01-23 2017-07-25 International Business Machines Corporation Vector exception code
US9804840B2 (en) 2013-01-23 2017-10-31 International Business Machines Corporation Vector Galois Field Multiply Sum and Accumulate instruction
US9513906B2 (en) 2013-01-23 2016-12-06 International Business Machines Corporation Vector checksum instruction
US9471308B2 (en) 2013-01-23 2016-10-18 International Business Machines Corporation Vector floating point test data class immediate instruction
US9547489B2 (en) * 2014-03-31 2017-01-17 Qualcomm Incorporated System and method for modifying a sequence of instructions in a read-only memory of a computing device
US11544214B2 (en) 2015-02-02 2023-01-03 Optimum Semiconductor Technologies, Inc. Monolithic vector processor configured to operate on variable length vectors using a vector length register
US11149195B2 (en) * 2016-11-17 2021-10-19 Current Lighting Solutions, Llc Coated red line emitting phosphors
US20200264879A1 (en) * 2019-02-20 2020-08-20 Nanjing Iluvatar CoreX Technology Co., Ltd. (DBA "Iluvatar CoreX Inc. Nanjing") Enhanced scalar vector dual pipeline architecture with cross execution
FR3101982B1 (en) * 2019-10-11 2024-03-08 St Microelectronics Grenoble 2 Determining an indicator bit
US20230297507A1 (en) * 2022-03-15 2023-09-21 Nxp B.V. Adaptive prefetcher for shared system cache

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053986A (en) * 1990-02-21 1991-10-01 Stardent Computer, Inc. Circuit for preservation of sign information in operations for comparison of the absolute value of operands
US6748522B1 (en) * 2000-10-31 2004-06-08 International Business Machines Corporation Performance monitoring based on instruction sampling in a microprocessor
US7480787B1 (en) * 2006-01-27 2009-01-20 Sun Microsystems, Inc. Method and structure for pipelining of SIMD conditional moves

Family Cites Families (138)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4569016A (en) 1983-06-30 1986-02-04 International Business Machines Corporation Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system
JPS60103482A (en) 1983-10-24 1985-06-07 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Data processor having vector processing capacity
JPS60136872A (en) 1983-12-26 1985-07-20 Hitachi Ltd Vector processor
JPS6266377A (en) * 1985-09-19 1987-03-25 Fujitsu Ltd Mask pattern generation system
JPH0731669B2 (en) 1986-04-04 1995-04-10 株式会社日立製作所 Vector processor
US5113521A (en) 1988-03-18 1992-05-12 Digital Equipment Corporation Method and apparatus for handling faults of vector instructions causing memory management exceptions
US5043867A (en) 1988-03-18 1991-08-27 Digital Equipment Corporation Exception reporting mechanism for a vector processor
US5974522A (en) 1990-01-24 1999-10-26 Cornell Research Foundation, Inc. Machine for processing interrupted out-of-order instructions
US5247524A (en) 1990-06-29 1993-09-21 Digital Equipment Corporation Method for generating a checksum
SG45269A1 (en) * 1992-02-06 1998-01-16 Intel Corp End bit markers for instruction decode
US5388233A (en) * 1993-04-30 1995-02-07 Intel Corporation Method and apparatus for counting instruction types using bit masks and a programmable bit map
WO1994027215A1 (en) 1993-05-07 1994-11-24 Apple Computer, Inc. Method for decoding guest instructions for a host computer
US5487159A (en) 1993-12-23 1996-01-23 Unisys Corporation System for processing shift, mask, and merge operations in one instruction
US5673407A (en) 1994-03-08 1997-09-30 Texas Instruments Incorporated Data processor having capability to perform both floating point operations and memory access in response to a single instruction
US5551013A (en) 1994-06-03 1996-08-27 International Business Machines Corporation Multiprocessor for hardware emulation
JP3672634B2 (en) 1994-09-09 2005-07-20 株式会社ルネサステクノロジ Data processing device
US5680338A (en) * 1995-01-04 1997-10-21 International Business Machines Corporation Method and system for vector processing utilizing selected vector elements
US5825678A (en) 1995-03-31 1998-10-20 International Business Machines Corporation Method and apparatus for determining floating point data class
US5663952A (en) 1995-07-07 1997-09-02 Sun Microsystems, Inc. Checksum generation circuit and method
US7301541B2 (en) 1995-08-16 2007-11-27 Microunity Systems Engineering, Inc. Programmable processor and method with wide operations
US5701316A (en) 1995-08-31 1997-12-23 Unisys Corporation Method for generating an internet protocol suite checksum in a single macro instruction
US5790825A (en) 1995-11-08 1998-08-04 Apple Computer, Inc. Method for emulating guest instructions on a host computer through dynamic recompilation of host instructions
JP2904099B2 (en) * 1996-02-19 1999-06-14 日本電気株式会社 Compiling device and compiling method
US5768168A (en) 1996-05-30 1998-06-16 Lg Semicon Co., Ltd. Universal galois field multiplier
GB9627069D0 (en) 1996-12-30 1997-02-19 Certicom Corp A method and apparatus for finite field multiplication
US5884071A (en) 1997-03-31 1999-03-16 Intel Corporation Method and apparatus for decoding enhancement instructions using alias encodings
US5960012A (en) 1997-06-23 1999-09-28 Sun Microsystems, Inc. Checksum determination using parallel computations on multiple packed data elements
US5953240A (en) 1997-06-23 1999-09-14 Sun Microsystems, Inc. SIMD TCP/UDP checksumming in a CPU
US6088782A (en) 1997-07-10 2000-07-11 Motorola Inc. Method and apparatus for moving data in a parallel processor using source and destination vector registers
US6047304A (en) 1997-07-29 2000-04-04 Nortel Networks Corporation Method and apparatus for performing lane arithmetic to perform network processing
US5864703A (en) 1997-10-09 1999-01-26 Mips Technologies, Inc. Method for providing extended precision in SIMD vector arithmetic operations
US6009261A (en) 1997-12-16 1999-12-28 International Business Machines Corporation Preprocessing of stored target routines for emulating incompatible instructions on a target processor
US6223320B1 (en) 1998-02-10 2001-04-24 International Business Machines Corporation Efficient CRC generation utilizing parallel table lookup operations
US6105129A (en) 1998-02-18 2000-08-15 Advanced Micro Devices, Inc. Converting register data from a first format type to a second format type if a second type instruction consumes data produced by a first type instruction
US6173393B1 (en) * 1998-03-31 2001-01-09 Intel Corporation System for writing select non-contiguous bytes of data with single instruction having operand identifying byte mask corresponding to respective blocks of packed data
US6308255B1 (en) 1998-05-26 2001-10-23 Advanced Micro Devices, Inc. Symmetrical multiprocessing bus and chipset used for coprocessor support allowing non-native code to run in a system
US6038652A (en) 1998-09-30 2000-03-14 Intel Corporation Exception reporting on function generation in an SIMD processor
US6760837B1 (en) 1998-10-06 2004-07-06 Texas Instruments Incorporated Bit field processor
US6463582B1 (en) 1998-10-21 2002-10-08 Fujitsu Limited Dynamic optimizing object code translator for architecture emulation and dynamic optimizing object code translation method
US6324670B1 (en) 1999-03-24 2001-11-27 Novell, Inc. Checksum generator with minimum overflow
FR2796736B1 (en) 1999-07-20 2001-11-30 St Microelectronics Sa METHOD FOR PERFORMING ACCUMULATION MULTIPLICATION IN A GALOIS BODY
US6675292B2 (en) 1999-08-13 2004-01-06 Sun Microsystems, Inc. Exception handling for SIMD floating point-instructions using a floating point status register to report exceptions
US6760742B1 (en) 2000-02-18 2004-07-06 Texas Instruments Incorporated Multi-dimensional galois field multiplier
US6711602B1 (en) 2000-02-18 2004-03-23 Texas Instruments Incorporated Data processor with flexible multiply unit
US6701424B1 (en) * 2000-04-07 2004-03-02 Nintendo Co., Ltd. Method and apparatus for efficient loading and storing of vectors
US7847803B1 (en) 2000-07-26 2010-12-07 Ati Technologies Ulc Method and apparatus for interleaved graphics processing
US6877084B1 (en) * 2000-08-09 2005-04-05 Advanced Micro Devices, Inc. Central processing unit (CPU) accessing an extended register set in an extended register mode
US6643821B2 (en) 2000-11-30 2003-11-04 Stmicroelectronics, Inc. Method and device for computing incremental checksums
US6848074B2 (en) 2001-06-21 2005-01-25 Arc International Method and apparatus for implementing a single cycle operation in a data processing system
US6839828B2 (en) 2001-08-14 2005-01-04 International Business Machines Corporation SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode
US20030037085A1 (en) * 2001-08-20 2003-02-20 Sandbote Sam B. Field processing unit
US20040054877A1 (en) * 2001-10-29 2004-03-18 Macy William W. Method and apparatus for shuffling data
US7013321B2 (en) 2001-11-21 2006-03-14 Sun Microsystems, Inc. Methods and apparatus for performing parallel integer multiply accumulate operations
US7082452B2 (en) 2001-11-30 2006-07-25 Analog Devices, Inc. Galois field multiply/multiply-add/multiply accumulate
US7313583B2 (en) 2002-10-22 2007-12-25 Broadcom Corporation Galois field arithmetic unit for use within a processor
US20090199075A1 (en) 2002-11-25 2009-08-06 Victor Demjanenko Array form reed-solomon implementation as an instruction set extension
JP3818263B2 (en) 2003-01-28 2006-09-06 日本電気株式会社 AES encryption processing device, AES decryption processing device, AES encryption / decryption processing device, AES encryption processing method, AES decryption processing method, and AES encryption / decryption processing method
US7139900B2 (en) 2003-06-23 2006-11-21 Intel Corporation Data packet arithmetic logic devices and methods
US7275148B2 (en) * 2003-09-08 2007-09-25 Freescale Semiconductor, Inc. Data processing system using multiple addressing modes for SIMD operations and method thereof
US7096399B2 (en) 2003-09-11 2006-08-22 Intel Corporation Monitoring packet content
US7383483B2 (en) 2003-12-11 2008-06-03 International Business Machines Corporation Data transfer error checking
US7493481B1 (en) * 2004-05-17 2009-02-17 Netxen, Inc. Direct hardware processing of internal data structure fields
US7363574B1 (en) 2004-10-12 2008-04-22 Nortel Networks Limited Method and system for parallel CRC calculation
US20060106910A1 (en) 2004-11-16 2006-05-18 Analog Devices, Inc. Galois field polynomial multiplication
US7512647B2 (en) 2004-11-22 2009-03-31 Analog Devices, Inc. Condensed Galois field computing system
WO2006121444A1 (en) 2005-05-10 2006-11-16 Telairity Semiconductor, Inc. Vector processor with special purpose registers and high speed memory access
FR2885711B1 (en) 2005-05-12 2007-07-06 Atmel Corp METHOD AND MODULAR AND RANDOM EQUIPMENT FOR POLYNOMIAL REDUCTION
US7400271B2 (en) 2005-06-21 2008-07-15 International Characters, Inc. Method and apparatus for processing character streams
US7333917B2 (en) 2005-08-11 2008-02-19 The University Of North Carolina At Chapel Hill Novelty detection systems, methods and computer program products for real-time diagnostics/prognostics in complex physical systems
US7421566B2 (en) 2005-08-12 2008-09-02 International Business Machines Corporation Implementing instruction set architectures with non-contiguous register file specifiers
US9436468B2 (en) * 2005-11-22 2016-09-06 Intel Corporation Technique for setting a vector mask
US7925957B2 (en) 2006-03-20 2011-04-12 Intel Corporation Validating data using processor instructions
US20080021943A1 (en) 2006-07-20 2008-01-24 Advanced Micro Devices, Inc. Equality comparator using propagates and generates
US7600104B2 (en) 2006-08-15 2009-10-06 Peter Neumann Method and system for parallel vector data processing of vector data having a number of data elements including a defined first bit-length
US8062303B2 (en) 2006-08-16 2011-11-22 K2M, Inc. Apparatus and methods for inserting an implant
JP4374363B2 (en) 2006-09-26 2009-12-02 Okiセミコンダクタ株式会社 Bit field operation circuit
US7624251B2 (en) 2006-11-01 2009-11-24 Apple Inc. Instructions for efficiently accessing unaligned partial vectors
US8346839B2 (en) 2007-03-30 2013-01-01 Intel Corporation Efficient advanced encryption standard (AES) datapath using hybrid rijndael S-box
US8560591B2 (en) 2007-04-25 2013-10-15 International Business Machines Corporation Detection of potential need to use a larger data format in performing floating point operations
US8055886B2 (en) 2007-07-12 2011-11-08 Texas Instruments Incorporated Processor micro-architecture for compute, save or restore multiple registers and responsive to first instruction for repeated issue of second instruction
US9529592B2 (en) * 2007-12-27 2016-12-27 Intel Corporation Vector mask memory access instructions to perform individual and sequential memory access operations if an exception occurs during a full width memory access operation
US8112691B1 (en) 2008-03-25 2012-02-07 Oracle America, Inc. Method for efficient generation of a Fletcher checksum using a single SIMD pipeline
US8255443B2 (en) 2008-06-03 2012-08-28 International Business Machines Corporation Execution unit with inline pseudorandom number generator
US8051226B2 (en) * 2008-06-13 2011-11-01 Freescale Semiconductor, Inc. Circular buffer support in a single instruction multiple data (SIMD) data processor
US8340280B2 (en) 2008-06-13 2012-12-25 Intel Corporation Using a single instruction multiple data (SIMD) instruction to speed up galois counter mode (GCM) computations
JP5268469B2 (en) 2008-07-23 2013-08-21 株式会社東芝 High availability system and execution state control method
US8793472B2 (en) * 2008-08-15 2014-07-29 Apple Inc. Vector index instruction for generating a result vector with incremental values based on a start value and an increment value
US8175265B2 (en) 2008-09-02 2012-05-08 Apple Inc. Systems and methods for implementing block cipher algorithms on attacker-controlled systems
GB2464292A (en) 2008-10-08 2010-04-14 Advanced Risc Mach Ltd SIMD processor circuit for performing iterative SIMD multiply-accumulate operations
CN101430881B (en) 2008-11-10 2013-04-17 华为技术有限公司 Encoding, decoding and encoding/decoding method, encoding/decoding system and correlated apparatus
US8280040B2 (en) 2009-02-04 2012-10-02 Globalfoundries Inc. Processor instructions for improved AES encryption and decryption
CN101901127B (en) 2009-05-31 2012-07-25 国际商业机器公司 Galois field multiplier
GB2470782B (en) 2009-06-05 2014-10-22 Advanced Risc Mach Ltd A data processing apparatus and method for handling vector instructions
US8918623B2 (en) 2009-08-04 2014-12-23 International Business Machines Corporation Implementing instruction set architectures with non-contiguous register file specifiers
US20110047358A1 (en) 2009-08-19 2011-02-24 International Business Machines Corporation In-Data Path Tracking of Floating Point Exceptions and Store-Based Exception Indication
US9003170B2 (en) * 2009-12-22 2015-04-07 Intel Corporation Bit range isolation instructions, methods, and apparatus
CN102122241A (en) 2010-01-08 2011-07-13 复旦大学 Analog multiplier/divider applicable to prime field and polynomial field
US8850166B2 (en) 2010-02-18 2014-09-30 International Business Machines Corporation Load pair disjoint facility and instruction therefore
US8417961B2 (en) 2010-03-16 2013-04-09 Oracle International Corporation Apparatus and method for implementing instruction support for performing a cyclic redundancy check (CRC)
US8645669B2 (en) 2010-05-05 2014-02-04 International Business Machines Corporation Cracking destructively overlapping operands in variable length instructions
US8539472B2 (en) 2010-06-09 2013-09-17 Lear Corporation Method and system of updating shared memory
US20110314263A1 (en) 2010-06-22 2011-12-22 International Business Machines Corporation Instructions for performing an operation on two operands and subsequently storing an original value of operand
US8903882B2 (en) 2010-12-13 2014-12-02 International Business Machines Corporation Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product
WO2012134532A1 (en) 2011-04-01 2012-10-04 Intel Corporation Vector friendly instruction format and execution thereof
KR101572770B1 (en) 2011-09-26 2015-11-27 인텔 코포레이션 Instruction and logic to provide vector load-op/store-op with stride functionality
US9665371B2 (en) 2011-11-30 2017-05-30 Intel Corporation Providing vector horizontal compare functionality within a vector register
CN106502624B (en) 2011-11-30 2019-10-18 英特尔公司 For providing processor, equipment and the processing system of vector transverse direction majority voting function
US10157061B2 (en) 2011-12-22 2018-12-18 Intel Corporation Instructions for storing in general purpose registers one of two scalar constants based on the contents of vector write masks
CN104025020B (en) 2011-12-23 2017-06-13 英特尔公司 System, device and method for performing masked bits compression
WO2013095661A1 (en) 2011-12-23 2013-06-27 Intel Corporation Systems, apparatuses, and methods for performing conversion of a list of index values into a mask value
US10037205B2 (en) 2011-12-23 2018-07-31 Intel Corporation Instruction and logic to provide vector blend and permute functionality
CN104169867B (en) 2011-12-23 2018-04-13 英特尔公司 For performing the systems, devices and methods of conversion of the mask register to vector registor
US9575757B2 (en) 2011-12-30 2017-02-21 Intel Corporation Efficient zero-based decompression
US9459864B2 (en) 2012-03-15 2016-10-04 International Business Machines Corporation Vector string range compare
US9715383B2 (en) 2012-03-15 2017-07-25 International Business Machines Corporation Vector find element equal instruction
US9710266B2 (en) 2012-03-15 2017-07-18 International Business Machines Corporation Instruction to compute the distance to a specified memory boundary
US9459868B2 (en) 2012-03-15 2016-10-04 International Business Machines Corporation Instruction to load data up to a dynamically determined memory boundary
US9459867B2 (en) 2012-03-15 2016-10-04 International Business Machines Corporation Instruction to load data up to a specified memory boundary indicated by the instruction
US9588762B2 (en) 2012-03-15 2017-03-07 International Business Machines Corporation Vector find element not equal instruction
CN102819710B (en) 2012-08-22 2014-11-12 西北工业大学 Cross-site script vulnerability detection method based on percolation test
US9606961B2 (en) 2012-10-30 2017-03-28 Intel Corporation Instruction and logic to provide vector compress and rotate functionality
US9411589B2 (en) 2012-12-11 2016-08-09 International Business Machines Corporation Branch-free condition evaluation
US9256427B2 (en) 2012-12-11 2016-02-09 International Business Machines Corporation Tracking multiple conditions in a general purpose register and instruction therefor
US9152419B2 (en) 2012-12-18 2015-10-06 Intel Corporation Instruction set for supporting wide scalar pattern matches
US9411584B2 (en) 2012-12-29 2016-08-09 Intel Corporation Methods, apparatus, instructions, and logic to provide vector address conflict detection functionality
US9372692B2 (en) 2012-12-29 2016-06-21 Intel Corporation Methods, apparatus, instructions, and logic to provide permute controls with leading zero count functionality
US9411592B2 (en) 2012-12-29 2016-08-09 Intel Corporation Vector address conflict resolution with vector population count functionality
US9778932B2 (en) 2013-01-23 2017-10-03 International Business Machines Corporation Vector generate mask instruction
US9471308B2 (en) 2013-01-23 2016-10-18 International Business Machines Corporation Vector floating point test data class immediate instruction
US9513906B2 (en) 2013-01-23 2016-12-06 International Business Machines Corporation Vector checksum instruction
US9823924B2 (en) 2013-01-23 2017-11-21 International Business Machines Corporation Vector element rotate and insert under mask instruction
US9804840B2 (en) 2013-01-23 2017-10-31 International Business Machines Corporation Vector Galois Field Multiply Sum and Accumulate instruction
US9715385B2 (en) 2013-01-23 2017-07-25 International Business Machines Corporation Vector exception code
US9886277B2 (en) 2013-03-15 2018-02-06 Intel Corporation Methods and apparatus for fusing instructions to provide OR-test and AND-test functionality on multiple test sources
US9513907B2 (en) 2013-08-06 2016-12-06 Intel Corporation Methods, apparatus, instructions and logic to provide vector population count functionality
US9495155B2 (en) 2013-08-06 2016-11-15 Intel Corporation Methods, apparatus, instructions and logic to provide population count functionality for genome sequencing and alignment
US9552205B2 (en) 2013-09-27 2017-01-24 Intel Corporation Vector indexed memory access plus arithmetic and/or logical operation processors, methods, systems, and instructions
US9436434B2 (en) 2014-03-14 2016-09-06 International Business Machines Corporation Checksum adder

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053986A (en) * 1990-02-21 1991-10-01 Stardent Computer, Inc. Circuit for preservation of sign information in operations for comparison of the absolute value of operands
US6748522B1 (en) * 2000-10-31 2004-06-08 International Business Machines Corporation Performance monitoring based on instruction sampling in a microprocessor
US7480787B1 (en) * 2006-01-27 2009-01-20 Sun Microsystems, Inc. Method and structure for pipelining of SIMD conditional moves

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US9778932B2 (en) 2017-10-03
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US9740482B2 (en) 2017-08-22
GB2524440A (en) 2015-09-23
US20150143075A1 (en) 2015-05-21
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DE112013005466T5 (en) 2015-08-13
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GB201513183D0 (en) 2015-09-09
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