EP4004713A1 - Mise à jour d'un micrologiciel dans un jeu de puces d'un dispositif périphérique - Google Patents

Mise à jour d'un micrologiciel dans un jeu de puces d'un dispositif périphérique

Info

Publication number
EP4004713A1
EP4004713A1 EP19790775.1A EP19790775A EP4004713A1 EP 4004713 A1 EP4004713 A1 EP 4004713A1 EP 19790775 A EP19790775 A EP 19790775A EP 4004713 A1 EP4004713 A1 EP 4004713A1
Authority
EP
European Patent Office
Prior art keywords
chipset
microcontroller
host
memory
firmware image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP19790775.1A
Other languages
German (de)
English (en)
Inventor
Jean-Luc BISSON
Alain Sales
Sylvain Sevamy
Emmanuel Lemay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seagate Technology LLC
Original Assignee
Seagate Technology LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seagate Technology LLC filed Critical Seagate Technology LLC
Publication of EP4004713A1 publication Critical patent/EP4004713A1/fr
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G06F21/572—Secure firmware programming, e.g. of basic input output system [BIOS]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1433—Saving, restoring, recovering or retrying at system level during software upgrading
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G06F21/575—Secure boot

Definitions

  • Various embodiments of the present disclosure are generally directed to updating firmware (FW) in a chipset, such as a chipset of a peripheral device coupled to a host device.
  • FW firmware
  • a chipset coupled to a host device is provided with a chipset microcontroller and a chipset memory.
  • the chipset microcontroller is placed in an inactive state, such as during a boot reinitialization sequence.
  • a host microcontroller writes a firmware image, representing updated firmware for the chipset microcontroller, directly to the chipset memory such as through the use of an SPI (Serial Peripheral Interface) connection.
  • the host microcontroller subsequently reads back the transferred firmware image from the chipset memory to verify a successful transfer of the firmware image.
  • the chipset microcontroller is subsequently transitioned to an active state to execute the transferred firmware image.
  • the chipset may form a controller of a computer peripheral device, such as a data storage device.
  • the firmware image may be supplied from the host microcontroller using an HID (Human Interface Device) of the data storage device.
  • FIG. 1 provides a functional block representation of a data storage device to provide an exemplary operational environment for various embodiments of the present disclosure.
  • FIG. 2 shows the storage device of FIG. 1 operably coupled to a host device in accordance with some embodiments.
  • FIG. 3 shows a sequence in which an updated firmware (FW) image is loaded to the storage device using the host device.
  • FIG. 4 provides a schematic diagram to illustrate the loading of the updated FW image by the host of FIG. 3 in some embodiments.
  • FIG. 5 is a flow chart for a FW update routine.
  • FIG. 6 is a functional block diagram of a solid state drive (SSD) type data storage device in which various embodiments may be advantageously practiced.
  • SSD solid state drive
  • FIG. 7 is a functional block diagram of a hard disc drive (HDD) or hybrid type data storage device in which various embodiments may be advantageously practiced.
  • HDD hard disc drive
  • hybrid type data storage device in which various embodiments may be advantageously practiced.
  • the present disclosure generally relates to the updating of firmware (FW) in a chipset, such as a chipset in a peripheral device connected to a host device over an interface.
  • firmware FW
  • Peripheral devices also sometimes referred to as computer peripherals, are a class of devices that are separate from, but provide enhanced functionality to, a core computer (also referred to as a host device). Peripheral devices can include input devices, output devices, storage devices, etc. A suitable wired or wireless interface is typically provided to enable bi-directional communication between the peripheral device and the host device. Peripheral devices may be internal or external to a housing of the host device.
  • chipsets which constitute an integrated circuit package having one or more programmable microcontrollers (also referred to as controllers or processors) and associated memory.
  • chipsets are also sometimes referred to as SOCs (Systems on Chip) and may be supported and interconnected on an electronic circuit board.
  • the microcontrollers execute programming instructions in the form of firmware (FW) stored in the associated memory location.
  • firmware firmware
  • firmware will be understood broadly as computerized instructions stored in a memory and executed by a programmable processor to control the operation of the device.
  • Firmware may alternatively be referred to as software, code, programming instructions, executable data, scripts, etc.
  • a boot sequence may be carried out during which the firmware (or a portion thereof) may be loaded to a local volatile memory, such as DRAM. Thereafter, the firmware is sequentially executed to control the operation of the device.
  • firmware provides a certain amount of flexibility with new product development as well as with addressing limitations or problems discovered later on during the life cycle of a product, since a firmware upgrade is far less intrusive than the installation of new, replacement hardwired logic circuitry.
  • Various embodiments of the present disclosure are directed to a method and apparatus for updating firmware in a chipset having a microcontroller and a memory, such as in a peripheral device coupled to a host device.
  • the peripheral device will be a data storage device such as an internal or external solid-state drive (SSD), hard disc drive (HDD), hybrid drive, etc.
  • the storage device is configured to communicate with the host device over a main interface, such as via the so-called USB (Universal Serial Bus) interface.
  • a separate interface such as but not limited to an SPI (Serial Peripheral Interface) is provided to allow duplex communications between the host and the peripheral device in a master/slave relationship using a separate interface circuit, such as an HID (Human Interface Device) module.
  • a microcontroller of the host device is configured to have direct write privileges to a local memory in the peripheral device via the separate interface. Both the main and SPI channels may use the same USB cable (e.g., Thunderbolt 3.0, etc.).
  • the system works by generating and loading a flash image of a new version of firmware to the host device.
  • the firmware image is transferred directly to the local memory of the storage device using the HID of the storage device.
  • a single peripheral device may be updated, or a number of peripheral devices may be updated in turn during a concurrent firmware upgrade.
  • the microcontroller of the host device performs an authorized boot of each peripheral device to reinitialize the device.
  • the host places the peripheral device in an update mode, so that each of the local microcontrollers in the peripheral devices is reset and temporarily disabled.
  • SPI switches associated with the SPI interface are set to connect the host microcontroller to the local storage device memory to receive the firmware update.
  • the updated flash image is directly written to each device in turn, and read back for verification, while the local storage device microcontroller is disabled. If any exception cases are identified, the process can be repeated.
  • the sequence can be triggered by the connection of the HID to the host; for example, the host detects new firmware, and initiates the boot reset mode with the peripheral device to initiate the transfer.
  • a user input of the HID such as a button that is depressed by the user, can be used to initiate the HID protocol transfers.
  • the local controller in the device being updated is placed in a reset condition so that it is not involved in the update process.
  • the actual firmware to be executed is transferred directly to the peripheral on a bit-by-bit basis.
  • check sums or other parity type values can be used as part of the transfer process, but such are not required.
  • authentication sequences can be carried out between the host, the HID and/or the peripheral device(s) prior to the image transfer.
  • the various embodiments provide a unified solution to easily and safely update firmware of a chipset on an electronic board, such as but not limited to a chipset in a peripheral device.
  • the firmware can be flashed even if the associated chipset is non functional.
  • No dedicated computer drivers or other elements are required to carry out the transfer, and the process can be carried out using any host OS configuration.
  • the storage device 100 includes a controller 102 and a memory module 104.
  • the controller 102 provides top level control for the device 100 and may be configured as one or more programmable microcontrollers (also referred to as controllers or processors) with associated programming (firmware, FW) stored in local memory.
  • the microcontrollers may be arranged in one or more SOCs (systems on chip), also referred to as chip sets.
  • the memory module 104 can be arranged as one or more non-volatile memory (NVM) elements including rotatable magnetic recording discs and solid-state memory arrays. While a separate controller 102 is shown in FIG. 1, such is unnecessary as alternative embodiments may incorporate any requisite controller functions directly into the memory module, or external to the data storage device.
  • NVM non-volatile memory
  • FIG. 2 shows another storage device 1 10 that generally corresponds to the storage device 100 of FIG. 1.
  • the data storage device 110 is a solid-state drive (SSD) that utilizes NAND flash memory to store and retrieve user data for a host device 120.
  • the SSD 120 is a computer peripheral for the host 110.
  • the storage device 1 10 has various elements that map to FIG. 1. These elements include a main interface (I/F) circuit 112 that communicates with the host device 120 over a main interface connection (e.g., PCIe, SAS, Ethernet, etc.). While not limiting, it is contemplated that the main connection comprises a USB (Universal Serial Bus) 3.0 Thunderbolt interface.
  • a main interface connection e.g., PCIe, SAS, Ethernet, etc.
  • USB Universal Serial Bus
  • a separate HID (Human Interface Device) circuit 114 of the storage device 110 provides a separate, generic interface for the host device to carry out various configuration and status operations relating to the storage device, including a firmware upgrade as discussed below.
  • a chipset 116 of the storage device 110 includes a storage microcontroller and associated memory to provide top level control for the storage device 110. The chipset may be realized as a single SOC (System on Chip) device or multiple integrated circuits (ICs).
  • NVM 118 represents a main store flash memory to which user data are stored and retrieved by the host device 120.
  • the host device 120 may take the form of a computer or other device that uses the NVM 1 18 of the storage device 1 10 as a main store for user data.
  • the host device 120 includes a host I/F circuit 122 configured to communicate with the storage device 110 over both the main bus and the special SPI bus (or other configured secondary communication path).
  • the host device 120 further includes a main microcontroller 124 that provides top level control of the host device.
  • a host memory 126 stores various data, programming and control information, including a host OS (Operating System) 126 and, at such times that a firmware upgrade is desired for the storage device 110, a firmware (FW) image 128.
  • the firmware 120 represents the programming instructions executed by the storage microcontroller of the chipset 116.
  • FIG. 3 shows a generalized system (apparatus) 140 whereby a firmware upgrade is provided to the storage device 1 10 by the host device 120 using the HID 114. More details are set forth below, but at a top level, the system 140 commences operation with the connection of the host device 120 to the HID 114. From there, the firmware image 128 is transferred to the embedded memory (e.g., flash) of the chipset 116. The host microprocessor writes the firmware image to the storage memory, and then reads it back from the storage memory for verification purposes.
  • the embedded memory e.g., flash
  • FIG. 4 describes the firmware update process by the system 140 in greater detail.
  • the schematic shows an update sequence upon N nominally identical peripheral devices, although the sequence can be applied to just a single device.
  • Each of the N peripheral devices are contemplated as corresponding to a nominally identical copy of the storage device 110.
  • Each peripheral device includes a chipset 150 that generally corresponds to the chipset 116 discussed above.
  • Each chipset has 150 various elements including a chipset microcontroller (MC) 152 and associated chipset memory 154.
  • MC chipset microcontroller
  • the memory 154 will be non-volatile flash memory, such as NAND or NOR flash, although other forms of memory may be used including volatile or non volatile memory.
  • the memory 154 stores the firmware executed by the associated chipset microcontroller 152. In some cases, the firmware image may be transferred to volatile memory within the chipset, after which the image is transferred to corresponding non-volatile memory.
  • a host microcontroller 156 corresponding to the host controller 122 provides top level control of the process, including activation of SPI (Serial Peripheral Interface) switches 158 and the writing of the flash image bits to the flash memories 154 over an SPI interface 160.
  • SPI Serial Peripheral Interface
  • the SPI switches 158 may form a portion of the chipsets 150, or may be separate elements.
  • the HID is enumerated from a USB connection, so the dedicated HID app does not require special privileges or drivers to interconnect with the host.
  • the firmware image in binary form, is forwarded from the HID to the peripheral memory.
  • the process may be initialized by activating an HID interface, such as by depressing an HID user button 162. Other mechanisms and sequences can be used.
  • FIG. 5 provides a firmware (FW) update routine 200 to describe the operation of FIGS. 3-4 in greater detail.
  • the routine 200 describes the updating of a single peripheral device (e.g., the SSD 1 10 in FIG. 2), although the various steps can be repeated as desired to process multiple peripheral devices as illustrated in FIG. 4.
  • the storage device is coupled to the host device using a suitable interconnection that includes the USB/SPI paths, as shown by step 202.
  • the host detects the HID and recognizes a new firmware image is to be loaded.
  • An HID application at the host device may be activated at this time to facilitate the data transfer.
  • a boot sequence for the storage device is initiated at step 206 to reset the storage device.
  • the microcontroller 152 in each chipset 150 is placed in a reset mode so as to be temporarily deactivated, step 208. This includes the setting of the SPI switch(es) 158 necessary to enable the controller 156 to write the firmware image directly to the associated chipset memory 152, step 210.
  • the image bits may be written to a local circuit that in turn writes to the flash memory.
  • the flash image is thereafter written sequentially to the flash in a form that will be subsequently used by the associated chipset microcontroller.
  • EDC error detection and correction
  • check sums, parity values, etc. may be transferred to protect the firmware image payload during transfer to the associated peripheral device.
  • the microcontroller 156 causes the written image to be sequentially read back to the host device 120, step 212. This is for purposes of verification that the image was written properly.
  • This verification step can be carried out in a number of ways.
  • the recovered image can be compared bit-by-bit to the written image.
  • a suitable hash function e.g., SHA 256, etc.
  • step 216 If any errors are detected, the process is repeated. Once the flash image has been successfully written and verified, the microcontroller 152 in the chipset 150 is released to complete the initialization process using the newly written firmware, step 214, and normal operation between the host and the storage device is resumed, step 216.
  • FIGS. 6 and 7 have been provided to illustrate further details regarding suitable environments for the use of HID based firmware updates described herein.
  • FIG. 7 shows a functional block diagram for a solid state drive (SSD) data storage device 300 in accordance with some embodiments.
  • SSD solid state drive
  • a controller 302 provides top level control for the device 300 and may correspond to the controller 102 of FIG. 1.
  • An interface circuit 304 and local buffer memory 306 coordinate the transfer of user data between an external host device and a flash memory 308.
  • the interface circuit 304 includes the main interface and special HID interface capabilities as discussed above.
  • a read/write/erase circuit 310 performs the requisite encoding of input write data and directs the programming of the appropriate flash memory cells to write the encoded write data to the memory 308.
  • FW 312 represents the firmware updated by the routine of FIG. 5. The firmware enables the controller 302 to manage the transfer of data between the flash memory 308 and the associated host, as well as other required functionality of the SSD.
  • FIG. 7 provides a functional block diagram for a hard disc drive (HDD) or hybrid solid state drive (HSSD) storage device 400 in some embodiments.
  • a controller circuit 402, interface circuit 404 and buffer memory 405 operate as in FIG. 7 to coordinate data transfers with a host device.
  • a flash memory 406 provides local non-volatile semiconductor memory for storage of data.
  • a read/write (R/W) channel 408 and preamplifier/driver (preamp) 410 support transfers of data to a rotatable recording medium (disc) 412 using a data read/write transducer (head) 414. Head position is controlled using a voice coil motor (VCM) 416 and a closed loop servo control circuit 418.
  • VCM voice coil motor
  • Data from the host may be stored to the flash 406 and/or the disc 412 as required.
  • the channel 408 encodes the data during a write operation, and recovers the data during a subsequent read operation.
  • FW 420 represents the firmware updated by the routine of FIG. 5, and enables the controller 402 to manage the transfer of data between the host, flash and disc as well as other functions as required.
  • an HID to present a firmware image for direct loading to a peripheral device, via an HID app executed by the intervening host device, allows the firmware to be updated in a fast and secure manner. Separate authentication operations can be carried out between the HID, host and peripheral as required.
  • the specially configured HID carries within it the capabilities to easily and directly write the firmware image to each peripheral device connected to the host.
  • the transfer can be directed by the host microcontroller in a similar fashion. Regardless, it will be appreciated that the host controller, directly or indirectly, ultimately places the peripheral device into the reset mode and directs the writing of the firmware image via the intervening USB (or other) interface between the host and peripheral devices.
  • chipset While various embodiments have contemplated the chipset to constitute a portion of a computer peripheral, it will be appreciated that the present disclosure is not so limited. Substantially any chipset can be subjected to a firmware upgrade provided the chipset is connected to a host device over a suitable interface.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)

Abstract

L'invention concerne un appareil et un procédé (200) de mise à jour d'un micrologiciel dans un jeu de puces pourvu d'un microcontrôleur et d'une mémoire de jeu de puces. Le microcontrôleur de jeu de puces est placé dans un état inactif (208), par exemple pendant une séquence de réinitialisation à l'amorçage. Un microcontrôleur hôte écrit une image d'un micrologiciel, représentant un micrologiciel mis à jour destiné au microcontrôleur de jeu de puces, directement dans la mémoire de jeu de puces (210) au moyen d'une connexion SPI (interface périphérique série). Le microcontrôleur hôte relit l'image du micrologiciel transférée provenant de la mémoire de jeu de puces de façon à s'assurer d'un transfert réussi de l'image du micrologiciel (212). Le microcontrôleur de jeu de puces est ensuite placé dans un état actif de façon à exécuter l'image du micrologiciel transférée (214). Le jeu de puces peut former un contrôleur d'un dispositif périphérique informatique, tel un dispositif de stockage de données. L'image du micrologiciel peut être fournie à la mémoire de jeu de puces au moyen d'un HID (dispositif d'interface humaine).
EP19790775.1A 2019-07-31 2019-07-31 Mise à jour d'un micrologiciel dans un jeu de puces d'un dispositif périphérique Pending EP4004713A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2019/000898 WO2021019270A1 (fr) 2019-07-31 2019-07-31 Mise à jour d'un micrologiciel dans un jeu de puces d'un dispositif périphérique

Publications (1)

Publication Number Publication Date
EP4004713A1 true EP4004713A1 (fr) 2022-06-01

Family

ID=68296543

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19790775.1A Pending EP4004713A1 (fr) 2019-07-31 2019-07-31 Mise à jour d'un micrologiciel dans un jeu de puces d'un dispositif périphérique

Country Status (2)

Country Link
EP (1) EP4004713A1 (fr)
WO (1) WO2021019270A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116305169B (zh) * 2023-05-12 2023-08-11 天津市中环电子计算机有限公司 一种固件安全检测方法和固件校验方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2702479A4 (fr) * 2011-04-29 2014-10-29 Hewlett Packard Development Co Mise à jour du micrologiciel d'un système informatique
US10922413B2 (en) * 2018-09-27 2021-02-16 Intel Corporation Methods and apparatus to apply a firmware update to a host processor

Also Published As

Publication number Publication date
WO2021019270A1 (fr) 2021-02-04

Similar Documents

Publication Publication Date Title
CN110032405B (zh) 系统开机码存储器管理方法、存储器装置与应用其的电子系统
US9529541B2 (en) Nonvolatile storage device and operating system (OS) image program method thereof
US9245634B2 (en) Initialization of flash storage via an embedded controller
US7549020B2 (en) Method and apparatus for raid on memory
US20080147962A1 (en) Storage subsystem with multiple non-volatile memory arrays to protect against data losses
TW201135746A (en) Method and controller for performing a copy-back operation
US20040030953A1 (en) Fault-tolerant architecture for in-circuit programming
US9817600B2 (en) Configuration information backup in memory systems
KR20080098511A (ko) 두 가지 형태의 저장매체를 이용한 데이터 저장장치
TW202008171A (zh) 資料寫入方法以及儲存控制器
JP2008046791A (ja) 記憶装置、ファームウェア更新方法、及び制御装置
TWI473103B (zh) 快閃記憶體儲存裝置及其不良儲存區域的判定方法
US20230004320A1 (en) Method of managing debugging log in storage device
US20130262398A1 (en) Scatter gather list for data integrity
EP4004713A1 (fr) Mise à jour d'un micrologiciel dans un jeu de puces d'un dispositif périphérique
TWI668569B (zh) 主機記憶體緩衝區配置方法、記憶體儲存裝置與記憶體控制電路單元
US9361123B2 (en) Boot from logical volume spanning plurality of PCI devices
US7287182B2 (en) Method and apparatus for copying data of disk drive in disk array system
US20040167999A1 (en) Data transfer control device, electronic instrument, program and method of fabricating electronic instrument
EP2730993B1 (fr) Procédé de réinitialisation et dispositif de réseau
US20110314236A1 (en) Control apparatus, control method, and storage system
TWI826287B (zh) 管理平台系統及其映像檔修復與除錯方法
US20210319810A1 (en) Method and apparatus for accessing to data in response to power-supply event
JP2024006308A (ja) Ｒａｉｄ構成管理装置、ｒａｉｄ構成管理方法及びｒａｉｄ構成管理プログラム
KR20240008046A (ko) 비휘발성 메모리 장치의 프로그램 상태에 대응하여 데이터를 읽는 장치 및 방법

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: UNKNOWN

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20210604

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN