EP4004713A1

EP4004713A1 - Updating firmware in a chipset of a peripheral device

Info

Publication number: EP4004713A1
Application number: EP19790775.1A
Authority: EP
Inventors: Jean-Luc BISSON; Alain Sales; Sylvain Sevamy; Emmanuel Lemay
Original assignee: Seagate Technology LLC
Current assignee: Seagate Technology LLC
Priority date: 2019-07-31
Filing date: 2019-07-31
Publication date: 2022-06-01
Also published as: WO2021019270A1

Abstract

Apparatus and method (200) for updating firmware in a chipset having a chipset microcontroller and a chipset memory. The chipset microcontroller is placed in an inactive state (208), such as during a boot reinitialization sequence. A host microcontroller writes a firmware image, representing updated firmware for the 5 chipset microcontroller, directly to the chipset memory (210) using an SPI (Serial Peripheral Interface) connection. The host microcontroller reads back the transferred firmware image from the chipset memory to verify a successful transfer of the firmware image (212). The chipset microcontroller is subsequently transitioned to an active state to execute the transferred firmware image (214). The chipset may form a 10 controller of a computer peripheral device, such as a data storage device. The firmware image may be supplied to the chipset memory using an HID (Human Interface Device).

Description

UPDATING FIRMWARE IN A CHIPSET

OF A PERIPHERAL DEVICE

Summary

Various embodiments of the present disclosure are generally directed to updating firmware (FW) in a chipset, such as a chipset of a peripheral device coupled to a host device.

In some embodiments, a chipset coupled to a host device is provided with a chipset microcontroller and a chipset memory. The chipset microcontroller is placed in an inactive state, such as during a boot reinitialization sequence. A host microcontroller writes a firmware image, representing updated firmware for the chipset microcontroller, directly to the chipset memory such as through the use of an SPI (Serial Peripheral Interface) connection. The host microcontroller subsequently reads back the transferred firmware image from the chipset memory to verify a successful transfer of the firmware image. The chipset microcontroller is subsequently transitioned to an active state to execute the transferred firmware image. The chipset may form a controller of a computer peripheral device, such as a data storage device. The firmware image may be supplied from the host microcontroller using an HID (Human Interface Device) of the data storage device.

These and other features and advantages which may characterize various embodiments can be understood in view of the following detailed discussion and the accompanying drawings.

Brief Description of the Drawings

FIG. 1 provides a functional block representation of a data storage device to provide an exemplary operational environment for various embodiments of the present disclosure.

FIG. 2 shows the storage device of FIG. 1 operably coupled to a host device in accordance with some embodiments.

FIG. 3 shows a sequence in which an updated firmware (FW) image is loaded to the storage device using the host device. FIG. 4 provides a schematic diagram to illustrate the loading of the updated FW image by the host of FIG. 3 in some embodiments.

FIG. 5 is a flow chart for a FW update routine.

FIG. 6 is a functional block diagram of a solid state drive (SSD) type data storage device in which various embodiments may be advantageously practiced.

FIG. 7 is a functional block diagram of a hard disc drive (HDD) or hybrid type data storage device in which various embodiments may be advantageously practiced.

Detailed Description

The present disclosure generally relates to the updating of firmware (FW) in a chipset, such as a chipset in a peripheral device connected to a host device over an interface.

Peripheral devices, also sometimes referred to as computer peripherals, are a class of devices that are separate from, but provide enhanced functionality to, a core computer (also referred to as a host device). Peripheral devices can include input devices, output devices, storage devices, etc. A suitable wired or wireless interface is typically provided to enable bi-directional communication between the peripheral device and the host device. Peripheral devices may be internal or external to a housing of the host device.

With continued advancements in circuit complexity, it is increasingly common for peripheral devices to be supplied with chipsets, which constitute an integrated circuit package having one or more programmable microcontrollers (also referred to as controllers or processors) and associated memory. Such chipsets are also sometimes referred to as SOCs (Systems on Chip) and may be supported and interconnected on an electronic circuit board.

The microcontrollers execute programming instructions in the form of firmware (FW) stored in the associated memory location. For reference, the term “firmware” as used herein will be understood broadly as computerized instructions stored in a memory and executed by a programmable processor to control the operation of the device. Firmware may alternatively be referred to as software, code, programming instructions, executable data, scripts, etc.

During device initialization, a boot sequence may be carried out during which the firmware (or a portion thereof) may be loaded to a local volatile memory, such as DRAM. Thereafter, the firmware is sequentially executed to control the operation of the device.

One advantage of the use of firmware is that the system hardware architectures (e.g., processors, buffers, support circuitry, etc. associated with a given chipset) can be stabilized over time and used on a number of different generations of products. New features and capabilities can be added by revisions or updates to the firmware. Firmware thus provides a certain amount of flexibility with new product development as well as with addressing limitations or problems discovered later on during the life cycle of a product, since a firmware upgrade is far less intrusive than the installation of new, replacement hardwired logic circuitry.

Various embodiments of the present disclosure are directed to a method and apparatus for updating firmware in a chipset having a microcontroller and a memory, such as in a peripheral device coupled to a host device. While not limiting, in some embodiments the peripheral device will be a data storage device such as an internal or external solid-state drive (SSD), hard disc drive (HDD), hybrid drive, etc.

The storage device is configured to communicate with the host device over a main interface, such as via the so-called USB (Universal Serial Bus) interface. A separate interface, such as but not limited to an SPI (Serial Peripheral Interface), is provided to allow duplex communications between the host and the peripheral device in a master/slave relationship using a separate interface circuit, such as an HID (Human Interface Device) module. A microcontroller of the host device is configured to have direct write privileges to a local memory in the peripheral device via the separate interface. Both the main and SPI channels may use the same USB cable (e.g., Thunderbolt 3.0, etc.).

Generally, the system works by generating and loading a flash image of a new version of firmware to the host device. The firmware image is transferred directly to the local memory of the storage device using the HID of the storage device. A single peripheral device may be updated, or a number of peripheral devices may be updated in turn during a concurrent firmware upgrade.

The microcontroller of the host device performs an authorized boot of each peripheral device to reinitialize the device. During the boot sequence, the host places the peripheral device in an update mode, so that each of the local microcontrollers in the peripheral devices is reset and temporarily disabled. SPI switches associated with the SPI interface are set to connect the host microcontroller to the local storage device memory to receive the firmware update. The updated flash image is directly written to each device in turn, and read back for verification, while the local storage device microcontroller is disabled. If any exception cases are identified, the process can be repeated.

The sequence can be triggered by the connection of the HID to the host; for example, the host detects new firmware, and initiates the boot reset mode with the peripheral device to initiate the transfer. A user input of the HID, such as a button that is depressed by the user, can be used to initiate the HID protocol transfers.

Once an authorized connection is established, the local controller in the device being updated is placed in a reset condition so that it is not involved in the update process. There is no need to negotiate specific interface requirements or perform other actions to affect the transfer; instead, the actual firmware to be executed is transferred directly to the peripheral on a bit-by-bit basis. As required, check sums or other parity type values can be used as part of the transfer process, but such are not required. While not required, in some embodiments authentication sequences can be carried out between the host, the HID and/or the peripheral device(s) prior to the image transfer.

The various embodiments provide a unified solution to easily and safely update firmware of a chipset on an electronic board, such as but not limited to a chipset in a peripheral device. The firmware can be flashed even if the associated chipset is non functional. No dedicated computer drivers or other elements are required to carry out the transfer, and the process can be carried out using any host OS configuration. These and other features and aspects of various embodiments will be understood beginning with a review of FIG. 1 which generally illustrates an exemplary data storage device 100. The device 100 is presented to provide an exemplary environment in which the various embodiments may be advantageously practiced. The various embodiments set forth herein are not limited to data storage applications and can readily be extended to substantially any other type of computer peripheral, or any other application where a chipset is connectable via an interface to a host device.

The storage device 100 includes a controller 102 and a memory module 104. The controller 102 provides top level control for the device 100 and may be configured as one or more programmable microcontrollers (also referred to as controllers or processors) with associated programming (firmware, FW) stored in local memory. The microcontrollers may be arranged in one or more SOCs (systems on chip), also referred to as chip sets.

The memory module 104 can be arranged as one or more non-volatile memory (NVM) elements including rotatable magnetic recording discs and solid-state memory arrays. While a separate controller 102 is shown in FIG. 1, such is unnecessary as alternative embodiments may incorporate any requisite controller functions directly into the memory module, or external to the data storage device.

FIG. 2 shows another storage device 1 10 that generally corresponds to the storage device 100 of FIG. 1. While not limiting, for purposes of the present discussion it will be contemplated that the data storage device 110 is a solid-state drive (SSD) that utilizes NAND flash memory to store and retrieve user data for a host device 120. As such, the SSD 120 is a computer peripheral for the host 110.

The storage device 1 10 has various elements that map to FIG. 1. These elements include a main interface (I/F) circuit 112 that communicates with the host device 120 over a main interface connection (e.g., PCIe, SAS, Ethernet, etc.). While not limiting, it is contemplated that the main connection comprises a USB (Universal Serial Bus) 3.0 Thunderbolt interface.

A separate HID (Human Interface Device) circuit 114 of the storage device 110 provides a separate, generic interface for the host device to carry out various configuration and status operations relating to the storage device, including a firmware upgrade as discussed below. A chipset 116 of the storage device 110 includes a storage microcontroller and associated memory to provide top level control for the storage device 110. The chipset may be realized as a single SOC (System on Chip) device or multiple integrated circuits (ICs). NVM 118 represents a main store flash memory to which user data are stored and retrieved by the host device 120.

The host device 120 may take the form of a computer or other device that uses the NVM 1 18 of the storage device 1 10 as a main store for user data. The host device 120 includes a host I/F circuit 122 configured to communicate with the storage device 110 over both the main bus and the special SPI bus (or other configured secondary communication path). The host device 120 further includes a main microcontroller 124 that provides top level control of the host device. A host memory 126 stores various data, programming and control information, including a host OS (Operating System) 126 and, at such times that a firmware upgrade is desired for the storage device 110, a firmware (FW) image 128. The firmware 120 represents the programming instructions executed by the storage microcontroller of the chipset 116.

FIG. 3 shows a generalized system (apparatus) 140 whereby a firmware upgrade is provided to the storage device 1 10 by the host device 120 using the HID 114. More details are set forth below, but at a top level, the system 140 commences operation with the connection of the host device 120 to the HID 114. From there, the firmware image 128 is transferred to the embedded memory (e.g., flash) of the chipset 116. The host microprocessor writes the firmware image to the storage memory, and then reads it back from the storage memory for verification purposes.

FIG. 4 describes the firmware update process by the system 140 in greater detail. The schematic shows an update sequence upon N nominally identical peripheral devices, although the sequence can be applied to just a single device. Each of the N peripheral devices are contemplated as corresponding to a nominally identical copy of the storage device 110.

Each peripheral device includes a chipset 150 that generally corresponds to the chipset 116 discussed above. Each chipset has 150 various elements including a chipset microcontroller (MC) 152 and associated chipset memory 154. It is contemplated that the memory 154 will be non-volatile flash memory, such as NAND or NOR flash, although other forms of memory may be used including volatile or non volatile memory. The memory 154 stores the firmware executed by the associated chipset microcontroller 152. In some cases, the firmware image may be transferred to volatile memory within the chipset, after which the image is transferred to corresponding non-volatile memory.

A host microcontroller 156 corresponding to the host controller 122 provides top level control of the process, including activation of SPI (Serial Peripheral Interface) switches 158 and the writing of the flash image bits to the flash memories 154 over an SPI interface 160. The SPI switches 158 may form a portion of the chipsets 150, or may be separate elements.

The HID is enumerated from a USB connection, so the dedicated HID app does not require special privileges or drivers to interconnect with the host. The firmware image, in binary form, is forwarded from the HID to the peripheral memory. The process may be initialized by activating an HID interface, such as by depressing an HID user button 162. Other mechanisms and sequences can be used.

FIG. 5 provides a firmware (FW) update routine 200 to describe the operation of FIGS. 3-4 in greater detail. It will be appreciated that the routine 200 describes the updating of a single peripheral device (e.g., the SSD 1 10 in FIG. 2), although the various steps can be repeated as desired to process multiple peripheral devices as illustrated in FIG. 4.

Initially, the storage device is coupled to the host device using a suitable interconnection that includes the USB/SPI paths, as shown by step 202. At step 204, the host detects the HID and recognizes a new firmware image is to be loaded. An HID application at the host device may be activated at this time to facilitate the data transfer.

A boot sequence for the storage device is initiated at step 206 to reset the storage device. During this reset operation, the microcontroller 152 in each chipset 150 is placed in a reset mode so as to be temporarily deactivated, step 208. This includes the setting of the SPI switch(es) 158 necessary to enable the controller 156 to write the firmware image directly to the associated chipset memory 152, step 210.

As required, the image bits may be written to a local circuit that in turn writes to the flash memory. The flash image is thereafter written sequentially to the flash in a form that will be subsequently used by the associated chipset microcontroller. As desired, error detection and correction (EDC) values such as check sums, parity values, etc. may be transferred to protect the firmware image payload during transfer to the associated peripheral device.

Once the image has been written, the microcontroller 156 causes the written image to be sequentially read back to the host device 120, step 212. This is for purposes of verification that the image was written properly. This verification step can be carried out in a number of ways. In some cases, the recovered image can be compared bit-by-bit to the written image. In other cases, a suitable hash function (e.g., SHA 256, etc.) can be applied to the respective written and recovered images to generate first and second hash values, which are then compared to determine if the hash values match, etc.

If any errors are detected, the process is repeated. Once the flash image has been successfully written and verified, the microcontroller 152 in the chipset 150 is released to complete the initialization process using the newly written firmware, step 214, and normal operation between the host and the storage device is resumed, step 216.

FIGS. 6 and 7 have been provided to illustrate further details regarding suitable environments for the use of HID based firmware updates described herein. FIG. 7 shows a functional block diagram for a solid state drive (SSD) data storage device 300 in accordance with some embodiments.

A controller 302 provides top level control for the device 300 and may correspond to the controller 102 of FIG. 1. An interface circuit 304 and local buffer memory 306 coordinate the transfer of user data between an external host device and a flash memory 308. The interface circuit 304 includes the main interface and special HID interface capabilities as discussed above. A read/write/erase circuit 310 performs the requisite encoding of input write data and directs the programming of the appropriate flash memory cells to write the encoded write data to the memory 308. FW 312 represents the firmware updated by the routine of FIG. 5. The firmware enables the controller 302 to manage the transfer of data between the flash memory 308 and the associated host, as well as other required functionality of the SSD.

FIG. 7 provides a functional block diagram for a hard disc drive (HDD) or hybrid solid state drive (HSSD) storage device 400 in some embodiments. A controller circuit 402, interface circuit 404 and buffer memory 405 operate as in FIG. 7 to coordinate data transfers with a host device. A flash memory 406 provides local non-volatile semiconductor memory for storage of data. A read/write (R/W) channel 408 and preamplifier/driver (preamp) 410 support transfers of data to a rotatable recording medium (disc) 412 using a data read/write transducer (head) 414. Head position is controlled using a voice coil motor (VCM) 416 and a closed loop servo control circuit 418.

Data from the host may be stored to the flash 406 and/or the disc 412 as required. As before, the channel 408 encodes the data during a write operation, and recovers the data during a subsequent read operation. FW 420 represents the firmware updated by the routine of FIG. 5, and enables the controller 402 to manage the transfer of data between the host, flash and disc as well as other functions as required.

It will now be appreciated that the various embodiments presented herein provide a number of benefits over the existing art. The use of an HID to present a firmware image for direct loading to a peripheral device, via an HID app executed by the intervening host device, allows the firmware to be updated in a fast and secure manner. Separate authentication operations can be carried out between the HID, host and peripheral as required. The specially configured HID carries within it the capabilities to easily and directly write the firmware image to each peripheral device connected to the host.

While the system has been described in some embodiments as having the HID controller directing the transfer, in other embodiments the transfer can be directed by the host microcontroller in a similar fashion. Regardless, it will be appreciated that the host controller, directly or indirectly, ultimately places the peripheral device into the reset mode and directs the writing of the firmware image via the intervening USB (or other) interface between the host and peripheral devices.

While various embodiments have contemplated the chipset to constitute a portion of a computer peripheral, it will be appreciated that the present disclosure is not so limited. Substantially any chipset can be subjected to a firmware upgrade provided the chipset is connected to a host device over a suitable interface.

It is to be understood that even though numerous characteristics and advantages of various embodiments of the present disclosure have been set forth in the foregoing description, together with details of the structure and function of various thereof, this detailed description is illustrative only, and changes may be made in detail, especially in matters of structure and arrangements of parts within the principles of the present disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.

Claims

Claims:

1. A method comprising:

placing a microcontroller of a chipset in an inactive state;

writing, via a host device coupled to the chipset, a firmware image to a memory of the chipset associated with the microcontroller; reading back the transferred firmware image from the memory to the host device to verify the transfer was successful; and

transitioning the microcontroller to an active state in which the microcontroller executes the transferred firmware image.

2. The method of claim 1 , wherein the chipset comprises a chipset of a peripheral device coupled to the host device via a selected interface.

3. The method of claim 2, wherein the peripheral device comprises a data storage device having a non-volatile memory (NVM), wherein the firmware image constitutes program instructions used by the microcontroller of the chipset to direct data transfer operations between the NVM and the host device.

4. The method of claim 1, wherein the placing step comprises placing the microcontroller of the chipset in an inactive state by interrupting a boot reinitialization sequence, and wherein the transitioning step comprises resuming the boot reinitialization sequence so that the microcontroller initiates loading and execution of the transferred firmware image to place the chipset in a normal operational mode.

5. The method of claim 1, wherein each of the placing, writing, reading and transitioning steps are carried out by a host microcontroller of the host device, the host microcontroller connected to the chipset via a communication interface.

6. The method of claim 5, wherein the host microcontroller sets an SPI (Serial Peripheral Interface) switch to connect, via an SPI connection path, the host microcontroller to the memory, subsequently transfers the firmware image to the memory over the SPI connection path, and subsequently resets the SPI switch to disconnect the host microcontroller from the memory of the chipset.

7. The method of claim 5, wherein the host controller compares the firmware image transferred to the memory of the chipset to a recovered copy of the firmware image read back from the memory of the chipset to verify the transfer of the firmware image was successful.

8. The method of claim 1, further comprising connecting a human interface device (HID) circuit of the storage device to the host device, the HID transferring the firmware image as a bit-by-bit transfer of the firmware image to the memory of the chipset.

9. The method of claim 7, wherein the HID comprises a user activated button, and wherein the HID transfers the firmware image to the host device responsive to an activation of the button by a user.

10. A method comprising:

placing a microcontroller of a peripheral device in an inactive reset state during a boot reinitialization sequence;

using a human interface device (HID) of the peripheral device to transfer, via a host device coupled to the peripheral device, a firmware image to a memory of the peripheral device associated with the microcontroller; reading back the transferred firmware image from the memory of the peripheral device to the host device to verify the transfer was successful; and transitioning the microcontroller of the peripheral device to an active state to complete the boot reinitialization sequence using the transferred firmware image, the microcontroller of the peripheral device executing the transferred firmware image during the active state thereof.

11. The method of claim 9, wherein the peripheral device comprises a data storage device having a non-volatile memory (NVM), wherein the microcontroller of the peripheral device comprises a storage controller which executes the transferred firmware image to control a transfer of user data between the NVM and the host device.

12. The method of claim 1 1, wherein the data storage device comprises a solid-state drive (SSD) and the NVM comprises flash memory.

13. The method of claim 1 1 , wherein the data storage device comprises a hard disc drive (HDD) or a hybrid drive and the NVM comprises a rotatable magnetic recording disc.

14. The method of claim 10, wherein the peripheral device is connected to the host device via a USB (Universal Serial Bus) interface connection.

15. The method of claim 10, wherein the HID comprises a user activated button, and wherein the HID transfers the firmware image to the host device responsive to an activation of the button by a user.

16. The method of claim 10, wherein a microcontroller of the host device uses a Serial Peripheral Interface (SPI) connection to direct the firmware image to the memory of the peripheral device while the microcontroller of the peripheral device remains in the inactive reset state, and wherein the microcontroller of the host device communicates via a Universal Serial Bus (USB) connection with the microcontroller of the peripheral device while the microcontroller of the peripheral device is in the active state.

17. A data storage device, comprising:

a chipset having a chipset microcontroller and a chipset memory;

a main interface configured to interconnect the data storage device to a host device via a main bus; and

a human interface device (HID) configured to transfer a firmware image from the host device to the chipset memory responsive to receipt of a firmware image and deactivation of the chipset microcontroller by a host microcontroller of the host device, the HID configured to write the firmware image directly to the chipset memory, read back the written firmware image from the chipset memory, verify the firmware image was successfully written to the chipset memory, and reactivate the chipset microcontroller, the chipset microcontroller executing the transferred firmware image written to the chipset memory responsive to the reactivation thereof by the host microcontroller.

18. The apparatus of claim 17, wherein the HID is interconnectable to the host device using a first USB (Universal Serial Bus) connection, wherein the host microcontroller is interconnectable to the chipset using a second USB connection during reactivation of the chipset microcontroller, and wherein the host microcontroller is interconnectable to the chipset using an SPI (Serial Peripheral Interface) connection to transfer, bit-by-bit, the firmware image to the chipset memory.

19. The apparatus of claim 17, wherein host microcontroller transfers the firmware image to the HID responsive to execution of an HID application by the host microcontroller stored in a host memory.

20. The apparatus of claim 17, wherein the peripheral device comprises a selected one of a solid-state drive (SSD), a hard disc drive (HDD) or a hybrid drive.