EP4004681A1 - Distribution de puissance à un hôte à partir d'un dispositif périphérique à deux ports - Google Patents

Distribution de puissance à un hôte à partir d'un dispositif périphérique à deux ports

Info

Publication number
EP4004681A1
EP4004681A1 EP19790780.1A EP19790780A EP4004681A1 EP 4004681 A1 EP4004681 A1 EP 4004681A1 EP 19790780 A EP19790780 A EP 19790780A EP 4004681 A1 EP4004681 A1 EP 4004681A1
Authority
EP
European Patent Office
Prior art keywords
power
psu
data
external
host
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19790780.1A
Other languages
German (de)
English (en)
Inventor
Jean-Luc BISSON
Gaspard PLANTROU
Alexandra-Elena DRAGOMIR
Alain Sales
Sylvain Sevamy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seagate Technology LLC
Original Assignee
Seagate Technology LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seagate Technology LLC filed Critical Seagate Technology LLC
Publication of EP4004681A1 publication Critical patent/EP4004681A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips

Definitions

  • Various embodiments of the present disclosure are generally directed to providing electrical power to a host device from a peripheral device, such as but not limited to a dual port data storage device.
  • a peripheral device is connected to a host device using a first serial cable to establish a first data link and a first power transfer link with a first serial port of the peripheral device.
  • the peripheral device is connected to an external power supply unit (PSU) using a second serial cable to establish a second data link and a second power transfer link with a second serial port of the peripheral device.
  • PSU external power supply unit
  • a controller circuit of the peripheral device uses the second data transfer link to detect available power from the external PSU at a level suitable for use by the host device.
  • the controller circuit transfers, via the first data link, an indication to the host device of the available power from the external PSU, and interconnects the first and second serial ports to flow the conditioned power to the host device via the first and second power transfer links responsive to a request, from the host device to the peripheral device, for the available power via the first data transfer link.
  • FIG. 1 provides a functional block representation of a data storage device to provide an exemplary operational environment for various embodiments of the present disclosure.
  • FIG. 2 shows the storage device of FIG. 1 operably coupled to a host device in accordance with some embodiments.
  • FIG. 3 shows a system by which the host device receives electrical power from the storage device of FIG. 2 in accordance with some embodiments.
  • FIG. 4 shows a power flow configuration for a storage device of the related art.
  • FIG. 5 shows a power flow configuration for the storage device of FIG. 3 in accordance with some embodiments.
  • FIG. 6 is a sequence flow diagram to illustrate activation of the powering of the host in FIG. 3.
  • FIG. 7 is a sequence flow diagram to illustrate deactivation of the powering of the host in FIG. 3.
  • FIG. 8 illustrates a circuit adapted to charge a battery in accordance with some embodiments.
  • FIG. 9 is a functional block diagram of an external power supply unit (PSU) with which various embodiments may be advantageously practiced.
  • PSU external power supply unit
  • FIG. 10 is a functional block diagram of a solid state drive (SSD) type data storage device in which various embodiments may be advantageously practiced.
  • SSD solid state drive
  • FIG. 11 is a functional block diagram of a hard disc drive (HDD) or hybrid type data storage device in which various embodiments may be advantageously practiced.
  • HDD hard disc drive
  • hybrid type data storage device in which various embodiments may be advantageously practiced.
  • the present disclosure generally relates to the distribution of electrical power among elements in a computer system.
  • Peripheral devices also sometimes referred to as computer peripherals, are a class of devices that are separate from, but provide enhanced functionality to, a core computer (also referred to as a host device). Peripheral devices can include input devices, output devices, storage devices, etc. A suitable wired or wireless interface is typically provided to enable bi-directional communication between the peripheral device and the host device. Peripheral devices may be internal or external to a housing of the host device.
  • Thunderbolt describes a class of interconnection mechanisms that are particularly suitable for coupling host and peripheral devices.
  • Current generation Thunderbolt connectors are sometimes referred to as Thunderbolt 3 and/or Type-C serial cables and operate in accordance with the well-known USB (Universal Serial Bus) 3.0 standard.
  • Thunderbolt also sometimes referred to as TBT or TBT3, combines PCIe (Peripheral Computer Interface Express) and DisplayPort (DP) into four serial lanes (max 10 Gbits/sec transfer rate per lane).
  • the interface accommodates the transfer of DC power, and can multiplex the support of up to six (6) connected devices via hub or daisy chain connections.
  • TBT connections accommodates the flow of both data and power, it should be at least theoretically possible to supply electrical power from any device to any other device in a TBT chain.
  • peripheral devices such as data storage devices, tend to have power output capabilities that are insufficient to meet the consumption requirements of a host device, such as to support a host battery charging operation, etc.
  • various embodiments of the present disclosure are generally directed to an apparatus and method for distributing electrical power among elements in a computer system, including but not necessarily limited to devices coupled in a TBT chain.
  • some embodiments provide a dual port peripheral device, such as a storage device, configured to be coupled to a host device using a selected port (e.g., Port A) of the peripheral device.
  • An external power source may be coupled to another selected port of the peripheral device (e.g., Port B). This allows electrical power to be directed, through the peripheral device, from the external source to the host.
  • a controller of the peripheral device is configured to detect the presence of a source of power on port B of the device. Once validated as an acceptable form of power for the host, the controller interconnects this power to the power rails of port A and informs the host that this power is available, should the host elect to receive it.
  • the host may be currently supplying power at a first voltage level on the cable interconnecting the host to Port A of the peripheral device.
  • power at a second voltage may be supplied from the peripheral device to the host via the cable at a specified power profile.
  • the peripheral device may operate as an intelligent docking station to adaptively supply/receive both power and data through a single serial cable between the peripheral device and the host, with the system automatically switching among different power profiles as such become available.
  • FIG. 1 generally illustrates an exemplary data storage device 100.
  • the device 100 is presented to provide an illustrated environment in which the various embodiments may be advantageously practiced.
  • the various embodiments set forth herein are not limited to data storage applications and can readily be extended to substantially any other type of computer peripheral, or any other application where a dual-port device is connectable via an interface to a host device.
  • the storage device 100 includes a controller 102 and a memory module 104.
  • the controller 102 provides top level control for the device 100 and may be configured as one or more programmable microcontrollers (also referred to as controllers or processors) with associated programming (firmware, FW) stored in local memory.
  • the microcontrollers may be arranged in one or more SOCs (systems on chip), also referred to as chip sets.
  • the memory module 104 can be arranged as one or more non-volatile memory (NVM) elements including rotatable magnetic recording discs and solid- state memory arrays. While a separate controller 102 is shown in FIG. 1, such is unnecessary as alternative embodiments may incorporate any requisite controller functions directly into the memory module, or external to the data storage device.
  • NVM non-volatile memory
  • FIG. 2 shows a storage device 110 that generally corresponds to the storage device 100 of FIG. 1. While not limiting, for purposes of the present discussion it will be contemplated that the storage device 110 is a solid-state drive (SSD) that utilizes NAND flash memory to store and retrieve user data for a host device 112. As such, the SSD is a computer peripheral for the host.
  • SSD solid-state drive
  • the storage device 110 has various elements that map to FIG. 1 including a storage microcontroller (CPU) 114, local storage memory 116, non-volatile memory (NVM) 118 and a storage power module 120.
  • the local storage memory 116 may be volatile or non-volatile utilized by the storage microcontroller 114 and which stores various elements such as firmware (FW) 122 and data 124.
  • the firmware 122 represents the programming instructions executed by the microcontroller 114.
  • the data 122 can represent user data, metadata, parameters, etc. useful during data transfer operations between the NVM 118 and the host 112.
  • the microcontroller 114 and memory 116 may be incorporated into an SOC (chipset).
  • the NVM 118 represents flash memory in a separate flash memory module that negotiates data transfer operations with the SOC.
  • the storage power module 120 manages electrical power distribution and flows within and through the storage device 110 in a manner explained below.
  • the host device 112 takes the form of a computer and includes a host microcontroller (CPU) 134, a host memory 136, a user interface (I/F) 138 and a host power module 140.
  • the host microcontroller 134 may take the form of one or more programmable processors.
  • the host memory 136 stores various programming and data elements for the microcontroller 134 including an operating system (OS) 142 and various host applications (apps) 144.
  • OS operating system
  • apps host applications
  • the user I/F 138 can constitute various GUI (Graphical User Interface) type elements such as a touch screen, a display, a mouse, a keyboard, etc. to enable a user to interact with the system.
  • the host power module 140 operates in cooperation with the storage power module 120 of the storage device 110 to transfer power between the respective devices via one or more interfaces 145.
  • Each interface may include one or more sets of data transfer lines 146 and power transfer lines 148.
  • FIG. 3 shows a system 150 that incorporates the storage device 110 and the host device 112 from FIG. 2 in accordance with some embodiments.
  • the storage device 110 is characterized as a dual-port device with first and second ports 152, 154, respectively denoted as Ports A and B.
  • the dual port storage device 110 may have additional ports as well that are not illustrated in FIG. 3.
  • Port A 152 of the storage device is coupled to a host port 156 of the host 112, and Port B 154 is coupled to an external port 158 of an external power source 160.
  • respective port interconnections 162, 164 are configured in accordance with the TBT3 standard, and operate as USB 3.0 interfaces with both power and data transfer capabilities using Type-C serial cables. Other interface configurations can be used.
  • electrical power from the external power source 160 flows through the storage device 110 to the host 112 via the interconnections 162, 164, as managed by power management circuitry 168 of the storage device 110.
  • FIG. 4 shows a data storage device 170 of the related art to briefly illustrate limitations in the ability to transfer electrical power to the host in the manner depicted in FIG. 3.
  • the storage device 170 is coupled to a host device 172, a daisy chained device 174 and a device power supply unit (PSU) 176. These interconnections are carried out using a first port (Port A) 178, a second port (Port B) 180 and a power jack (input) 182.
  • the PSU 176 may be a cord with a transformer that transforms alternating current (AC) power from a wall receptacle to a suitable direct current (DC) level for use by the storage device 110. Other configurations for the PSU 176 can be used as desired.
  • the thick arrowed lines 184 represent a flow of electrical power from the PSU 176, through the storage device 170, and to the daisy chained device 174.
  • a portion of the electrical power 184 is directed to a first power control circuit 186 that includes a 5V power converter circuit 188 and controFpower logic circuitry (MOS) 190. This supplies electrical power for use by Port A 178.
  • Another portion of the electrical power 184 is directed to a second power control circuit 192 with a 5V power conversion circuit 194 and controFpower logic circuitry (MOS) 196 for use by Port B 180.
  • the power supplied to Port B is forwarded for use by the daisy chained device 174, which may be a companion storage device with similar power consumption requirements as the storage device 170.
  • the power 184 from the power jack 182 will be internally routed to other portions of the storage device 170 as well, such as generally illustrated in FIG. 2, but such details have been omitted for clarity.
  • the power delivery capability of the storage device 170 is insufficient to meet the power consumption needs of the host 172.
  • the storage device 172 may be only capable of supplying upwards of about 15 watt, W of power to Port A 178, while the minimum power consumption requirements of the host 172 may be more on the order of 60 W to 100 W.
  • a separate host PSU 198 is thus used to enable operation of the host 172.
  • the power supplied by PSU 198 can be used by the host 172 in a number of ways, including power to run the processors and other elements of the host during normal operation, power to recharge a rechargeable battery of the host, etc.
  • the host PSU 198 can take any number of forms, including a cable with a transformer to perform an AC-DC conversion from a wall receptacle.
  • FIG. 5 shows a data storage device 200 constructed and operated in accordance with various embodiments of the present disclosure to overcome these and other limitations of the existing art, including those associated with FIG. 4. It will be noted that the device 200 generally corresponds to the storage devices 100, 110 discussed above. For convenience, like reference numerals are used for similar components appearing in both FIGS. 4-5.
  • the storage device 200 is coupled to the host device 172 using Port A 178 via a suitable interconnection such as a Type-C serial cable.
  • the storage device 200 is further coupled to an external power supply unit (EXT PSU) 202 via Port B 180 using a second type-C serial cable.
  • EXT PSU external power supply unit
  • No external power connection to the storage device 200 is provided from the power jack 182.
  • An internal power flow is supplied to the storage device 200 through Port B 180 from the EXT PSU 202, as generally represented by thick arrowed lines 204. It will be noted that this power is forwarded to the host 172 via Port A 178. This eliminates the need for a separate host PSU 198 to provide electrical power to the host 172 as shown in FIG. 4. This allows only one type-C serial cable to be connected to the host.
  • the storage device 200 is configured with additional circuitry not present in FIG. 4, including a power delivery (PD) controller 206, a power logic circuit 208, and a power multiplexor (mux) 210.
  • a beefed up first power control circuit 212 is provided with an enhanced voltage converter 214 and MOS logic 216.
  • the voltage converter may include a buck-boost power converter with capabilities of outputting power levels at various voltages including, but not necessarily limited to, 5V, 9V, 15V and 20V.
  • the PD controller 206 may form a portion of the existing storage device controller (see e.g., element 114 in FIG. 2), or may be stand-alone hardwired or programmable processing circuit. If the PD controller is realized as one or more programmable processors, suitable program instructions (firmware) will be supplied in an associated memory to facilitate operation. Generally, the PD controller 206 operates to manage the distribution of power in and through the storage device 200. To this end, the PD controller 206 forms a portion of the power management circuit 168 of FIG. 3, and operates to detect the current power state of the storage device 210 and provide various control settings within the device, including inputs to the power management circuit 208 and the voltage converter 214.
  • the power controller 208 is in charge with regard to requesting, to the PD controller, new profile definitions due to the PSU connection on port B.
  • the PD controller informs the host of the new available profiles.
  • An automatic power mux switching arrangement can be used.
  • the mux 210 can automatically switch to direct power from the power jack 182.
  • the PSU device 176 will provide the power during the PD profile redefinition to a lower PD profile.
  • Power pass-through controller will request a new PD profile definition, the PD controller will inform the host, and the host will switch to the lower available PD profile.
  • FIG. 6 provides a sequence diagram 220 to illustrate various operations of the storage device 200 of FIG. 5 in accordance with some embodiments to establish the supplying of electrical power to the host 172.
  • block 222 depicts the connection of the host 172 to the storage device 200 using Port A 178
  • block 224 depicts the connection of the EXT PSU 202 to Port B 180. It is contemplated that these connections are TBT3 interconnections using suitable cabling with both data and power transfer capabilities.
  • the interconnection of the EXT PSU to Port B is detected by the PD controller 206 at block 226.
  • This can be carried out in a number of ways, including through the use of voltage sensors and/or decoding logic.
  • Communication is established between the PD controller 206 and a controller of the EXT PSU 202 in order to determine an available power profile from the PSU. These and other communications can be facilitated by the main storage controller of the storage device 200 as required.
  • the available power profile can be characterized in a number of suitable ways. In some embodiments, the available power may be expressed in terms of available power output levels that can be supplied by the PSU (e.g., 60 W, 80 W, 100 W), etc.
  • Block 228 shows the establishment of a power delivery contract between the PD controller and the PSU.
  • a power delivery contract represents an agreed upon set of parameters (terms) by which the power will be supplied via Port B (e.g., the power profile). This may include voltage levels, overall power levels, characteristics of the power, a minimum elapsed time duration over which the power will be provided, etc.
  • the PD controller may utilize circuitry of the storage device to validate the available power, such as by testing the applied power or otherwise characterizing it is sufficiently stable for use.
  • the flow passes to block 230 where the power mux 210 is configured to receive the external power from the PSU.
  • the host 172 is notified at block 232 of the new available power profiles at Port A.
  • the host via the host controller (see e.g., controller 134 in FIG. 2), establishes a power delivery contract with the storage device 200 for delivery of the electrical power via Port A, block 234.
  • the host may have previously been applying 5V of power voltage on the power bus aspects of the TBT3 cable (e.g., power transfer lines 148, FIG. 2), and now 20V of power will be supplied by the storage device to the host on these same lines during the duration of the contract.
  • power is delivered to the host via Port A at block 236 in accordance with the terms of the delivery contract. This delivered power may be used by the host in any suitable manner described above, including the charging of an on-board rechargeable battery of the host.
  • FIG. 7 shows a sequence diagram 240 illustrative of steps carried out to subsequently discontinue the provision of electrical power to the host from the storage device 240.
  • the disconnecting of power can be carried out as a result of a variety of causes, including an abrupt and unplanned user disconnection of the external PSU, as indicated by block 242.
  • Other disconnection scenarios are contemplated, including the expiration of a set time in which the PSU agreed to supply power to the storage device.
  • the power mux 210 Upon the loss of input power at Port B, the power mux 210 operates at block 244 to switch automatically to direct internal power through the storage device 200. This may include switching over to available power from an external source at power jack 182, or to switch over to electrical power from an internal power source (e.g., an internal battery, a super cap, etc.). In some cases, the removal of the external PSU may result in an agreed upon supplying of electrical power from the host back to the storage device via Port A.
  • an internal power source e.g., an internal battery, a super cap, etc.
  • the PD controller 206 changes the available power profile of the system to a new level based on the change of available power via the mux.
  • the host is notified at block 248 of the new maximum available power profile that the storage device can supply, block 250. Based on this information, the host asks for a new profile and adjusts the power settings including switching over to another available power source, reconfiguring the system to the new lower level power to the storage device via Port A, etc., as indicated by block 252. It is contemplated that during the entirety of the sequences of both FIGS. 6-7, sufficient local power will be available to ensure uninterrupted, continuous operation of both the storage device and the host.
  • FIG. 8 provides a simplified diagram of a power source circuit 260 in some embodiments.
  • the power source circuit can be implemented in the storage device 200, the host 172, or in both of these devices as required.
  • the circuit 260 includes a charging circuit 262 that receives input electrical power, and uses this input electrical power to recharge a rechargeable battery 264.
  • the battery 264 can be used to supply electrical power to at least parts of the computer system.
  • the power supplied to the host via Port A in FIG. 5 can be used to charge a host battery, after which the battery can be configured to begin supplying power for use by the host once the external PSU is disconnected.
  • FIG. 9 shows a functional block representation of an external power supply unit (PSU) such as the EXT PSU 202 in FIG. 5.
  • PSU external power supply unit
  • the PSU 280 includes an interface (I/F) circuit 282, a controller 284 and a power source 286.
  • the PSU may form a portion of a larger device such as a host, a peripheral device, an intelligent power supply, etc.
  • the interface circuit 282 is configured to communicate data commands and responses over the data lines that connect to Port B 180 of the storage device 200.
  • the PSU controller 284 may be a hardware or programmable processor based processor configured to communicate with the storage device 200 via Port B as described above to negotiate the supply of electrical power over the power transfer lines of the associated interface.
  • the power source 286 can take the form of a battery, a voltage converter, a charge storage device, or any other form that can provide electrical power to the storage device.
  • the PSU 280 may form a portion of a larger operational peripheral or host device, and may include a transformer that performs an AC-DC conversion of electrical power that is made available to the storage device as required.
  • FIGS. 10 and 11 have been provided to illustrate further details regarding suitable data storage device configurations in accordance with the present discussion.
  • FIG. 10 shows a functional block diagram for a solid state drive (SSD) data storage device 300 in accordance with some embodiments.
  • SSD solid state drive
  • a controller 302 provides top level control for the device 300 and may correspond to the controller 102 of FIG. 1.
  • An interface circuit 304 and local buffer memory 306 coordinate the transfer of user data between an external host device and a flash memory 308.
  • a read/write/erase circuit 310 performs the requisite encoding of input write data and directs the programming of the appropriate flash memory cells to write the encoded write data to the memory 308.
  • Power management (MGMT) circuit 312 represents elements used to implement the power flow of FIG. 5, and operates in accordance with the sequences of FIGS. 6-7.
  • FIG. 11 provides a functional block diagram for a hard disc drive (HDD) or hybrid solid state drive (HSSD) storage device 400 in some embodiments.
  • a controller circuit 402, interface circuit 404 and buffer memory 405 operate as in FIG. 10 to coordinate data transfers with a host device.
  • a flash memory 406 provides local non-volatile semiconductor memory for storage of data.
  • a read/write (R/W) channel 408 and preamp lifier/driver (preamp) 410 support transfers of data to a rotatable recording medium (disc) 412 using a data read/write transducer (head) 414. Head position is controlled using a voice coil motor (VCM) 416 and a closed loop servo control circuit 418. Data from the host may be stored to the flash 406 and/or the disc 412 as required.
  • VCM voice coil motor
  • the channel 408 encodes the data during a write operation, and recovers the data during a subsequent read operation.
  • a power management (MGMT) circuit 420 generally corresponds to the circuitry shown in FIG. 5, and operates in accordance with the sequence flows of FIGS. 6 and 7.
  • a dual port peripheral device provides the capability of evaluating, validating and presenting electrical power from an external source through a second port to a host via a first port.
  • a data storage device provides a particularly suitable environment for the implementation of various embodiments, substantially any form of peripheral device can be used.
  • Thunderbolt 3 (TBT3) interface is particularly suitable for use in implementing these power and data transfers using the USB 3.0 standard, such is merely

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

L'invention concerne un appareil et un procédé de distribution de puissance à un ordinateur hôte (112). Un premier câble série (145) établit une première liaison de données (146) et une première liaison de transfert de puissance (148) entre un premier port série d'un dispositif périphérique (110) et l'ordinateur hôte. Un second câble série établit une seconde liaison de données (146) et une seconde liaison de transfert de puissance (148) entre un second port du dispositif périphérique et une unité d'alimentation en puissance externe (PSU). Un circuit de dispositif de commande périphérique (114) détecte la puissance disponible provenant de la PSU externe à un niveau approprié pour une utilisation par le dispositif hôte, notifie l'ordinateur hôte de la puissance disponible à partir de la PSU externe, et interconnecte les premier et second ports série pour faire circuler la puissance disponible vers le dispositif hôte par l'intermédiaire des première et seconde liaisons de transfert de puissance. Le dispositif périphérique peut prendre la forme d'un lecteur à semi-conducteurs (SSD) (110) doté d'une mémoire non volatile (118), telle qu'une mémoire flash.
EP19790780.1A 2019-07-31 2019-07-31 Distribution de puissance à un hôte à partir d'un dispositif périphérique à deux ports Withdrawn EP4004681A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2019/000911 WO2021019271A1 (fr) 2019-07-31 2019-07-31 Distribution de puissance à un hôte à partir d'un dispositif périphérique à deux ports

Publications (1)

Publication Number Publication Date
EP4004681A1 true EP4004681A1 (fr) 2022-06-01

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EP19790780.1A Withdrawn EP4004681A1 (fr) 2019-07-31 2019-07-31 Distribution de puissance à un hôte à partir d'un dispositif périphérique à deux ports

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EP (1) EP4004681A1 (fr)
CN (1) CN114424143A (fr)
WO (1) WO2021019271A1 (fr)

Family Cites Families (9)

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US7447922B1 (en) * 2004-06-23 2008-11-04 Cypress Semiconductor Corp. Supplying power from peripheral to host via USB
GB2427514B (en) * 2005-06-21 2007-08-01 Peter Robertson Socket assembly with standby sockets
GB2453405B (en) * 2007-06-15 2012-08-08 Apple Inc Systems and methods for providing device-to-device handshaking through a power supply signal
US8504860B2 (en) * 2009-06-26 2013-08-06 Seagate Technology Llc Systems, methods and devices for configurable power control with storage devices
JP5236701B2 (ja) * 2010-08-11 2013-07-17 株式会社バッファロー サーバ装置、消費電力制御方法、ネットワークシステム
CN103931176B (zh) * 2011-09-14 2018-10-19 巴科股份有限公司 用于会议的电子工具和方法
US9274578B2 (en) * 2012-05-09 2016-03-01 Apple Inc. Enable power from an accessory to a host device based on whether the accessory is able to alter an electrical characteristic of the power path
US9594415B2 (en) * 2013-09-22 2017-03-14 Microsoft Technology Licensing, Llc Accessory device power management
TWI639922B (zh) * 2016-09-08 2018-11-01 鈺群科技股份有限公司 通用序列匯流排c型模組

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CN114424143A (zh) 2022-04-29

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