EP3981074A1 - Root monitoring on an fpga using satellite adcs - Google Patents

Root monitoring on an fpga using satellite adcs

Info

Publication number
EP3981074A1
EP3981074A1 EP20745456.2A EP20745456A EP3981074A1 EP 3981074 A1 EP3981074 A1 EP 3981074A1 EP 20745456 A EP20745456 A EP 20745456A EP 3981074 A1 EP3981074 A1 EP 3981074A1
Authority
EP
European Patent Office
Prior art keywords
reference voltage
satellite
monitor
satellite monitors
sensors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP20745456.2A
Other languages
German (de)
English (en)
French (fr)
Inventor
John K. Jennings
Brendan FARLEY
John G. O'dwyer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/506,064 external-priority patent/US11709275B2/en
Priority claimed from US16/535,713 external-priority patent/US10705144B1/en
Priority claimed from US16/535,726 external-priority patent/US10598729B1/en
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of EP3981074A1 publication Critical patent/EP3981074A1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters

Definitions

  • This disclosure relates generally to integrated circuits, and specifically to monitoring one or more operating conditions of an integrated circuit.
  • Programmable logic devices are devices that may be programmed by a user to implement a variety of user-specified circuit designs.
  • a PLD is a field programmable gate array (FPGA).
  • An FPGA may include an array of configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), input/output blocks (lOBs), digital signal processors (DSPs), a number of processing cores, and other subsystems (such as memory controllers, device management resources, and configuration circuitry) that may be selectively connected together by programmable interconnect structures.
  • CLBs configurable logic blocks
  • BRAM dedicated random access memory blocks
  • lOBs input/output blocks
  • DSPs digital signal processors
  • a user-specified circuit design may be implemented within a programmable device by loading configuration data representative of the user-specified circuit design into
  • configuration registers that collectively determine the functions and operations performed by the various blocks, interconnect structures, and subsystems of the programmable device.
  • Electrical components within programmable devices are typically operated within specified operating conditions.
  • electrical components may be designed to operate within a specified temperature range, and may be disabled or powered down if the operating temperature increases beyond a certain level.
  • supply voltages are typically maintained between a minimum voltage level and a maximum voltage level to provide a relatively constant operating voltage to other electrical components provided within the programmable device.
  • supply voltages are typically maintained between a minimum voltage level and a maximum voltage level to provide a relatively constant operating voltage to other electrical components provided within the programmable device.
  • the programmable device may include a plurality of configurable logic resources, a root monitor, a number of sensors distributed in various locations across the programmable device, a plurality of satellite monitors distributed in the various locations across the programmable device, and a network interconnect system coupled to the configurable logic resources, to the root monitor, and to each of the plurality of satellite monitors.
  • Each of the sensors may be configured to measure the operating conditions of an associated circuit at a corresponding one of the various locations, and may provide analog signals indicative of the measured operating conditions to a corresponding one of the satellite monitors.
  • the operating conditions may include at least one of a temperature or a voltage level of the associated circuit.
  • Each of the satellite monitors may include an analog-to-digital converter (ADC) having an input to receive the analog signals from one or more associated sensors, and having an output to provide the digital data to the network
  • ADC analog-to-digital converter
  • the ADC may convert the analog signals into digital data indicative of the operating conditions of one or more associated sensors, and may provide the digital data to the root monitor via the network interconnect system.
  • the root monitor may include circuity configured to generate a reference voltage, and may include a memory configured to store digital data received from the plurality of satellite monitors.
  • the root monitor may include a bandgap reference circuit that compensates the reference voltage for temperature variations.
  • the root monitor may include a controller configured to determine whether the measured operating conditions of the associated circuits are within a range. In some aspects, the controller may be further configured to generate an alarm based on the
  • the network interconnect system may be configured to distribute the reference voltage from the root monitor to each of the plurality of satellite monitors, and may be configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor.
  • the network interconnect system may include one or more analog channels configured to distribute the reference voltage from the root monitor to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route the digital data from the satellite monitors to the root monitor.
  • the digital data may be routed through the network interconnect system as individually addressable data packets. In other aspects, the digital data may be routed through the network interconnect system as non-packetized digital signals.
  • each of the satellite monitors may include a switch configured to selectively couple the reference voltage distributed by the
  • control signals may be generated by the root monitor, and may be distributed to
  • the root monitor may selectively assert the control signals based on a timing schedule that allows only one of the satellite monitors to access the distributed reference voltage from the network interconnect system at any given point in time.
  • An example system for monitoring a number of operating conditions of a programmable device may include a root monitor, a plurality of sensors distributed across the programmable device, a plurality of satellite monitors distributed across the programmable device, and a network interconnect system coupled to at least the root monitor and each of the plurality of satellite monitors.
  • the root monitor may include circuity configured to generate a reference voltage that can be used for performing analog-to-digital conversions.
  • the root monitor may include a bandgap reference circuit that compensates the reference voltage for temperature variations.
  • the root monitor may include a controller configured to determine whether the measured operating conditions of the associated circuits are within a range. In some aspects, the controller may be further configured to generate an alarm based on the
  • Each of the sensors may be configured to generate analog signals indicative of operating conditions of an associated circuit
  • each of the satellite monitors may be configured to convert the analog signals generated by one or more associated sensors into digital data that can be routed to the root monitor via the network interconnect system.
  • the network interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route the digital data from each of the plurality of satellite monitors to the root monitor.
  • the digital data may be routed through the network interconnect system as individually addressable data packets. In other aspects, the digital data may be routed through the network interconnect system as non- packetized digital signals.
  • Each of the satellite monitors may include an analog-to-digital converter (ADC) configured to convert the analog signals into the digital data.
  • ADC analog-to-digital converter
  • each of the satellite monitors may include a switch configured to selectively couple the reference voltage distributed by the interconnect system to the satellite monitor based on a control signal.
  • the control signals may be generated by the root monitor, and may be distributed to corresponding satellite monitors via the network interconnect system (or by other suitable signal interconnects).
  • the root monitor may selectively assert the control signals based on a timing schedule that allows only one of the satellite monitors to access the distributed reference voltage from the network interconnect system at any given point in time.
  • An example method disclosed herein may be used to monitor a number of operating conditions of a programmable device.
  • the method may include generating a reference voltage using a voltage generator associated with a root monitor provided within the programmable device, and distributing the reference voltage to each of a plurality of satellite monitors using one or more analog channels of a network interconnect system integrated within the programmable device.
  • distributing the reference voltage may include selectively coupling each of the plurality of satellite monitors to the network interconnect system based on a corresponding control signal.
  • the control signals may be generated by the root monitor and distributed to the plurality of satellite monitors by the network interconnect system.
  • the root monitor may selectively assert the control signals based on a timing schedule that allows only one of the satellite monitors to access the distributed reference voltage from the network interconnect system at any given point in time.
  • the method may also include generating, using each of a number of sensors, analog signals indicative of operating conditions of an associated circuit, and providing the analog signals to corresponding ones of the plurality of satellite monitors.
  • the analog signals may be converted into digital data using the plurality of satellite monitors, and the digital data may be selectively routed from the plurality of satellite monitors to the root monitor using one or more digital channels of the network interconnect system.
  • the digital data may be routed through the network interconnect system as individually addressable data packets. In other aspects, the digital data may be routed through the network interconnect system as non-packetized digital signals.
  • the method may also include determining whether the operating conditions of the associated circuits are within a range, and selectively generating one or more alarms based on the determination.
  • an alarm may be generated when the operating conditions of at least one of the associated circuits are not within the range, which may indicate that the at least one of the associated circuits is operating outside of certain conditions.
  • the programmable device may include programmable logic including a plurality of configurable logic resources, a root monitor, a plurality of sensors distributed in various locations across the programmable device, and a plurality of satellite monitors distributed in the various locations across the programmable device.
  • Each of the sensors may be configured to generate analog signals indicative of measured operating conditions of one or more associated circuits in a vicinity of a corresponding one of the various locations, and may provide the analog signals to an associated one of the satellite monitors via one or more local signal lines.
  • the operating conditions may include at least one of a temperature or a voltage level of the associated circuit.
  • the root monitor may include a bandgap voltage generator configured to generate a temperature-independent reference voltage, and may include a memory to store digital data received from the plurality of satellite monitors.
  • the root monitor may also include a controller configured to determine whether the measured operating conditions of the associated circuits are within a range. In some aspects, the controller may be further configured to generate an alarm based on the determination indicating that the measured operating conditions are not within the range.
  • Each of the satellite monitors may include a relatively small local voltage source configured to generate a local reference voltage, an analog-to-digital converter (ADC), a calibration circuit, and a correction circuit.
  • the ADC may include a reference terminal to receive the local reference voltage, and may be configured to convert the analog signals generated by the one or more associated sensors into digital codes indicative of the measured operating conditions.
  • the calibration circuit may be configured to generate a correction factor indicative of errors in the digital codes, and the correction circuit may be configured to correct the digital codes generated by the ADC based on the correction factor.
  • each of the satellite monitors may include a switch including a first input terminal coupled to receive the temperature-independent reference voltage, a second input terminal coupled to receive the analog signals generated by the one or more associated sensors, a control terminal coupled to receive a control signal, and an output terminal coupled to an input terminal of the ADC within the satellite monitor.
  • the switch may provide the temperature-independent reference voltage as an input signal to the ADC, and the ADC may sample the temperature-independent reference voltage to generate a reference code.
  • the calibration circuit may generate the correction factor based on a difference between the reference code generated by the ADC and a predetermined digital code indicative of the temperature-independent reference.
  • the switch may provide the analog signals from the sensors as input signals to the ADC, the ADC may sample the analog signals from the one or more associated sensors to generate the digital codes, and the correction circuit may use the correction factor to correct the digital codes.
  • the root monitor may generate the control signals based at least in part on a timing schedule for calibrating the plurality of satellite monitors.
  • the timing schedule may be configured to sequentially enable calibration of each of the plurality of satellite monitors by allowing only one of the satellite monitors to access the temperature-independent reference voltage at a time.
  • the programmable device may include a network- on-chip (NoC) interconnect system coupled to the configurable logic resources, to the root monitor, and to each of the plurality of satellite monitors.
  • the NoC interconnect system may be configured to route control signals from the root monitor to each of the plurality of satellite monitors, and may be configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor.
  • the programmable device may include one or more analog channels configured to distribute the temperature- independent reference voltage from the root monitor to each of the plurality of satellite monitors.
  • An example method disclosed herein may be used to monitor operating conditions of a plurality of circuits distributed in various locations across a programmable device.
  • the method may include generating an analog signal indicative of the operating conditions of each of the plurality of circuits using a corresponding one of a plurality of sensors distributed in the various locations across the programmable device; providing each of the analog signals to a corresponding one of a plurality of satellite monitors distributed in the various locations across the programmable device; generating, in each of the plurality of satellite monitors, a local reference voltage using a local voltage source; converting, in each of the plurality of satellite monitors, a corresponding one of the plurality of analog signals into a digital code using an analog-to-digital converter (ADC) based on the local reference voltage; distributing a temperature-independent reference voltage from a root monitor to each of the plurality of satellite monitors; correcting the digital code generated by the ADC within each of the plurality of satellite monitors based at least in part on the distributed temperature-in
  • each of the plurality of satellite monitors sequentially enabling each of the plurality of satellite monitors to access the temperature-independent reference voltage based on a corresponding plurality of control signals generated by the root monitor.
  • the corrected digital codes may be selectively routed from the plurality of satellite monitors to the root monitor using a network-on- chip (NoC) interconnect system spanning the programmable logic, and the temperature-independent reference voltage may be distributed from the root monitor to the plurality of satellite monitors using one or more analog channels spanning the programmable logic.
  • correcting the digital codes may include providing the temperature-independent reference voltage as an input signal to the ADC; converting the temperature-independent reference voltage into a reference code using the ADC; generating a correction factor based on differences between the reference code and a predetermined digital code indicative of the temperature-independent reference voltage; and adjusting the digital code based on the correction factor.
  • the programmable device may include programmable logic including a plurality of configurable logic resources, a root monitor, a plurality of sensors distributed in various locations across the programmable device, and a plurality of satellite monitors distributed in the various locations across the programmable device.
  • Each of the sensors may be configured to generate analog signals indicative of measured operating conditions of one or more associated circuits in a vicinity of a corresponding one of the various locations, and may provide the analog signals to an associated one of the satellite monitors via one or more local signal lines.
  • the operating conditions may include at least one of a temperature or a voltage level of the associated circuit.
  • the root monitor may include a bandgap voltage generator configured to generate a temperature-independent reference voltage, and may include a memory to store digital data received from the plurality of satellite monitors.
  • the root monitor may also include a controller configured to determine whether the measured operating conditions of the associated circuits are within a range. In some aspects, the controller may be further configured to generate an alarm based on the determination indicating that the measured operating conditions are not within the range.
  • Each of the satellite monitors may include a voltage store configured to store a local reference voltage based on the temperature-independent reference voltage generated by the bandgap voltage generator, an analog-to-digital converter (ADC), a calibration circuit, and a correction circuit.
  • the ADC may include a reference terminal to receive the local reference voltage, and may be configured to convert the analog signals generated by the one or more associated sensors into digital codes indicative of the measured operating conditions.
  • the calibration circuit may be configured to generate a correction factor indicative of errors in the digital codes, and the correction circuit may be configured to correct the digital codes generated by the ADC based on the correction factor.
  • each of the satellite monitors may include a first switch and a second switch.
  • the first switch may include a first input terminal coupled to receive the temperature-independent reference voltage, a second input terminal coupled to receive the analog signals generated by the one or more associated sensors, a control terminal coupled to receive a control signal, and an output terminal coupled to an input terminal of the ADC within the satellite monitor.
  • the second switch may include an input terminal coupled to receive the
  • the first switch may provide the temperature- independent reference voltage as an input signal to the ADC
  • the second switch may isolate the voltage store from the temperature-independent reference voltage
  • the ADC may sample the temperature-independent reference voltage to generate a reference code.
  • the calibration circuit may generate the correction factor based on a difference between the reference code generated by the ADC and a predetermined digital code indicative of the temperature-independent reference.
  • the first switch may provide the analog signals from the sensors as input signals to the ADC
  • the second switch may provide the temperature-independent reference voltage to the voltage store
  • the ADC may sample the analog signals from the one or more associated sensors to generate the digital codes
  • the correction circuit may use the correction factor to correct the digital codes.
  • the root monitor may generate the control signals based at least in part on a timing schedule for calibrating the plurality of satellite monitors.
  • the timing schedule may be configured to sequentially enable calibration of each of the plurality of satellite monitors by allowing only one of the satellite monitors to access the temperature-independent reference voltage at a time.
  • the programmable device may include a network- on-chip (NoC) interconnect system coupled to the configurable logic resources, to the root monitor, and to each of the plurality of satellite monitors.
  • the NoC interconnect system may be configured to route control signals from the root monitor to each of the plurality of satellite monitors, and may be configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor.
  • the programmable device may include one or more analog channels configured to distribute the temperature- independent reference voltage from the root monitor to each of the plurality of satellite monitors.
  • An example method disclosed herein may be used to monitor operating conditions of a plurality of circuits distributed in various locations across a programmable device.
  • the method may include generating an analog signal indicative of the operating conditions of each of the plurality of circuits using a corresponding one of a plurality of sensors distributed in the various locations across the programmable device; providing each of the analog signals to a corresponding one of a plurality of satellite monitors distributed in the various locations across the programmable device; storing, in each of the plurality of satellite monitors, a local reference voltage based on the temperature- independent reference voltage; converting, in each of the plurality of satellite monitors, a corresponding one of the plurality of analog signals into a digital code using an analog-to-digital converter (ADC) based on the local reference voltage; distributing a temperature-independent reference voltage from a root monitor to each of the plurality of satellite monitors; correcting the digital code generated by the ADC within each of the plurality of satellite monitors based at least in part on the distributed
  • the voltage store may be a capacitor, and the local reference voltage may be relatively imprecise compared to the temperature- independent reference voltage.
  • distributing the temperature-independent reference voltage may include sequentially enabling each of the plurality of satellite monitors to access the temperature-independent reference voltage based on a corresponding plurality of control signals generated by the root monitor.
  • the corrected digital codes may be selectively routed from the plurality of satellite monitors to the root monitor using a network-on-chip (NoC) interconnect system spanning the programmable logic, and the temperature-independent reference voltage may be distributed from the root monitor to the plurality of satellite monitors using one or more analog channels spanning the programmable logic.
  • correcting the digital codes may include providing the temperature-independent reference voltage as an input signal to the ADC; converting the temperature-independent reference voltage into a reference code using the ADC; generating a correction factor based on differences between the reference code and a predetermined digital code indicative of the temperature- independent reference voltage; and adjusting the digital code based on the correction factor.
  • FIG. 1 is a block diagram of an example programmable device within which various aspects of the present disclosure may be implemented.
  • FIG. 2 shows a functional block diagram of a portion of the programmable device of FIG. 1 , in accordance with some implementations.
  • FIG. 3 shows a block diagram of an example programmable fabric, in accordance with some implementations.
  • FIG. 4 shows a functional block diagram of a monitoring system, in accordance with some implementations.
  • FIG. 5 shows a block diagram of an example root monitor, in accordance with some implementations.
  • FIG. 6 shows a block diagram of an example satellite monitor, in accordance with some implementations.
  • FIG. 7 is an illustrative flow chart depicting an example operation for monitoring a number of operating conditions of a programmable device, in accordance with some implementations.
  • FIG. 8 is a block diagram of an example programmable device within which various aspects of the present disclosure may be implemented.
  • FIG. 9 shows a functional block diagram of a portion of the programmable device of FIG. 8, in accordance with some implementations.
  • FIG. 10 shows a block diagram of an example programmable fabric, in accordance with some implementations.
  • FIG. 1 1 shows a functional block diagram of a monitoring system, in accordance with some implementations.
  • FIG. 12 shows a block diagram of an example root monitor, in accordance with some implementations.
  • FIG. 13 shows a block diagram of an example satellite monitor, in accordance with some implementations.
  • FIG. 14 is an illustrative flow chart depicting an example operation for monitoring a number of operating conditions of a programmable device, in accordance with some implementations.
  • FIG. 15 is an illustrative flow chart depicting an example operation for correcting digital codes, in accordance with some implementations.
  • FIG. 16 shows a block diagram of an example satellite monitor, in accordance with some implementations.
  • Implementations of the subject matter described in this disclosure may be used to monitor a number of operating conditions of a programmable device.
  • the operating conditions may be any suitable measure of the device’s operating characteristics or parameters including, for example, a temperature of a circuit or component provided within the programmable device, a temperature of a circuit or device external to the programmable device, a voltage level of a supply voltage, and the like.
  • a monitoring system may be implemented in a programmable device that includes programmable logic, dedicated circuitry such as processors and DSPs, and a network interconnect system that can route information between the programmable logic, the dedicated circuitry, and other circuits or components of the programmable device using individually addressable data packets.
  • the monitoring system may include a root monitor, a number of sensors distributed in various locations across the programmable device, and a plurality of satellite monitors distributed in the various locations across the programmable device.
  • Each of the sensors may generate analog signals indicative of one or more operating conditions of an associated circuit, and may provide the analog signals to a corresponding one of the satellite monitors.
  • Each of the satellite monitors may include an ADC to convert the analog signals into digital data, and the network interconnect system may route the digital data from each of the satellite monitors to the root monitor.
  • each of the satellite monitors may be positioned in a vicinity of a corresponding sensor, for example, so that analog signals generated by the corresponding sensor are not routed across the
  • programmable device to the root monitor for conversion to digital data, but instead are routed a relatively short distance to the corresponding satellite monitor, via local signal wires, for conversion to digital data.
  • digital data generated by the satellite monitors may be routed to the root monitor using other suitable routing resources provided within the device including (but not limited to) clock distribution networks, programmable interconnect fabric, and/or routing resources provided within each of the programmable logic tiles in the device.
  • the root monitor may receive the digital data generated by each of the satellite monitors via the network interconnect system, and may analyze the digital data to determine whether one or more of the circuits being monitored are not operating within a specified operating range.
  • the root monitor may generate a trimmed and temperature-compensated reference voltage, and the network interconnect system may distribute the trimmed and temperature- compensated reference voltage to each of the satellite monitors located throughout the device.
  • Conventional systems for monitoring operating conditions of various circuits distributed across a programmable device typically include a central system monitor and a plurality of sensors positioned near the circuits to be monitored.
  • Each sensor generates analog signals indicative of the operating conditions of an associated circuit, and the analog signals are routed from each of the sensors to the system monitor for conversion to digital data.
  • the sensors are typically distributed in various locations throughout the device, and therefore the analog signals generated by at least some of the sensors may be routed across large portions of the device to reach the system monitor. Because analog signals indicative of operating conditions may be particularly susceptible to noise and interference, some programmable devices may use dedicated metal-layer routing resources with shielding properties to route these analog signals from the various sensors to the system monitor for conversion to digital data.
  • the shielding properties of such dedicated metal-layer routing resources may reduce signal degradation and data loss, the dedicated metal-layer routing resources are expensive and consume significant amounts of the device’s metal layers.
  • the signal routing resources embedded within each of the repeatable tiles is typically based on a worst-case routing scenario (such as for tiles to be placed in locations in which device density is the greatest). As a result, many of the repeatable tiles are over equipped with signal routing resources, which may result in unused routing resources and/or may limit scalability of the programmable device.
  • the monitoring systems disclosed herein may convert analog signals generated by the sensors into digital data using local satellite monitors, and then route digital data from the various locations throughout the device to the root monitor.
  • the analog signals are not routed across large portions of the device and then converted to digital data, but instead are transmitted relatively short distances to the nearest satellite monitor for conversion to digital data, which is then routed to the root monitor using the network interconnect system.
  • digital data generated by the satellite monitors may be routed to the root monitor as individually addressable data packets. In other aspects, digital data generated by the satellite monitors may be routed to the root monitor as non-packetized data.
  • performing the analog-to-digital conversions locally e.g., in the vicinities of the sensors
  • routing the resulting digital data from the satellite monitors to the root monitor may allow more sensor data to be collected and analyzed by the root monitor (as compared to prior techniques that route analog signals from various sensors located throughout the device to an ADC provided within a system monitor), for example, because the ADCs distributed throughout the programmable device may perform analog-to-digital conversions in parallel (e.g., at the same time).
  • buses or single signal lines may be shown as buses or as single signal lines.
  • Each of the buses may alternatively be a single signal line, and each of the single signal lines may alternatively be buses, and a single line or bus might represent any one or more of a myriad of physical or logical mechanisms for communication between components.
  • FIG. 1 shows a block diagram of an example programmable device 100 within which various aspects of the present disclosure may be implemented.
  • the device 100 may include a number of subsystems such as, for example,
  • the device 100 may include other subsystems or components not shown in FIG. 1 . Further, although not shown for simplicity, the device 100 may be coupled to a number of peripheral components (such as a high-performance memory device) and/or other devices or chips (such as another programmable device).
  • PMR processing and management resources
  • CCM CCIX and PCIe Module
  • transceiver blocks 150 input/output blocks 160
  • memory controllers 170 configuration logic 180
  • a root monitor 190 a plurality of satellite monitors 192(1 )- 192(19)
  • S number of sensors
  • the device 100 may include other subsystems or components not shown in FIG. 1 . Further, although not shown for simplicity, the device 100 may be coupled to a number of peripheral components (such as a high-performance memory device) and/or other devices or chips (such as another programmable device).
  • the PL 1 10 includes programmable circuitry that may be configured or programmed to perform a multitude of different user-defined functions or operations.
  • the PL 1 10 may include a plurality of programmable circuit blocks implemented as repeatable tiles arranged in columns in the programmable device 100, for example, as depicted in FIG. 1 .
  • the programmable circuit blocks which may also be referred to as programmable fabric sub-regions (FSRs), may each include programmable interconnect circuitry and programmable logic circuitry.
  • the programmable circuit blocks may include (but are not limited to) configurable logic blocks (CLBs), random access memory blocks (BRAM), digital signal processing blocks (DSPs), clock managers, delay lock loops (DLLs), and/or other logic or circuits that can be programmed or configured to implement a user-specified circuit design.
  • CLBs configurable logic blocks
  • BRAM random access memory blocks
  • DSPs digital signal processing blocks
  • DLLs delay lock loops
  • other logic or circuits that can be programmed or configured to implement a user-specified circuit design.
  • the programmable interconnect circuitry within each of the programmable circuit blocks or tiles may include a plurality of interconnect wires of varying lengths interconnected by programmable interconnect points (PIPs).
  • the interconnect wires may be configured to provide connectivity between components within a particular programmable tile, between components within different programmable tiles, and between components of a programmable tile and other subsystems or devices.
  • the programmable interconnect circuitry and the programmable circuit blocks may be programmed or configured by loading configuration data into configuration registers that define how the programmable elements are configured and operate to implement a corresponding user-specified circuit design.
  • the programmable interconnect circuitry within each of a number of the programmable circuit blocks may form part of a programmable interconnect fabric (not shown for simplicity) that provides block-level and/or device-level signal routing resources for the device 100.
  • the network interconnect system 120 which may be fabricated as part of the device 100, may include any number of horizontal segments and vertical segments (and/or diagonal segments) connected together to implement a high speed, high-bandwidth programmable signal routing network that can selectively interconnect various device resources (such as the PL 1 10, the PMR 130, the CPM 140, the transceiver blocks 150, the I/O blocks 160, the memory controllers 170, the configuration logic 180, the root monitor 190, and the satellite monitors 192(1 )- 192(19)) with each other and with other components not shown for simplicity.
  • the network interconnect system 120 is shown to include two horizontal segments and four vertical segments.
  • a first horizontal segment extending across the width of the device 100 is positioned along a bottom boundary of the device 100, and a second horizontal segment extending across the width of the device 100 is positioned along the top boundary of the device 100.
  • the four vertical segments extend across the height of the device 100 and are connected to the first and second horizontal segments of the network interconnect system 120.
  • the horizontal segments may allow the network interconnect system 120 to exchange signals and data with the I/O blocks 160 and memory controllers 170 without any intervening circuits or interfaces
  • the vertical segments may allow the network interconnect system 120 to exchange signals and data with the transceiver blocks 150, the processing and management resources (PMR) 130, and the CPM 140 without any intervening circuits or interfaces.
  • PMR processing and management resources
  • the network interconnect system 120 may include other numbers of horizontal and vertical segments, which in turn may occupy other positions of the device 100.
  • the particular layout, shape, size, orientation, and other physical characteristics of the example network interconnect system 120 depicted in FIG. 1 are merely illustrative of the various implementations disclosed herein.
  • the network interconnect system 120 may be configured to transmit information between various device resources as data packets that can be individually addressed and routed from a source location to a destination location.
  • the data packets transmitted on the network interconnect system 120 may be dynamically addressable.
  • the network interconnect system 120 may employ a suitable data packet protocol (such as token ring protocol) and/or use memory-mapped addresses to route data packets from any number of source locations to any number of destination locations.
  • the data packets may include header information (such as source addresses, destination addresses, and protocol information) that can be used by the network interconnect system 120 to route the data packets to their indicated destinations.
  • the data packets may include Quality-of-Service (QoS) information that allows the transmission of data packets through the network interconnect system 120 to be prioritized, for example, based on assigned priorities, traffic types, traffic flows, and/or other criteria.
  • QoS Quality-of-Service
  • the network interconnect system 120 may include priority logic that can determine priority levels or traffic classes of received data packets, and use the determined priority levels or traffic classes when queuing the data packets for transmission.
  • the network interconnect system 120 may provide connectivity between the various device resources, irrespective of a particular user- specified circuit design, thereby significantly increasing the signal routing capabilities of the device 100 (as compared to conventional programmable devices).
  • the network interconnect system 120 may concurrently route each of a plurality of data packets from any source address to any destination address on the device 100, thereby providing system-level connectivity for the device 100.
  • the network interconnect system 120 may also include a scheduler and arbitration logic.
  • the scheduler may be used to schedule the transmission of data packets from a source address to a destination address using one or more physical and/or virtual channels of the network interconnect system 120.
  • the arbitration logic may be used to arbitrate access to the network interconnect system 120, for example, to minimize collisions and other contention-related latencies.
  • the columnal portions of the network interconnect system 120 may provide signal connections between adjacent super logic regions (SLRs), for example, to allow configuration data to be routed between master and slave SLRs.
  • SLRs super logic regions
  • the network interconnect system 120 may be programmed by loading configuration data into corresponding configuration registers that define how various switches, interfaces, and routers within or associated with the network interconnect system 120 are configured to implement a particular user-specified circuit design.
  • the network interconnect system 120 may include a plurality of nodes, ports, or other interfaces (not shown for simplicity) that provide selective connectivity between the network interconnect system 120 and the various resources, subsystems, circuits, and other components of the device 100.
  • the network interconnect system 120 may allow multiple subsystems of the device 100 to share access to on-chip memory (OCM) resources, processing resources, I/O resources, and/or the transceiver blocks 150.
  • OCM on-chip memory
  • the nodes, ports, or other interfaces of the network interconnect system 120 may be programmed to implement a particular connectivity profile by loading
  • the network interconnect system 120 may alleviate signal routing burdens on local interconnect resources, thereby increasing device performance and allowing for greater configuration flexibility than other programmable devices.
  • the network interconnect system 120 may increase the processing power and data throughput of the device 100 (as compared to other programmable devices).
  • the processing and management resources (PMR) 130 may provide dedicated data processing capabilities and platform management resources for the device 100.
  • the PMR 130 may include a processing system (PS) and a platform management controller (PMC), as described in more detail with respect to FIG. 2.
  • PS processing system
  • PMC platform management controller
  • the PS may include a number of processor cores, cache memory, memory controllers, and unidirectional and/or bidirectional interfaces configurable to couple directly to the I/O pins of the device 100.
  • each processor core may include central processing units (CPU) or scalar processors that can be used for sequential data processing.
  • the PMC may be used for booting and configuring the device 100 based on configuration data (such as a configuration bitstream) provided from external memory.
  • the PMC may also be used to configure the PL 1 10 and to control various encryption, authentication, root monitoring, and debug capabilities of the device 100.
  • the CCIX and PCIe module (CPM) 140 may include a number of interfaces that provide connectivity between the device 100 and a number of peripheral components (such as external devices or chips).
  • the CPM 140 may include a number of peripheral interconnect express (PCIe) interfaces and cache coherent interconnect for accelerators (CCIX) interfaces that provide connectivity to other devices or chips via the transceiver blocks 150.
  • PCIe peripheral interconnect express
  • CCIX cache coherent interconnect for accelerators
  • the PCIe and CCIX interfaces may be implemented as part of the transceiver blocks 150.
  • the transceiver blocks 150 may provide signal connections with one or more other devices or chips (not shown for simplicity) connected to the device 100.
  • the transceiver blocks 150 may include a number of different serial transceivers such as, for example, gigabit serial transceivers (GTs).
  • GTs gigabit serial transceivers
  • the transceiver blocks 150 may be implemented as a number of repeatable tiles positioned in various locations along the right and left sides of the device 100, as depicted in FIG. 1 . In other implementations, the transceiver blocks 150 may be positioned in other suitable locations of the device 100. In one or more
  • each of the transceiver blocks 150 may be coupled to one or more associated voltage supplies (not shown for simplicity).
  • each bank of transceiver circuits within a given transceiver block 150 may include or may be coupled to a corresponding voltage supply, for example, so that each bank of transceiver circuits may be powered using a separate voltage supply.
  • the I/O blocks 160 are coupled to the device’s I/O pins (not shown for simplicity), and may provide I/O capabilities for the device 100.
  • the I/O blocks 160 may receive data from one or more other devices, and may drive the received data to a number of destinations in the device 100.
  • the I/O blocks 160 may also receive data from a number of sources in the device 100, and may drive the received data to one or more other devices via the device’s I/O pins.
  • the I/O blocks 160 may be implemented as repeatable tiles.
  • the device 100 may include any suitable number of I/O blocks 160, and therefore the example implementation depicted in FIG. 1 is merely illustrative.
  • the I/O blocks 160 may include any number of suitable I/O circuits or devices.
  • the I/O blocks 160 may include extremely high- performance I/O (XPIO) circuits, high-density I/O (HDIO) circuits, and multiplexed I/O (MIO) circuits.
  • the XPIO circuits may be optimized for high-performance communications such as providing a high-speed, low latency interface to the memory controllers 170.
  • the XPIO circuits may include dedicated memory resources that can be accessed by other subsystems of the device 100 without using the memory controllers 170.
  • the HDIO circuits may provide a cost-effective solution that supports lower speed and higher voltage I/O capabilities (as compared with the XPIO circuits).
  • the MIO circuits may provide general-purpose I/O resources that can be accessed by various subsystems such as, for example, the PL 1 10, the PMR 130, and the CPM 140.
  • the memory controllers 170 may be used to control access to various memory resources provided within and/or external to the device 100. In some implementations, the memory controllers 170 may be used to access dedicated memory residing in one or more of the I/O blocks 160.
  • the memory controllers 170 may include double data rate v4 (DDR4) memory controllers, high bandwidth memory (HBM) controllers, and/or other suitable memory controllers. In one or more implementations, some or all of the memory controllers 170 may include a scheduler having transaction reordering capabilities that may improve memory access efficiency. In addition, or in the alternative, the repeatable tiles that implement the memory controllers 170 may be different from one another. For example, a first number of the memory controllers 170 may implement DDR4 memory controllers, a second number of the memory controllers 170 may implement LPDDR4 memory controllers, and a third number of the memory controllers 170 may implement HBM controllers.
  • the device 100 may include any number of I/O blocks 160 and memory controllers 170, and therefore the numbers and positions of the I/O blocks 160 and memory controllers 170 depicted in FIG. 1 are merely illustrative.
  • a first row of I/O blocks 160 and memory controllers 170 may be implemented as repeatable tiles positioned along the bottom edge of the device 100, and a second row of I/O blocks 160 and memory controllers 170 may be implemented as repeatable tiles positioned along the top edge of the device 100.
  • the I/O blocks 160 and memory controllers 170 may be alternately positioned or distributed relative to each other, for example, as depicted in the example of FIG. 1. In other implementations, a pair of I/O blocks 160 and memory controllers 170 may be implemented within the same repeatable tile.
  • the first row of I/O blocks 160 and memory controllers 170 positioned along the bottom of the device 100 may be coupled to the first horizontal segment of the network interconnect system 120
  • the second row of I/O blocks 160 and memory controllers 170 positioned along the top of the device 100 may be coupled to the second horizontal segment of the network interconnect system 120.
  • the network interconnect system 120 may provide connectivity between the programmable resources of the device 100 and its I/O pins (not shown for simplicity).
  • the device 100 may include one or more columns of connectivity fabric (not shown for simplicity) extending vertically across the height of the device 100 and positioned in a vicinity of the transceiver blocks 150.
  • the connectivity fabric may include a number of hard-wired circuits including (but not limited to) USB controllers, Ethernet MACs, multi-rate (MR) Ethernet MACs (MRMACs), PCIe controllers, CCIX controllers, and/or other components to provide connectivity between the transceiver blocks 150 and the PL 1 10.
  • the configuration logic 180 may be used to load configuration data (such as a configuration bitstream) from an external memory and route portions (such as frames, words, bytes, and/or bits) of the configuration data to the appropriate configuration registers that define how the various programmable resources of the device 100 are configured.
  • the configuration logic 180 may also be used to partially re-configure the device 100 and/or to internally reconfigure one or more portions of the device 100.
  • the configuration logic 180 may include configuration registers, boundary-scan test circuitry (such as TAP controller circuitry), encryption circuitry to encrypt bitstreams of configuration data read out of the device 100, and decryption circuitry to decrypt bitstreams of configuration data loaded into the device 100.
  • the device 100 may include an interface between the programmable fabric and each of the rows of I/O blocks 160 and memory controllers 170 positioned on the boundary of the device 100.
  • This interface which may be referred to herein as a Boundary Logic Interface (BLI)
  • BLI Boundary Logic Interface
  • HBM large and complex external devices
  • CLB blocks
  • the BLI may be arranged in rows positioned at the top and bottom boundaries or edges of the programmable fabric. In this manner, the BLI may be used to route signals between columnar logic structures (such as a CLB column or a DSP column) and rows of I/O resources (such as the I/O blocks 160).
  • programmable device 100 may include a monitoring system that can monitor one or more operating conditions of a plurality of selected circuits provided throughout the programmable device 100, for example, to ensure that the selected circuits operate within specified operational parameters.
  • the monitoring system disclosed herein may measure any suitable operating condition of the selected circuits including, for example, temperature, voltage levels, and current levels.
  • selected circuits may refer to any circuit, component, supply voltage, structure, or device that can be selected for monitoring one or more operating conditions to ensure proper operation of the device 100.
  • the monitoring system may generate an alarm (or multiple alarms) when the measured operating conditions of one or more of the selected circuits do not fall within a specified range of operating conditions.
  • the alarms may be used to power-down a number of circuits or components of the device 100. In other aspects, the alarms may be used to power-down the entire device 100.
  • the monitoring system may include (or may be formed by) the root monitor 190, the satellite monitors 192(1 )— 192(19), the sensors (S), and at least a portion of the network interconnect system 120.
  • the root monitor 190 is coupled to the network interconnect system 120, and may include circuity configured to generate a reference voltage.
  • the reference voltage generated by the root monitor 190 may be a trimmed and temperature-compensated voltage suitable for analog-to-digital conversions.
  • the root monitor 190 may be positioned within the processor system of the device 100, for example, as depicted in FIG. 1 .
  • the root monitor 190 may be positioned in other suitable locations in the device 100.
  • the reference voltage may be distributed to each of the satellite monitors 192(1 )— 192(19) via the network interconnect system 120, thereby eliminating the need to place multiple voltage generators at various locations across the device 100 to provide the reference voltage to each of the satellite monitors 192(1 )- 192(19).
  • the network interconnect system 120 may include one or more analog channels to distribute the reference voltage from the root monitor 190 to each of the satellite monitors 192(1 )— 192(19), and may include one or more digital channels to selectively route digital data from the satellite monitors 192(1 )— 192(19) to the root monitor 190.
  • the sensors (S) may be any suitable sensing circuit or device that can generate electrical signals indicative of one or more operating conditions of at least one of the selected circuits, and may include (but are not limited to) temperature sensors, voltage sensors, and/or current sensors. In some implementations, each sensor (S) may measure the operating conditions of one or more selected circuits, and may provide analog signals indicative of the measured operating conditions to a corresponding one of the satellite monitors 192(1 )— 192(19).
  • the satellite monitors 192(1 )— 192(19) may be any suitable circuit or device that can convert analog signals generated by the sensors (S) into digital data indicative of the measured operating conditions of the selected circuits.
  • each of the satellite monitors 192(1 )— 192(19) may include at least an analog-to-digital converter (ADC) and a memory.
  • the ADC which may be any suitable circuit that can convert analog signals into digital data, may include one or more inputs to receive analog signals generated by a number of associated sensors (S), one or more outputs to provide digital data indicative of the operating conditions measured by the associated sensors (S), and one or more reference terminals to receive a local reference voltage.
  • the local reference voltage may be based at least in part on the reference voltage generated by the root monitor and distributed to the satellite monitors 192(1 )— 192(19) by the network interconnect system 120.
  • the memory may store digital data generated by the ADC, and may provide the digital data to the network interconnect system 120 for routing to the root monitor.
  • the sensors (S) and the satellite monitors 192(1 )— 192(19) may be distributed throughout the programmable device 100 and positioned in various locations near the selected circuits, for example, so that analog signals indicative of operating conditions of the selected circuits may be converted to digital signals at the various distributed locations (rather than transmitted to a central hub and then converted into digital data).
  • each of the sensors (S) may be positioned in a vicinity of a corresponding selected circuit, for example, so that the sensor (S) and the corresponding selected circuit may be coupled together using local signal lines.
  • each of the satellite monitors 192(1 )— 192(19) may be positioned in a vicinity of one or more associated sensors (S), for example, so that the satellite monitor 192 and the one or more associated sensors (S) may be coupled together using local signal lines.
  • the term“vicinity” as used herein may refer to a distance over which analog signals indicative of operating conditions can be transmitted via relatively short local signal wires with minimal signal degradation.
  • a first group of sensors (S) located within the transceiver blocks 150 may be positioned in the respective vicinities of voltage supplies (not shown for simplicity) associated with the transceiver blocks 150, and a first group of satellite monitors 192(1 )— 192(6) may be positioned in the vicinities of the first group of sensors (S), for example, so that each of the first group of sensors (S) may be coupled to a corresponding supply voltage and to a corresponding satellite monitor 190 by relatively short local signal wires.
  • each of the first group of sensors (S) may be configured to generate analog signals indicative of one or more operating conditions of a corresponding voltage supply
  • each of the first group of satellite monitors 192(1 )— 192(6) may be configured to convert analog signals generated by the associated sensor (S) into digital data that can be transmitted to the root monitor 190 via the network interconnect system 120.
  • a second group of sensors (S) located within the PL 1 10 may be positioned in the vicinities of a number of corresponding selected circuits (not shown for simplicity) within or associated with the PL 1 10, and a second group of satellite monitors 192(7)— 192(19) may be positioned in the vicinities of the second group of sensors (S), for example, so that each of the second group of sensors (S) may be coupled to a corresponding selected circuit and to a corresponding one of the second group of satellite monitors 192(7)— 192(19) by relatively short local signal wires.
  • each of the second group of sensors (S) may be configured to generate analog signals indicative of one or more operating conditions of a corresponding selected circuit
  • each of the second group of satellite monitors 192(7)— 192(19) may be configured to convert analog signals generated by the associated sensor (S) into digital data that can be transmitted to the root monitor 190 via the network interconnect system 120.
  • Each of the satellite monitors 192(1 )— 192(19) may be coupled to any suitable number of sensors (S) by local signal lines.
  • satellite monitor 192(1 ) may be coupled to a single sensor (S) positioned within the transceiver blocks 150, and may generate digital signals indicative of one or more operating conditions of a corresponding voltage supply associated with the transceiver blocks 150.
  • satellite monitor 192(16) may be coupled to two sensors (S) positioned within the PL 1 10, and may generate digital signals indicative of one or more operating conditions of selected circuits
  • satellite monitor 192(17) may be coupled to four sensors (S) positioned within the PL 1 10, and may generate digital signals indicative of one or more operating conditions of selected circuits associated with the four sensors (S) positioned within the PL 1 10.
  • the programmable device 100 may include other numbers of satellite monitors 192 positioned in other suitable locations of the programmable device 100.
  • the satellite monitors 192(1 )— 192(19) may be positioned sufficiently close to the sensors (S) so that each of the sensors (S) can be coupled to a corresponding satellite monitor 192 using relatively short local signal wires, rather than transmitting analog signals over relatively long distances for conversion to digital data using central system monitor.
  • implementations of the monitoring systems disclosed herein may eliminate the need for metal-layer signal routing resources to route these analog signals from various locations distributed throughout the device 100 to a central monitor for conversion to digital data, which may reduce device complexity and cost while also increasing scalability of the monitoring system.
  • simultaneously measured is not limited by the number of input channels of the ADCs provided within the satellite monitors.
  • the number of sensors that can be simultaneously measured by conventional solutions which route analog sensor data to a central system monitor for conversion to digital data is limited by the number of input channels of the ADC associated with the system monitor.
  • the number of sensors that can be simultaneously measured by monitoring systems disclosed herein is based on the number of satellite monitors 192(1 )— 192(19), rather than on the number of input channels of any particular ADC.
  • the monitoring systems disclosed herein may simultaneously measure a much greater number of sensors than the aforementioned conventional solutions.
  • the root monitor 190 may receive the digital data routed from each of the satellite monitors 192(1 )— 192(19) by the network interconnect system 120, and may process the received digital data to determine the operating conditions of the selected circuits monitored by the sensors. In some implementations, the root monitor 190 may compare the measured operating conditions with one or more reference values to determine whether each of the selected circuits is operating within its specified operating range.
  • FIG. 1 is intended to illustrate only one example architecture of the programmable device 100.
  • the numbers of logic blocks in a column (or row), the relative width of the columns (or rows), the number and order of columns (or rows), the types of logic blocks included in the columns (or rows), the relative sizes of the logic blocks, and other architectural aspects shown in FIG. 1 are merely illustrative of the various implementations of the inventive subject matter disclosed herein.
  • FIG. 2 shows a functional block diagram of a programmable device 200 that may be one example of the programmable device 100 of FIG. 1 , in accordance with some implementations.
  • the device 200 is shown to include a transceiver block 150, programmable logic (PL) 210, a CPM 220, a processing system (PS) 230, a platform management controller (PMC) 240, and I/O blocks + memory controllers 260.
  • the PL 210 which may be one implementation of the PL 1 10 of FIG. 1 , may be adjacent to and directly connected to the transceiver blocks 150, the CPM 220, the PMC 240, and the network interconnect system 120.
  • the I/O blocks + memory controllers 260 may be implemented as a plurality of repeatable tiles arranged along the bottom edge of the programmable device 200. Although not shown in FIG. 2 for simplicity, the I/O blocks + memory controllers 260 may also be implemented as a plurality of repeatable tiles arranged along the top edge of the programmable device 200. In addition, or in the alternative, the I/O blocks + memory controllers 260 may be implemented as a plurality of repeatable tiles arranged along the right and left edges of the programmable device 200.
  • the CPM 220 may provide interfacing capabilities for a number of different bus standards.
  • the CPM 220 may include a peripheral component interconnect express (PCIe) interface 222, a direct memory access (DMA) circuit 224, and a cache coherent interconnect for accelerators (CCIX) interface 226.
  • PCIe peripheral component interconnect express
  • DMA direct memory access
  • CCIX cache coherent interconnect for accelerators
  • the PCIe interface 222 may be used to exchange data between the PS 230 and one or more other devices or chips via the transceiver blocks 150 according to a PCI protocol.
  • the CCIX interface 226 may be used to exchange data between the PS 230 and one or more other devices or chips via the transceiver blocks 150 according to a CCIX protocol.
  • the PS 230 may provide dedicated data processing capabilities for the device 200, and is shown to include an application processing unit (APU) 232, a real-time processing unit (RPU) 234, cache memory 236, and a system-on-a-chip (SoC) interface 238. Although not shown for simplicity, the PS 230 may also include peripherals for communication standards (such as Ethernet and USB 2.0 interfaces) and various controllers (such as SPI, I2C, UART, and CAN-FD controllers).
  • the APU 232 and the RPU 234 may each include one or more processing cores (such as CPUs) that can provide dedicated scalar processing capabilities for the device 200.
  • the PS 230 may be selectively connected to other subsystems of the device 200 by the programmable
  • the APU 232 may include a multi-core ARM processor that supports hardware virtualization, and may have a built-in interrupt controller and snoop control unit.
  • the interrupt controller may support virtual interrupts, and the snoop control unit may be used maintain coherency between one or more caches used and/or shared by APU 232 and RPU 234.
  • the APU 232 may communicate with other components of the PS 230 using an AXI coherent extension (ACE) port, and may communicate with the PL 210 using an accelerator coherency port (ACP).
  • ACE AXI coherent extension
  • ACP accelerator coherency port
  • the RPU 234 may include a multi-core ARM processor that supports real-time data processing, may include tightly coupled memory (TCM) interface for real-time single cycle access, and may have a dedicated interrupt controller and floating point unit.
  • the RPU 234 may communicate with other components of the PS 230 and/or with the PL 210 using AXI ports.
  • the cache memory 236 may be any suitable high-speed cache that allows for shared access by the APU 232 and the RPU 234.
  • the SoC interface 238 may provide connectivity between various resources of the PS 230 and the network interconnect system 120.
  • the PMC 240 may include security circuitry 242, booting and reconfiguration circuitry 244, analog circuitry 246, and the root monitor 190 of FIG. 1 .
  • the security circuitry 242 may provide data encryption/decryption capabilities and other security features.
  • the booting and reconfiguration circuitry 244 may provide a multi-stage boot process that supports both a non-secure and a secure boot.
  • the analog circuitry 246 may include any suitable analog circuit components.
  • the PMC 240 may include test and debugging resources (such as JTAG circuitry), external flash memory interfaces, and other components or circuits. In some implementations, the PMC 240 may allow portions of the PL 210 to be reconfigured using a partial reconfiguration operation.
  • a new configuration bitstream for a portion of the PL 210 can be loaded from the PS 230 via either a primary or secondary boot interface (such as PCIe or Ethernet), and then stored in configuration registers associated with the portions of the PL 210 to be reconfigured.
  • a primary or secondary boot interface such as PCIe or Ethernet
  • the ability to allow for partial reconfiguration of one or more portions of the PL 210 may allow a user to more quickly reconfigure the device 200 to reflect changes or updates to the user-specified circuit design (such as compared with other programmable devices).
  • FIG. 3 shows a block diagram of an example programmable fabric 300 in accordance with some implementations.
  • the configuration in accordance with some implementations.
  • programmable fabric 300 may be the PL 1 10 of FIG. 1 , the PL 210 of FIG. 2, or both.
  • the programmable fabric 300 is shown to include a plurality of different programmable circuit blocks or tiles that can be arranged in columns (or rows).
  • the programmable circuit blocks may include (but are not limited to) programmable interconnect elements (INT) 310, configurable logic elements (CLEs) 320, DSPs 330, and block RAMs (BRAMs) 340 arranged in a columnar architecture.
  • programmable interconnect elements INT
  • CLEs configurable logic elements
  • BRAMs block RAMs
  • the programmable fabric 300 is shown to include eleven columns of programmable interconnect elements 310, five columns of CLEs 320, two columns of DSPs 330, and two columns of BRAM 340.
  • the programmable fabric 300 may include other numbers of columns of programmable interconnect elements 310, CLEs 320, DSPs 330, and BRAMs 340.
  • the programmable fabric 300 may also include a number of other subsystems or components not shown in FIG. 3 for simplicity (such as processing cores, programmable interconnect structures, and the like).
  • the programmable interconnect elements 310, the CLEs 320, the DSPs 330, and the BRAM 340 may be implemented as tiles that can be repeated across the programmable fabric 300.
  • Each of the tiles may include at least one
  • programmable interconnect element 310 that provides local signal interconnections to a programmable logic element within the same tile, that provides local signal interconnections to programmable interconnect elements 310 within adjacent tiles, and/or that provides local signal interconnections to other signal routing resources.
  • the programmable interconnect elements 310 may collectively form at least a portion of the programmable interconnect fabric (or other suitable block-level and/or device-level signal routing structure).
  • the programmable fabric 300 may include a columnar hard block 350 that extends vertically across the height of the programmable fabric 300
  • the hard block 350 may include a number of hard-wired circuits such as, for example, USB controllers, Ethernet MACs, multi-rate (MR) Ethernet MACs, PCIe controllers, CCIX controllers, and/or other suitable circuits or components that implement the Physical Layer, the Data Link Layer, and the Transaction Layer of the PCIe protocol.
  • the hard block 350 may be one implementation of the connectivity fabric described above with respect to FIG. 1 .
  • FIG. 4 shows a functional block diagram of a monitoring system 400, in accordance with some implementations.
  • the monitoring system 400 which may be implemented in the programmable device 100 of FIG. 1 , is shown to include a root monitor 410, a plurality of satellite monitors SAT1-SAT15, a plurality of supply voltage sensors SV1-SV4, a plurality of temperature sensors T5-T15, and a plurality of selected circuits CKT5-CKT 15.
  • the root monitor 410 which may be one implementation of the root monitor 190 of FIG. 1 , is coupled to the network interconnect system 120 and may include circuitry to generate the reference voltage (VREF).
  • the root monitor 41 0 may include a bandgap reference circuit (not shown for simplicity) that generates a temperature- compensated reference voltage VREF.
  • the satellite monitors SAT 1 -SAT 15 may be distributed across the device
  • each of the satellite monitors SAT1-SAT15 is positioned in a vicinity of a corresponding one of the sensors SV1-SV4 and T5- T15.
  • the satellite monitors SAT1-SAT4 are coupled to respective supply voltage sensors SV1-SV4 via local signal wires
  • the satellite monitors SAT5-SAT 15 are coupled to respective temperature sensors T5-T15 via local signal wires.
  • analog signals generated by the supply voltage sensors SV1-SV4 may be provided to respective satellite monitors SAT1 -SAT4 by local signal wires
  • analog signals generated by the temperature sensors T5-T15 may be provided to respective satellite monitors SAT5-SAT 15 by local signal wires.
  • analog signals generated by the sensors SV1-SV4 and T5-T15 do not have to be routed across large portions of the device 100 to reach the root monitor 410, thereby minimizing signal degradation associated with routing relatively small analog signals across metal-layer interconnections that span across the device 100.
  • analog signals generated by each of the sensors SV1- SV4 and T5-T15 may be locally converted into digital data using a nearby one of the satellite monitors SAT1-STA15, expensive metal-layer routing resources are not needed to implement the monitoring system 400 within a programmable device (such as the programmable device 100 of FIG. 1 ).
  • the sensor SV1 may monitor the operating conditions of an associated supply voltage by generating analog signals indicative of the voltage level of the associated supply voltage.
  • the analog signals generated by the sensor SV1 do not need to be routed across the device 100 to the root monitor 410, but instead may be routed a relatively short distance to the satellite monitor SAT1 via local signal wires.
  • the sensor T5 may monitor the operating conditions of an associated circuit CKT5 by generating analog signals indicative of the temperature of the associated circuit CKT5.
  • the analog signals generated by the sensor T5 do not need to be routed across the device 100 to the root monitor 410, but instead may be routed a relatively short distance to the satellite monitor SAT5 via local signal wires.
  • the reference voltage VREF may be distributed across the device 100 and made accessible to each of the satellite monitors SAT1-STA15 by one or more dedicated analog channels of the network interconnect system 120, and the digital data may be selectively routed from each of the satellite monitors SAT1-STA15 to the root monitor 410 by one or more digital channels of the network interconnect system 120.
  • the one or more analog channels may be physically separated from the one or more digital channels.
  • FIG. 5 shows a block diagram of an example root monitor 500, in accordance with some implementations.
  • the root monitor 500 which may be one implementation of the root monitor 190 of FIG. 1 or the root monitor 410 of FIG. 4 (or both), is shown to include a voltage generator 510, a memory 520, and a controller 530.
  • the voltage generator 510 which may be any suitable circuit or device that can generate a trimmed voltage suitable for use as the reference voltage VREF, includes an output coupled to one or more analog channels 121 of the network interconnect system 120. Referring also to FIG. 1 , in some embodiments, in some embodiments, includes an output coupled to one or more analog channels 121 of the network interconnect system 120.
  • the reference voltage VREF generated by the voltage generator 510 may be distributed to each of the satellite monitors 192(1 )— 192(19) located throughout the device 100 using the one or more analog channels 121 of the network interconnect system 120.
  • the satellite monitors 192(1 )— 192(19) may access the reference voltage VREF from the network interconnect system 120, and may use the distributed reference voltage VREF to perform analog-to-digital conversions (or for other suitable operations).
  • the voltage generator 510 may include a bandgap circuit 512 that can generate a temperature-compensated voltage, for example, so that the reference voltage VREF is adjusted for temperature variations.
  • the voltage generator 510 may provide both a positive reference voltage and a negative reference voltage to the one or more analog channels 121 of the network interconnect system 120.
  • the reference voltage VREF may be equal to 1 .25 volts, although other suitable voltages may be used as VREF.
  • the memory 520 includes a data input coupled to one or more digital channels 122 of the network interconnect system 120, a control input coupled to the controller 530, a data output coupled to the controller 530, and one or more output ports from which data stored therein can be accessed by a user via one or more of a JTAG interface, a multiplexed input/output (MIO) block, or an AXI interface.
  • the memory 520 may include a number of status registers 521 and a number of alarm register 522.
  • the status registers 521 may store digital data indicative of operating conditions of the selected circuits provided throughout the device 100, and the alarm registers 522 may store a plurality of reference values that define a number of specified operating ranges.
  • the status registers 521 may be loaded with digital data routed from the satellite monitors 192(1 )— 192(19) to the root monitor 500 via the network interconnect system 120, and the alarms registers 522 may be loaded with the reference values during configuration (or re-configuration) of the programmable device 100.
  • the controller 530 may control various operations of the root monitor 500, may analyze the digital data received from the satellite monitors 192(1 )— 192(19) to determine whether any of the selected circuits are not operating within their specified operating ranges, and may generate result data that can be accessed by the user. In some implementations, the controller 530 may determine whether a selected circuit is operating within a specified operating range by comparing the measured operating conditions stored in the status registers 521 with
  • the controller 530 may generate an alarm.
  • the alarm may cause the selected circuit to be disabled or powered-down, for example, until the operating conditions of the selected circuit are within its specified operating range.
  • the alarm may cause the programmable device 100 to be powered-down or to operate at a reduced power level, for example, until the operating conditions of the selected circuit are within the specified operating range.
  • a specified voltage range may include a minimum voltage value and a maximum voltage value.
  • the controller 530 may compare the measured voltage of the selected circuit with the minimum and maximum voltage values stored in the alarms registers 522, and may generate one or more alarms based on the comparison. For example, if the measured voltage is between the minimum and maximum voltage values, the controller 530 may indicate that the selected circuit is operating within its specified voltage range. Conversely, if the measured voltage is less than the minimum voltage value or greater than the maximum voltage value, the controller 530 may generate an alarm to indicate that the selected circuit is not operating within its specified voltage range.
  • Other specified operating ranges stored in the alarms registers 522 may include a reference value that defines an upper operational limit.
  • a specified temperature range for a selected circuit may be defined by a reference temperature value.
  • the controller 530 may compare the measured temperature of the selected circuit with the reference temperature value stored in the alarms registers 522, and may generate one or more alarms based on the comparison. For example, if the measured temperature is less than (or equal to) the reference temperature value, the controller 530 may indicate that the selected circuit is operating within its specified temperature range. Conversely, if the measured temperature is greater than the reference temperature value, the controller 530 may generate an alarm to indicate that the selected circuit is too hot or overheated.
  • FIG. 6 shows a block diagram of an example satellite monitor 600, in accordance with some implementations.
  • the satellite monitor 600 which may be one example of any number of the satellite monitors 192(1 )— 192(19) of FIG. 1 or the satellite monitors SAT1-SAT15 of FIG. 4 (or both), includes a data input coupled to one or more sensors 20, an output coupled to the network interconnect system 120, and a reference terminal coupled to the network interconnect system
  • the satellite monitor 600 may receive the reference voltage VREF generated by the root monitor 500 and distributed by one or more analog channels
  • the sensors 20 may include (but are not limited to) temperature sensors 21 , supply voltage sensors 22, and external sensors 23.
  • the satellite monitor 600 is shown to include an ADC circuit 610, a memory 620, and a local reference circuit 630.
  • the ADC circuit 610 includes inputs coupled to the one or more sensors 20 via a second switch SW2, an output coupled to the memory 620, and one or more reference terminals coupled to the local reference circuit 630.
  • the ADC circuit 610 may be (or may include) any suitable ADC that can convert analog signals generated by one or more of the sensors 20 into digital signals or digital data.
  • the ADC circuit 610 may utilize a scaled architecture to digitize analog sensing data provided by the sensors 20.
  • the memory 620 which may be any suitable storage device, includes an input coupled to the output of the ADC circuit 610, and includes an output coupled to the network interconnect system 120.
  • the memory 620 may store digital data generated by the ADC circuit 610 in response to the analog signals provided by one or more of the sensors 20, and may provide the digital data to the one or more digital channels 122 of the network interconnect system 120 for routing to the root monitor 500 of FIG. 5.
  • the memory 620 may be or may include a plurality of registers each for storing digital data indicative of the operating conditions of a corresponding one of a plurality of circuits selected for monitoring.
  • the satellite monitor 600 may receive analog signals indicative of operating conditions of a corresponding one of the selected circuits from the sensors 20, may convert the analog signals into digital data, and may provide digital data indicative of the operating conditions of the selected circuit to one or more digital channels 122 of the network interconnect system 120.
  • the local reference circuit 630 which is coupled between the first switch SW1 and the one or more reference terminals of the satellite monitor 600, may be any suitable device or component that can provide a local reference voltage (VREF LOCAL) to the ADC circuit 610.
  • the local reference voltage VREF LOCAL may be based at least in part on the reference voltage VREF distributed by the network interconnect system 120, may be used by the ADC circuit 610 to perform analog-to-digital conversions.
  • the first switch SW1 may be configured to selectively couple the reference voltage VREF distributed by the network interconnect system 120 to the satellite monitor 600 based on a first control signal (CTRL1 ).
  • the first switch SW1 may couple the reference terminal of the satellite monitor 600 to the network interconnect system 120 when the first control signal CTRL1 is in an asserted state (such as logic high), and may isolate the satellite monitor 600 from the network interconnect system 120 when the first control signal CTRL1 is in a de- asserted state (such as logic low). In this manner, the first switch SW1 may be used to control when (and for how long) the satellite monitor 600 accesses the reference voltage VREF distributed by the network interconnect system 120.
  • an asserted state such as logic high
  • de- asserted state such as logic low
  • the first control signal CTRL1 may be generated by the root monitor 500 of FIG. 5, and may be routed to the satellite monitor 600 by the network interconnect system 120 (or by other suitable signal interconnections).
  • the root monitor 500 may assert the first control signal CTRL1 for each of a plurality of satellite monitors 600 distributed across a programmable device based on a timing schedule, for example, such that only one of the satellite monitors 600 can access the distributed reference voltage VREF via the network interconnect system 120 at any given instant in time. In this manner, the root monitor 500 may prevent dips in the distributed reference voltage VREF caused by more than one of the satellite monitors 600 accessing the distributed reference voltage VREF at the same time.
  • the second switch SW2 may selectively couple one of the sensors 21-23 to the input of the ADC circuit 610 based on a second control signal (CTRL2).
  • CTRL2 may be generated by the root monitor 500 of FIG. 5, and may be routed to the satellite monitor 600 by the network interconnect system 120 (or by other suitable signal interconnections).
  • FIG. 7 is an illustrative flow chart depicting an example operation 700 for monitoring a number of operating conditions of a programmable device, in accordance with some implementations.
  • the example operation 700 is described below with respect to the programmable device 100 of FIG. 1 , the monitoring system 400 of FIG. 4, the root monitor 500 of FIG. 5, and the satellite monitor 600 of FIG. 6 for illustrative purposes only. It is to be understood that the example operation 700 may be performed by other programmable devices disclosed herein and/or by other suitable devices.
  • the operation 700 may begin at block 701 by generating a reference voltage (VREF) using a voltage generator 510 associated with a root monitor 190 provided within the programmable device 100.
  • the root monitor 190 may generate a trimmed and temperature-compensated reference voltage VREF, for example, using the bandgap circuit 512 of FIG. 5.
  • the operation 700 may proceed at block 702 by distributing the reference voltage VREF from the root monitor 190 to each of a plurality of satellite monitors 192 using one or more analog channels 121 of the interconnect system 120.
  • distributing the reference voltage VREF may include selectively coupling each of the plurality of satellite monitors 192(1 )— 192(19) to the interconnect system 120 based on a corresponding control signal CTRL1 generated by the root monitor 190.
  • the satellite monitor 600 may allow the satellite monitor 600 to access the reference voltage VREF from the network interconnect system 120 based on a first state of CTRL1 , and the first switch SW1 may isolate the satellite monitor 600 from the network interconnect system 120 based on a second state of CTRL1 .
  • the operation 700 may proceed at block 703 by generating, using each of a number of sensors 20, analog signals indicative of operating conditions of an associated circuit.
  • each of the number of sensors 20 may be located in the vicinity of the associated circuit.
  • the sensor 20 may be (or may include) at least one of a temperature sensor 21 , a supply voltage sensor 22, or an external sensor 23.
  • the operation 700 may proceed at block 704 by providing the analog signals generated by the number of sensors 20 to corresponding ones of the plurality of satellite monitors 192(1 )— 192(19).
  • the analog signals generated by the sensors 20 may be provided to corresponding satellite monitors 192(1 )— 192(19) using relatively short local signal wires, for example, in contrast to conventional programmable devices in which analog signals indicative of operating conditions of various circuits are routed across the device and provided to a central monitor using a metal-layer signal routing structure.
  • the operation 700 may proceed at block 705 by converting the analog signals into digital data using the plurality of satellite monitors 192(1 )— 192(19).
  • the ADC circuit 610 provided within each of the satellite monitors 192(1 )— 192(19) may convert the analog signals into digital data that can be stored in the memory 620 of each of the satellite monitors 192(1 )— 192(19).
  • the memory 620 may selectively provide the stored digital data to the interconnect system 120 for routing to the root monitor 190.
  • the operation 700 may proceed at block 706 by selectively routing the digital data from the plurality of satellite monitors 192(1 )— 192(19) to the root monitor 190 using one or more digital channels 122 of the interconnect system 120.
  • the digital channels 122 may be physically separate from the analog channels 121 of the interconnect system 120.
  • the satellite monitors 192(1 )— 192(19) may provide the digital data to the interconnect system 120 in response to a signal (such as a trigger signal) generated by the root monitor 190, for example, to schedule or prioritize the delivery of digital data from the plurality of satellite monitors 192(1 )— 192(19) to the root monitor 190.
  • the satellite monitors 192(1 )— 192(19) may provide the digital data to the interconnect system 120 without prompting and/or without control by the root monitor 190.
  • the operation 700 may proceed at block 707 by determining whether the operating conditions of at least one of the associated circuits are within a range, and may proceed at block 708 by selectively generating an alarm based on the determination.
  • the root monitor 500 may receive digital data from a selected one of the satellite monitors 192(1 )— 192(19), and may compare the received digital data with one or more reference values to determine whether the operating conditions of the associated circuit are within the range.
  • the root monitor 500 may generate alarms and/or may power-down one or more portions of the programmable device 100 (or the entire programmable device 100 if a number of the various circuits, blocks, and
  • the root monitor 500 may compare the measured voltage of the associated circuit with minimum and maximum reference voltage levels. If the measured voltage of the associated circuit is between the minimum and maximum reference voltage levels, the root monitor 190 may determine that the associated circuit is operating within a specified voltage range. Conversely, if the measured voltage of the associated circuit is less than the minimum reference voltage level or is greater than the maximum reference voltage level, the root monitor 190 may determine that the associated circuit is not operating within the specified voltage range.
  • the root monitor 500 may compare the measured temperature of the associated circuit with a reference temperature value. If the measured temperature of the associated circuit is not greater than the reference temperature value, the root monitor 190 may determine that the associated circuit is operating within its specified temperature range. Conversely, if the measured temperature of the associated circuit is greater than the reference temperature value, the root monitor 190 may determine that the associated circuit is not operating within the specified temperature range.
  • Implementations of the subject matter described in this disclosure may be used to monitor a number of operating conditions of a programmable device.
  • the operating conditions may be any suitable measure of the device’s operating characteristics or parameters including, for example, a temperature of a circuit or component provided within the programmable device, a temperature of a circuit or device external to the programmable device, a voltage level of a supply voltage, and the like.
  • the monitoring system may include a root monitor, a plurality of sensors distributed in various locations across the programmable device, and a plurality of satellite monitors distributed in the various locations across the programmable device.
  • the root monitor may include a bandgap voltage generator configured to generate a highly accurate and temperature-independent reference voltage, and the
  • temperature-independent reference voltage may be distributed from the root monitor to each of the satellite monitors via one or more analog channels spanning the programmable logic.
  • Each of the sensors may generate analog signals indicative of one or more operating conditions of an associated circuit, and may provide the analog signals to a corresponding one of the satellite monitors via one or more local signal lines.
  • Each of the satellite monitors may include an ADC to convert the analog signals into digital data, and may be positioned in a vicinity of one or more associated sensors, for example, so that analog signals generated by the one or more associated sensors may be routed a relatively short distance to a respective one of the satellite monitors via local signal lines for conversion into digital data.
  • the programmable device may include a network-on-chip (NoC) interconnect system that can selectively route digital data from each of the satellite monitors to the root monitor for processing, and that can route control signals and other information from the root monitor to each of the satellite monitors.
  • NoC network-on-chip
  • digital data generated by each of the satellite monitors may be routed to the root monitor using other suitable routing resources provided within the device including (but not limited to) clock distribution networks, a programmable interconnect fabric, and/or routing resources provided within repeatable tiles that form the programmable logic of the device.
  • the accuracy of thermal and voltage monitoring of a plurality of sensors distributed across a programmable device depends on accurate analog-to-digital conversions at each of the plurality of satellite monitors distributed across the programmable device.
  • the accuracy of analog-to-digital conversions may be based, at least in part, on the accuracy of the reference voltage provided to the ADC within each of the satellite monitors.
  • a bandgap voltage generator may be used to generate a highly-accurate and temperature-independent reference voltage, the bandgap voltage generator consumes a significant amount of circuit area and requires expensive and time-consuming trimming during manufacture of the programmable device.
  • each of the satellite monitors may include a relatively small voltage source (such as an area-efficient voltage source) configured to generate a local reference voltage for the corresponding ADC.
  • the local voltage source may be relatively small and thus“area-efficient” compared to the bandgap voltage generator provided in the root monitor.
  • the local voltage source may include fewer than a dozen transistors, and may consume at least one order of magnitude less circuit area than the bandgap voltage generator.
  • each of the satellite monitors may include a local voltage store configured to store a local reference voltage for the corresponding ADC.
  • the local voltage store may consist of a capacitor coupled to a switch (such as a transistor).
  • the local reference voltage may be relatively imprecise compared to the highly-accurate temperature-independent reference voltage generated by the bandgap voltage generator, and may result in errors in digital codes generated by the ADC provided within a corresponding one of the satellite monitors.
  • each of the satellite monitors may include a calibration circuit configured to generate a correction factor indicative of errors in the digital codes, and may include a correction circuit configured to correct the digital codes based on the correction factor.
  • the ADCs provided within the plurality of satellite monitors may be periodically calibrated relative to the highly-accurate and temperature- independent reference voltage by their corresponding calibration circuits and correction circuits, as described in more detail below.
  • Conventional systems for monitoring operating conditions of various circuits distributed across a programmable device typically include a central system monitor and a plurality of sensors positioned near the circuits to be monitored.
  • Each sensor generates analog signals indicative of the operating conditions of an associated circuit, and the analog signals are routed from each of the sensors to the system monitor for conversion to digital data.
  • the sensors are typically distributed in various locations throughout the device, and therefore the analog signals generated by at least some of the sensors may be routed across large portions of the device to reach the system monitor. Because analog signals indicative of operating conditions may be particularly susceptible to noise and interference, some programmable devices may use dedicated metal-layer routing resources with shielding properties to route these analog signals from the various sensors to the system monitor for conversion to digital data.
  • the shielding properties of such dedicated metal-layer routing resources may reduce signal degradation and data loss, the dedicated metal-layer routing resources are expensive and consume significant amounts of the device’s metal layers.
  • the signal routing resources embedded within each of the repeatable tiles is typically based on a worst-case routing scenario (such as for tiles to be placed in locations in which device density is the greatest). As a result, many of the repeatable tiles are over equipped with signal routing resources, which may result in unused routing resources and/or may limit scalability of the programmable device.
  • the monitoring systems disclosed herein may convert analog signals generated by the sensors into digital data using local satellite monitors, and then route digital data from the various locations throughout the device to the root monitor.
  • the analog signals are not routed across large portions of the device and then converted to digital data, but instead are transmitted relatively short distances to the nearest satellite monitor for conversion to digital data, which is then routed to the root monitor using the NoC interconnect system.
  • digital data generated by the satellite monitors may be routed to the root monitor as individually addressable data packets.
  • digital data generated by the satellite monitors may be routed to the root monitor as non-packetized data.
  • the monitoring systems disclosed herein do not need metal-layer routing resources, which in turn may reduce cost while increasing scalability of the programmable device.
  • performing the analog-to-digital conversions locally e.g., in the vicinities of the sensors
  • routing the resulting digital data from the satellite monitors to the root monitor may allow more sensor data to be collected and analyzed by the root monitor (as compared to prior techniques that route analog signals from various sensors located throughout the device to an ADC provided within a system monitor), for example, because the ADCs distributed throughout the programmable device may perform analog-to-digital conversions in parallel (e.g., at the same time).
  • buses or single signal lines may be shown as buses or as single signal lines.
  • Each of the buses may alternatively be a single signal line, and each of the single signal lines may alternatively be buses, and a single line or bus might represent any one or more of a myriad of physical or logical mechanisms for communication between components.
  • FIG. 8 shows a block diagram of an example programmable device 800 within which various aspects of the present disclosure may be implemented.
  • the device 800 may include a number of subsystems such as, for example,
  • the device 800 may include other subsystems or components not shown in FIG. 8. Further, although not shown for simplicity, the device 800 may be coupled to a number of peripheral components (such as a high-performance memory device) and/or other devices or chips (such as another programmable device).
  • PL programmable logic
  • NoC network-on-chip
  • interconnect system 820 spanning the PL 810, one or more analog channels 821 spanning the PL 810, dedicated circuitry 830, a CCIX and PCIe Module (CPM) 840, transceiver blocks 850, input/output (I/O) blocks 860, memory controllers 870, configuration logic 880, a root monitor 890, a plurality of satellite monitors 892(1 )— 892(19), and a plurality of sensors (S).
  • the device 800 may include other subsystems or components not shown in FIG. 8. Further, although not shown for simplicity, the device 800 may be coupled to a number of peripheral components (such as a high-performance memory device
  • the PL 810 includes programmable circuitry that may be configured or programmed to perform a multitude of different user-defined functions or operations.
  • the PL 810 may include a plurality of programmable circuit blocks implemented as repeatable tiles arranged in columns in the programmable device 800, for example, as depicted in FIG. 8.
  • the programmable circuit blocks which may also be referred to as programmable fabric sub-regions (FSRs), may each include programmable interconnect circuitry and programmable logic circuitry.
  • the programmable circuit blocks may include (but are not limited to) configurable logic blocks (CLBs), random access memory blocks (BRAM), digital signal processing blocks (DSPs), clock managers, delay lock loops (DLLs), and/or other logic or circuits that can be programmed or configured to implement a user-specified circuit design.
  • CLBs configurable logic blocks
  • BRAM random access memory blocks
  • DSPs digital signal processing blocks
  • DLLs delay lock loops
  • other logic or circuits that can be programmed or configured to implement a user-specified circuit design.
  • the programmable interconnect circuitry within each of the programmable circuit blocks or tiles may include a plurality of interconnect wires of varying lengths interconnected by programmable interconnect points (PIPs).
  • the interconnect wires may be configured to provide connectivity between components within a particular programmable tile, between components within different programmable tiles, and between components of a programmable tile and other subsystems or devices.
  • the programmable interconnect circuitry and the programmable circuit blocks may be programmed or configured by loading configuration data into configuration registers that define how the programmable elements are configured and operate to implement a corresponding user-specified circuit design.
  • the programmable interconnect circuitry within each of a number of the programmable circuit blocks may form part of a programmable interconnect fabric (not shown for simplicity) that provides block-level and/or device-level signal routing resources for the device 800.
  • the NoC interconnect system 820 which may be fabricated as part of the device 800, may include any number of horizontal segments and vertical segments (and/or diagonal segments) connected together to implement a high-speed, high- bandwidth programmable signal routing network that can selectively interconnect various device resources (such as the PL 810, the dedicated circuitry 830, the CPM 840, the transceiver blocks 850, the I/O blocks 860, the memory controllers 870, the configuration logic 880, the root monitor 890, and the satellite monitors 892(1 )- 892(19)) with each other and with other components not shown for simplicity.
  • the NoC interconnect system 820 is shown to include two horizontal segments and four vertical segments. A first horizontal segment extending across the width of the device 800 is positioned along a bottom boundary of the device 800, and a second horizontal segment extending across the width of the device 800 is positioned along the top boundary of the device 800.
  • the four vertical segments extend across the height of the device 800 and are connected to the first and second horizontal segments of the NoC interconnect system 820.
  • the horizontal segments may allow the NoC interconnect system 820 to exchange signals and data with the I/O blocks 860 and memory controllers 870 without any intervening circuits or interfaces
  • the vertical segments may allow the NoC interconnect system 820 to exchange signals and data with the transceiver blocks 850, the dedicated circuitry 830, and the CPM 840 without any intervening circuits or interfaces.
  • the NoC interconnect system 820 may include other numbers of horizontal and vertical segments, which in turn may occupy other positions of the device 800.
  • the particular layout, shape, size, orientation, and other physical characteristics of the example NoC interconnect system 820 depicted in FIG. 8 are merely illustrative of the various implementations disclosed herein.
  • the NoC interconnect system 820 may be configured to transmit information between various device resources as data packets that can be individually addressed and routed from a source location to a destination location.
  • the data packets transmitted on the NoC interconnect system 820 may be dynamically addressable.
  • the NoC interconnect system 820 may employ a suitable data packet protocol (such as token ring protocol) and/or use memory-mapped addresses to route data packets from any number of source locations to any number of destination locations.
  • the data packets may include header information (such as source addresses, destination addresses, and protocol information) that can be used by the NoC interconnect system 820 to route the data packets to their indicated destinations.
  • the data packets may include Quality-of-Service (QoS) information that allows the transmission of data packets through the NoC interconnect system 820 to be prioritized, for example, based on assigned priorities, traffic types, traffic flows, and/or other criteria.
  • QoS Quality-of-Service
  • the NoC interconnect system 820 may include priority logic that can determine priority levels or traffic classes of received data packets, and use the determined priority levels or traffic classes when queuing the data packets for transmission.
  • the NoC interconnect system 820 may provide connectivity between the various device resources, irrespective of a particular user- specified circuit design, thereby significantly increasing the signal routing capabilities of the device 800 (as compared to conventional programmable devices).
  • the NoC interconnect system 820 may concurrently route each of a plurality of data packets from any source address to any destination address on the device 800, thereby providing system-level connectivity for the device 800.
  • the NoC interconnect system 820 may also include a scheduler and arbitration logic.
  • the scheduler may be used to schedule the transmission of data packets from a source address to a destination address using one or more physical and/or virtual channels of the NoC interconnect system 820.
  • the arbitration logic may be used to arbitrate access to the NoC interconnect system 820, for example, to minimize collisions and other contention-related latencies.
  • the columnal portions of the NoC interconnect system 820 may provide signal connections between adjacent super logic regions (SLRs), for example, to allow configuration data to be routed between master and slave SLRs.
  • SLRs super logic regions
  • the NoC interconnect system 820 may be programmed by loading configuration data into corresponding configuration registers that define how various switches, interfaces, and routers within or associated with the NoC interconnect system 820 are configured to implement a particular user-specified circuit design.
  • the NoC interconnect system 820 may include a plurality of nodes, ports, or other interfaces (not shown for simplicity) that provide selective connectivity between the NoC interconnect system 820 and the various resources, subsystems, circuits, and other components of the device 800.
  • the NoC interconnect system 820 may allow multiple subsystems of the device 800 to share access to on-chip memory (OCM) resources, processing resources, I/O resources, and/or the transceiver blocks 850.
  • OCM on-chip memory
  • the nodes, ports, or other interfaces of the NoC interconnect system 820 may be programmed to implement a particular connectivity profile by loading configuration data into one or more associated configuration registers.
  • the NoC interconnect system 820 may alleviate signal routing burdens on local interconnect resources, thereby increasing device performance and allowing for greater configuration flexibility than other programmable devices. Moreover, by providing a high-performance signal routing network having higher data
  • the NoC interconnect system 820 may increase the processing power and data throughput of the device 800 (as compared to other programmable devices).
  • the analog channels 821 spanning the programmable device 800 may be used to distribute a highly-accurate and temperature-independent reference voltage from the root monitor 890 to each of the plurality of satellite monitors 892(1 )- 892(19).
  • the analog channels 821 may be adjacent to (or integrated within) corresponding segments of the NoC interconnect system 820.
  • the analog channels 821 may be separate from the NoC interconnect system 820.
  • the analog channels 821 may be part of a clock distribution network or some other suitable signal
  • the dedicated circuitry 830 may include any suitable hard-wired circuits including (but not limited to) processors, serial transceivers, digital signal processors (DSPs), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), device management resources, device monitoring resources, device testing management resources, and so on.
  • the dedicated circuitry 830 may include a processing system (PS) and a platform management controller (PMC), described with respect to FIG. 9.
  • the PS may include one or more processor cores, cache memory, memory controllers, and unidirectional and/or bidirectional interfaces configurable to couple directly to the I/O pins of the device 800.
  • each processor core may include central processing units (CPU) or scalar processors that can be used for sequential data processing.
  • the PMC may be used for booting and configuring the device 800 based on configuration data (such as a configuration bitstream) provided from external memory.
  • the PMC may also be used to configure the PL 810 and to control various encryption, authentication, root monitoring, and debug capabilities of the device 800.
  • the CCIX and PCIe module (CPM) 840 may include a number of interfaces that provide connectivity between the device 800 and a number of peripheral components (such as external devices or chips).
  • the CPM 840 may include a plurality of peripheral interconnect express (PCIe) interfaces and cache coherent interconnect for accelerators (CCIX) interfaces that provide connectivity to other devices or chips via the transceiver blocks 850.
  • PCIe peripheral interconnect express
  • CCIX cache coherent interconnect for accelerators
  • the PCIe and CCIX interfaces may be implemented as part of the transceiver blocks 850.
  • One example implementation of the CPM 840 is described with respect to FIG. 9.
  • the transceiver blocks 850 may provide signal connections with one or more other devices or chips (not shown for simplicity) connected to the device 800.
  • the transceiver blocks 850 may include a number of different serial transceivers such as, for example, gigabit serial transceivers (GTs).
  • GTs gigabit serial transceivers
  • the transceiver blocks 850 may be implemented as a plurality of repeatable tiles positioned in various locations along the right and left sides of the device 800, as depicted in FIG. 8. In other implementations, the transceiver blocks 850 may be positioned in other suitable locations of the device 800. In one or more
  • each of the transceiver blocks 850 may be coupled to one or more associated voltage supplies (not shown for simplicity).
  • each bank of transceiver circuits within a given transceiver block 850 may include or may be coupled to a corresponding voltage supply, for example, so that each bank of transceiver circuits may be powered using a separate voltage supply.
  • the I/O blocks 860 are coupled to the device’s I/O pins (not shown for simplicity), and may provide I/O capabilities for the device 800.
  • the I/O blocks 860 may receive data from one or more other devices, and may drive the received data to a number of destinations in the device 800.
  • the I/O blocks 860 may also receive data from a number of sources in the device 800, and may drive the received data to one or more other devices via the device’s I/O pins.
  • the I/O blocks 860 may be implemented as repeatable tiles.
  • the device 800 may include any suitable number of I/O blocks 860, and therefore the example implementation depicted in FIG. 8 is merely illustrative.
  • the I/O blocks 860 may include any number of suitable I/O circuits or devices.
  • the I/O blocks 860 may include extremely high- performance I/O (XPIO) circuits, high-density I/O (HDIO) circuits, and multiplexed I/O (MIO) circuits.
  • the XPIO circuits may be optimized for high-performance communications such as providing a high-speed, low latency interface to the memory controllers 870.
  • the XPIO circuits may include dedicated memory resources that can be accessed by other subsystems of the device 800 without using the memory controllers 870.
  • the HDIO circuits may provide a cost-effective solution that supports lower speed and higher voltage I/O capabilities (as compared with the XPIO circuits).
  • the MIO circuits may provide general-purpose I/O resources that can be accessed by various subsystems such as, for example, the PL 810, the dedicated circuitry 830, and the CPM 840.
  • the memory controllers 870 may be used to control access to various memory resources provided within and/or external to the device 800. In some implementations, the memory controllers 870 may be used to access dedicated memory residing in one or more of the I/O blocks 860.
  • the memory controllers 870 may include double data rate v4 (DDR4) memory controllers, high bandwidth memory (HBM) controllers, and/or other suitable memory controllers. In one or more implementations, some or all of the memory controllers 870 may include a scheduler having transaction reordering capabilities that may improve memory access efficiency. In addition, or in the alternative, the repeatable tiles that implement the memory controllers 870 may be different from one another. For example, a first number of the memory controllers 870 may implement DDR4 memory controllers, a second number of the memory controllers 870 may implement LPDDR4 memory controllers, and a third number of the memory controllers 870 may implement HBM controllers.
  • the device 800 may include any number of I/O blocks 860 and memory controllers 870, and therefore the numbers and positions of the I/O blocks 860 and memory controllers 870 depicted in FIG. 8 are merely illustrative.
  • a first row of I/O blocks 860 and memory controllers 870 may be implemented as repeatable tiles positioned along the bottom edge of the device 800, and a second row of I/O blocks 860 and memory controllers 870 may be implemented as repeatable tiles positioned along the top edge of the device 800.
  • the I/O blocks 860 and memory controllers 870 may be alternately positioned or distributed relative to each other, for example, as depicted in the example of FIG. 8. In other implementations, a pair of I/O blocks 860 and memory controllers 870 may be implemented within the same repeatable tile.
  • the first row of I/O blocks 860 and memory controllers 870 positioned along the bottom of the device 800 may be coupled to the first horizontal segment of the NoC interconnect system 820, and the second row of I/O blocks 860 and memory controllers 870 positioned along the top of the device 800 may be coupled to the second horizontal segment of the NoC interconnect system 820.
  • the NoC interconnect system 820 may provide connectivity between the programmable resources of the device 800 and its I/O pins (not shown for simplicity).
  • the device 800 may include one or more columns of connectivity fabric (not shown for simplicity) extending vertically across the height of the device 800 and positioned in a vicinity of the transceiver blocks 850.
  • the connectivity fabric may include one or more hard-wired circuits including (but not limited to) USB controllers, Ethernet MACs, multi-rate (MR) Ethernet MACs (MRMACs), PCIe controllers, CCIX controllers, and/or other components to provide connectivity between the transceiver blocks 850 and the PL 810.
  • the configuration logic 880 may be used to load configuration data (such as a configuration bitstream) from an external memory and route portions (such as frames, words, bytes, and/or bits) of the configuration data to the appropriate configuration registers that define how the various programmable resources of the device 800 are configured.
  • the configuration logic 880 may also be used to partially re-configure the device 800 and/or to internally reconfigure one or more portions of the device 800.
  • the configuration logic 880 may include configuration registers, boundary-scan test circuitry (such as TAP controller circuitry), encryption circuitry to encrypt bitstreams of configuration data read out of the device 800, and decryption circuitry to decrypt bitstreams of configuration data loaded into the device 800.
  • the device 800 may include an interface between the programmable fabric and each of the rows of I/O blocks 860 and memory controllers 870 positioned on the boundary of the device 800.
  • This interface which may be referred to herein as a Boundary Logic Interface (BLI)
  • BLI Boundary Logic Interface
  • HBM large and complex external devices
  • CLB blocks
  • the BLI may be arranged in rows positioned at the top and bottom boundaries or edges of the programmable fabric. In this manner, the BLI may be used to route signals between columnar logic structures (such as a CLB column or a DSP column) and rows of I/O resources (such as the I/O blocks 860).
  • programmable device 800 may include a monitoring system that can monitor one or more operating conditions of a plurality of selected circuits provided throughout the programmable device 800, for example, to ensure that the selected circuits operate within specified operational parameters.
  • the monitoring system disclosed herein may measure any suitable operating condition of the selected circuits including, for example, temperature, voltage levels, and current levels.
  • selected circuits may refer to any circuit, component, supply voltage, structure, or device that can be selected for monitoring one or more operating conditions to ensure proper operation of the device 800.
  • the monitoring system may generate an alarm (or multiple alarms) when the measured operating conditions of one or more of the selected circuits do not fall within a specified range of operating conditions.
  • the alarms may be used to power-down one or more circuits or components of the device 800. In other aspects, the alarms may be used to power-down the entire device 800.
  • the monitoring system may include (or may be formed by) the root monitor 890, the satellite monitors 892(1 )— 892(19), and the sensors (S).
  • the root monitor 890 is coupled to the NoC interconnect system 820 and to the analog channels 821 , and may include circuity configured to generate the highly-accurate and temperature-independent reference voltage.
  • the temperature-independent reference voltage may be distributed to each of the satellite monitors 892(1 )- 892(19) via the one or more analog channels 821 , thereby eliminating the need for each of the satellite monitors 892(1 )-892(19) to generate its own highly-accurate and temperature-independent reference voltage.
  • the root monitor 890 may be positioned within the processor system of the device 800, for example, as depicted in FIG. 8. In other implementations, the root monitor 890 may be positioned in other suitable locations in the device 800.
  • the sensors (S) may be any suitable sensing circuit or device that can generate electrical signals indicative of one or more operating conditions of at least one of the selected circuits, and may include (but are not limited to) temperature sensors, voltage sensors, and/or current sensors. In some implementations, each sensor (S) may measure the operating conditions of one or more selected circuits, and may provide analog signals indicative of the measured operating conditions to a corresponding one of the satellite monitors 892(1 )-892(19).
  • the satellite monitors 892(1 )-892(19) may be any suitable circuit or device that can convert analog signals generated by the sensors (S) into digital data indicative of the measured operating conditions of the selected circuits.
  • each of the satellite monitors 892(1 )-892( 19) may include at least an analog-to-digital converter (ADC), a local voltage source having a relatively small size (such as compared with the bandgap voltage generator), a calibration circuit, and a correction circuit.
  • ADC analog-to-digital converter
  • the ADC which may be any suitable circuit that can convert analog signals into digital data, may include one or more inputs to receive analog signals generated by one or more associated sensors (S), one or more outputs to provide digital data indicative of the operating conditions measured by the associated sensors (S), and one or more reference terminals to receive a local reference voltage.
  • S associated sensors
  • S outputs
  • S reference terminals
  • each of the satellite monitors 192(1 )— 192(19) may include at least an analog-to-digital converter (ADC), a local voltage store configured to store a local reference voltage for the corresponding ADC, a calibration circuit, and a correction circuit.
  • the local voltage store which for some implementations may be or employ a capacitor, has a relatively small size compared to the bandgap voltage generator.
  • the circuit area consumed by the local voltage store may be at least one order of magnitude smaller than the circuit area consumed by the bandgap voltage generator.
  • the voltage store may be selectively coupled to the one or more analog channels to charge the voltage store to a value approximately equal to the temperature-independent reference voltage. The resulting charge stored in the voltage store may be the local reference voltage provided to the reference terminals of the ADC.
  • the local voltage source may generate the local reference voltage, which may be relatively imprecise compared to the highly-accurate and temperature- independent reference voltage provided by the root monitor 890.
  • the local reference voltage may be at least one order of magnitude less accurate than the temperature-independent reference voltage generated by the bandgap voltage generator.
  • the local reference voltage may have an accuracy of approximately 5% within a target voltage, while the temperature-independent reference voltage may have an accuracy of approximately 0.5% within the target voltage.
  • the calibration circuit may generate a correction factor indicative of errors in digital codes generated by the ADC, and the correction circuit may correct the digital codes based on the correction factor.
  • the sensors (S) and the satellite monitors 892(1 )-892(19) may be distributed throughout the programmable device 800 and positioned in various locations near the selected circuits, for example, so that analog signals indicative of operating conditions of the selected circuits may be converted to digital signals at the various distributed locations (rather than transmitted to a central hub and then converted into digital data).
  • each of the sensors (S) may be positioned in a vicinity of a corresponding selected circuit, for example, so that the sensor (S) and the corresponding selected circuit may be coupled together using local signal lines.
  • each of the satellite monitors 892(1 )-892( 19) may be positioned in a vicinity of one or more associated sensors (S), for example, so that the satellite monitor 892 and the one or more associated sensors (S) may be coupled together using local signal lines.
  • the term“vicinity” as used herein may refer to a distance over which analog signals indicative of operating conditions can be transmitted via relatively short local signal wires with minimal signal degradation.
  • a first group of sensors (S) located within the transceiver blocks 850 may be positioned in the respective vicinities of voltage supplies (not shown for simplicity) associated with the transceiver blocks 850, and a first group of satellite monitors 892(1 )-892(6) may be positioned in the vicinities of the first group of sensors (S), for example, so that each of the first group of sensors (S) may be coupled to a corresponding supply voltage and to a corresponding satellite monitor 890 by relatively short local signal wires.
  • each of the first group of sensors (S) may be configured to generate analog signals indicative of one or more operating conditions of a corresponding voltage supply
  • each of the first group of satellite monitors 892(1 )-892(6) may be configured to convert analog signals generated by the associated sensor (S) into digital data that can be transmitted to the root monitor 890 via the NoC interconnect system 820.
  • a second group of sensors (S) located within the PL 810 may be positioned in the vicinities of one or more corresponding selected circuits (not shown for simplicity) within or associated with the PL 810, and a second group of satellite monitors 892(7)-892(19) may be positioned in the vicinities of the second group of sensors (S), for example, so that each of the second group of sensors (S) may be coupled to a corresponding selected circuit and to a corresponding one of the second group of satellite monitors 892(7)-892(19) by relatively short local signal wires.
  • each of the second group of sensors (S) may be configured to generate analog signals indicative of one or more operating conditions of a corresponding selected circuit
  • each of the second group of satellite monitors 892(7)-892(19) may be configured to convert analog signals generated by the associated sensor (S) into digital data that can be transmitted to the root monitor 890 via the NoC interconnect system 820.
  • Each of the satellite monitors 892(1 )-892(19) may be coupled to any suitable number of sensors (S) by local signal lines.
  • satellite monitor 892(1 ) may be coupled to a single sensor (S) positioned within the transceiver blocks 850, and may generate digital signals indicative of one or more operating conditions of a corresponding voltage supply associated with the transceiver blocks 850.
  • satellite monitor 892(16) may be coupled to two sensors (S) positioned within the PL 810, and may generate digital signals indicative of one or more operating conditions of selected circuits associated with the two sensors (S) positioned within the PL 810.
  • satellite monitor 892(17) may be coupled to four sensors (S) positioned within the PL 810, and may generate digital signals indicative of one or more operating conditions of selected circuits associated with the four sensors (S) positioned within the PL 810.
  • the programmable device 800 may include other numbers of satellite monitors 892 positioned in other suitable locations of the programmable device 800.
  • the satellite monitors 892(1 )-892( 19) may be positioned sufficiently close to the sensors (S) so that each of the sensors (S) can be coupled to a corresponding satellite monitor 892 using relatively short local signal wires, rather than transmitting analog signals over relatively long distances for conversion to digital data using central system monitor.
  • implementations of the monitoring systems disclosed herein may eliminate the need for metal-layer signal routing resources to route these analog signals from various locations distributed throughout the device 800 to a central monitor for conversion to digital data, which may reduce device complexity and cost while also increasing scalability of the monitoring system.
  • simultaneously measured is not limited by the number of input channels of the ADCs provided within the satellite monitors.
  • the number of sensors that can be simultaneously measured by conventional solutions which route analog sensor data to a central system monitor for conversion to digital data is limited by the number of input channels of the ADC associated with the system monitor.
  • the number of sensors that can be simultaneously measured by monitoring systems disclosed herein may be based on the number of satellite monitors 892(1 )-892(19), rather than on the number of input channels of a centrally-located ADC that receives analog signals from sensors distributed across the device.
  • the monitoring systems disclosed herein may
  • the root monitor 890 may receive the digital data routed from each of the satellite monitors 892(1 )-892(19) by the NoC interconnect system 820, and may process the received digital data to determine the operating conditions of the selected circuits monitored by the sensors. In some implementations, the root monitor 890 may compare the measured operating conditions with one or more reference values to determine whether each of the selected circuits is operating within its specified operating range.
  • FIG. 8 is intended to illustrate only one example architecture of the programmable device 800.
  • the numbers of logic blocks in a column (or row), the relative width of the columns (or rows), the number and order of columns (or rows), the types of logic blocks included in the columns (or rows), the relative sizes of the logic blocks, and other architectural aspects shown in FIG. 8 are merely illustrative of the various implementations of the inventive subject matter disclosed herein.
  • FIG. 9 shows a functional block diagram of a programmable device 900 that may be one example of the programmable device 800 of FIG. 8, in accordance with some implementations.
  • the device 900 is shown to include a transceiver block 850, programmable logic (PL) 910, a CPM 920, a processing system (PS) 930, a platform management controller (PMC) 940, and I/O blocks + memory controllers 960.
  • the PL 910 which may be one implementation of the PL 810 of FIG. 8, may be adjacent to and directly connected to the transceiver blocks 850, the CPM 920, the PMC 940, and the NoC interconnect system 820.
  • the I/O blocks + memory controllers 960 may be implemented as a plurality of repeatable tiles arranged along the bottom edge of the programmable device 900. Although not shown in FIG. 9 for simplicity, the I/O blocks + memory controllers 960 may also be implemented as a plurality of repeatable tiles arranged along the top edge of the programmable device 900. In addition, or in the alternative, the I/O blocks + memory controllers 960 may be implemented as a plurality of repeatable tiles arranged along the right and left edges of the programmable device 900.
  • the CPM 920 which may be one implementation of the CPM 840 of FIG. 8, may provide interfacing capabilities for a number of different bus standards.
  • the CPM 920 may include a peripheral component interconnect express (PCIe) interface 922, a direct memory access (DMA) circuit 924, and a cache coherent interconnect for accelerators (CCIX) interface 926.
  • PCIe peripheral component interconnect express
  • DMA direct memory access
  • CCIX cache coherent interconnect for accelerators
  • the PCIe interface 922 may be used to exchange data between the PS 930 and one or more other devices or chips via the transceiver blocks 850 according to a PCI protocol.
  • the CCIX interface 926 may be used to exchange data between the PS 930 and one or more other devices or chips via the transceiver blocks 850 according to a CCIX protocol.
  • the PS 930 may provide dedicated data processing capabilities for the device 900, and is shown to include an application processing unit (APU) 932, a real-time processing unit (RPU) 934, cache memory 936, and a system-on-a-chip (SoC) interface 938. Although not shown for simplicity, the PS 930 may also include peripherals for communication standards (such as Ethernet and USB 2.0 interfaces) and various controllers (such as SPI, I2C, UART, and CAN-FD controllers).
  • the APU 932 and the RPU 934 may each include one or more processing cores (such as CPUs) that can provide dedicated scalar processing capabilities for the device 900.
  • the PS 930 may be selectively connected to other subsystems of the device 900 by the programmable
  • the APU 932 may include a multi-core ARM processor that supports hardware virtualization, and may have a built-in interrupt controller and snoop control unit.
  • the interrupt controller may support virtual interrupts, and the snoop control unit may be used maintain coherency between one or more caches used and/or shared by APU 932 and RPU 934.
  • the APU 932 may communicate with other components of the PS 930 using an AXI coherent extension (ACE) port, and may communicate with the PL 910 using an accelerator coherency port (ACP).
  • ACE AXI coherent extension
  • ACP accelerator coherency port
  • the RPU 934 may include a multi-core ARM processor that supports real-time data processing, may include tightly coupled memory (TCM) interface for real-time single cycle access, and may have a dedicated interrupt controller and floating point unit.
  • the RPU 934 may communicate with other components of the PS 930 and/or with the PL 910 using AXI ports.
  • the cache memory 936 may be any suitable high-speed cache that allows for shared access by the APU 932 and the RPU 934.
  • the SoC interface 938 may provide connectivity between various resources of the PS 930 and the NoC interconnect system 820.
  • the PMC 940 may include security circuitry 942, booting and reconfiguration circuitry 944, analog circuitry 946, and the root monitor 890 of FIG. 8.
  • the security circuitry 942 may provide data encryption/decryption capabilities and other security features.
  • the booting and reconfiguration circuitry 944 may provide a multi-stage boot process that supports both a non-secure and a secure boot.
  • the analog circuitry 946 may include any suitable analog circuit components.
  • the PMC 940 may include test and debugging resources (such as JTAG circuitry), external flash memory interfaces, and other components or circuits. In some implementations, the PMC 940 may allow portions of the PL 910 to be reconfigured using a partial reconfiguration operation.
  • a new configuration bitstream for a portion of the PL 910 can be loaded from the PS 930 via either a primary or secondary boot interface (such as PCIe or Ethernet), and then stored in configuration registers associated with the portions of the PL 910 to be reconfigured.
  • a primary or secondary boot interface such as PCIe or Ethernet
  • the ability to allow for partial reconfiguration of one or more portions of the PL 910 may allow a user to more quickly reconfigure the device 900 to reflect changes or updates to the user-specified circuit design (such as compared with other programmable devices).
  • FIG. 10 shows a block diagram of an example programmable fabric 1000 in accordance with some implementations.
  • the configuration in accordance with some implementations.
  • programmable fabric 1000 may be the PL 810 of FIG. 8, the PL 910 of FIG. 9, or both.
  • the programmable fabric 1000 is shown to include a plurality of different programmable circuit blocks or tiles that can be arranged in columns (or rows).
  • the programmable circuit blocks may include (but are not limited to) programmable interconnect elements (INT) 1010, configurable logic elements (CLEs) 1020, DSPs 1030, and block RAMs (BRAMs) 1040 arranged in a columnar architecture.
  • programmable interconnect elements INT
  • CLEs configurable logic elements
  • BRAMs block RAMs
  • the programmable fabric 1000 is shown to include eleven columns of programmable interconnect elements 1010, five columns of CLEs 1020, two columns of DSPs 1030, and two columns of BRAM 1040.
  • INT programmable interconnect elements
  • CLEs configurable logic elements
  • BRAMs block RAMs
  • the programmable fabric 1000 may include other numbers of columns of programmable interconnect elements 1010, CLEs 1020, DSPs 1030, and BRAMs 31040.
  • the programmable fabric 1000 may also include a number of other subsystems or components not shown in FIG. 10 for simplicity (such as processing cores, programmable interconnect structures, and the like).
  • the programmable interconnect elements 1010, the CLEs 1020, the DSPs 1030, and the BRAM 1040 may be implemented as tiles that can be repeated across the programmable fabric 1000. Each of the tiles may include at least one programmable interconnect element 1010 that provides local signal
  • the programmable interconnect elements 1010 may collectively form at least a portion of the programmable interconnect fabric (or other suitable block-level and/or device-level signal routing structure).
  • the programmable fabric 1000 may include a columnar hard block 1050 that extends vertically across the height of the programmable fabric 1000.
  • the hard block 1050 may include a number of hard wired circuits such as, for example, USB controllers, Ethernet MACs, multi-rate (MR) Ethernet MACs, PCIe controllers, CCIX controllers, and/or other suitable circuits or components that implement the Physical Layer, the Data Link Layer, and the Transaction Layer of the PCIe protocol.
  • the hard block 1050 may be one implementation of the connectivity fabric described above with respect to FIG. 8.
  • FIG. 1 1 shows a functional block diagram of a monitoring system 1 100, in accordance with some implementations.
  • the monitoring system 1 100 which may be implemented in the programmable device 800 of FIG. 8, is shown to include a root monitor 1 1 10, a plurality of satellite monitors SAT1-SAT15, a plurality of supply voltage sensors SV1-SV4, a plurality of temperature sensors T5-T15, and a plurality of selected circuits CKT5-CKT 15.
  • the root monitor 1 10 which may be one implementation of the root monitor 890 of FIG. 8, is coupled to the NoC interconnect system 820 and the one or more analog channels 821 .
  • the root monitor 1 1 10 may include a bandgap voltage generator (not shown for simplicity) to generate the temperature-independent reference voltage VREF.
  • the satellite monitors SAT1-SAT15 may be distributed across the device 800 and arranged such that each of the satellite monitors SAT1-SAT15 is positioned in a vicinity of a corresponding one of the sensors SV1-SV4 and T5- T15.
  • the satellite monitors SAT1- SAT4 are coupled to respective supply voltage sensors SV1-SV4 via local signal wires
  • the satellite monitors SAT5-SAT15 are coupled to respective temperature sensors T5-T 15 via local signal wires.
  • analog signals generated by the supply voltage sensors SV1-SV4 may be provided to respective satellite monitors SAT1-SAT4 by local signal wires
  • analog signals generated by the temperature sensors T5-T15 may be provided to respective satellite monitors SAT5-SAT 15 by local signal wires.
  • analog signals generated by each of the sensors SV1-SV4 and T5-T15 may be locally converted into digital data using a nearby one of the satellite monitors SAT1-STA15, expensive metal-layer routing resources are not needed to implement the monitoring system 1 100 within a programmable device (such as the programmable device 800 of FIG. 8).
  • the sensor SV1 may monitor the operating conditions of an associated supply voltage by generating analog signals indicative of the voltage level of the associated supply voltage.
  • the analog signals generated by the sensor SV1 do not need to be routed across the device 800 to the root monitor 1 1 10, but instead may be routed a relatively short distance to the satellite monitor SAT 1 via local signal wires.
  • the sensor T5 may monitor the operating conditions of an associated circuit CKT5 by generating analog signals indicative of the temperature of the associated circuit CKT5.
  • the analog signals generated by the sensor T5 do not need to be routed across the device 800 to the root monitor 1 1 10, but instead may be routed a relatively short distance to the satellite monitor SAT5 via local signal wires.
  • the temperature-independent reference voltage VREF may be distributed across the device 800 and made accessible to each of the satellite monitors SAT1- STA15 by the one or more analog channels 821 , and digital data may be selectively routed from each of the satellite monitors SAT1-STA15 to the root monitor 1 1 10 by the NoC interconnect system 820.
  • the one or more analog channels 821 may extend along corresponding portions of the NoC interconnect system 820. In other implementations, the one or more analog channels 821 may be separate from the NoC interconnect system 820.
  • FIG. 12 shows a block diagram of an example root monitor 1200, in accordance with some implementations.
  • the root monitor 500 which may be one implementation of the root monitor 890 of FIG. 8 or the root monitor 1 1 10 of FIG. 1 1 (or both), is shown to include a bandgap voltage generator 1210, a memory 1220, and a controller 1230.
  • the bandgap voltage generator 1210 which may be any suitable circuit or device that can generate a highly-accurate and temperature- independent reference voltage VREF, includes an output coupled to the one or more analog channels 821 .
  • the bandgap voltage generator 1210 may provide the temperature-independent reference voltage VREF as a differential voltage (such as including both a positive reference voltage and a negative reference voltage) to the one or more analog channels 821 .
  • the temperature-independent reference voltage VREF may be equal to 1 .25 volts, although other suitable voltages may be used as VREF.
  • the temperature- independent reference voltage VREF generated by the bandgap voltage generator 1210 may be distributed to each of the satellite monitors 892(1 )-892(19) located throughout the device 800 using the one or more analog channels 821 .
  • the satellite monitors 892(1 )-892(19) may selectively access the temperature- independent reference voltage VREF from the one or more analog channels 821 to charge their respective voltage stores and to periodically calibrate their ADCs, for example, to compensate for analog-to-digital conversion errors associated with using the relatively imprecise local reference voltage for sampling analog signals (rather than using the highly-accurate and temperature-independent reference voltage VREF).
  • the memory 1220 includes a data input coupled to the NoC interconnect system 820, a control input coupled to the controller 1230, a data output coupled to the controller 1230, and one or more output ports from which data stored therein can be accessed by a user via one or more of a JTAG interface, a multiplexed input/output (MIO) block, or an AXI interface.
  • the memory 1220 may include a number of status registers 1221 and a number of alarm register 1222.
  • the status registers 1221 may store digital data indicative of operating conditions of the selected circuits provided throughout the device 800, and the alarm registers 1222 may store a plurality of reference values that define a number of specified operating ranges.
  • the status registers 1221 may be loaded with digital data routed from the satellite monitors 892(1 )-892(19) to the root monitor 1200 via the NoC interconnect system 820, and the alarms registers 1222 may be loaded with the reference values during configuration (or re-configuration) of the programmable device 800.
  • the controller 1230 may control various operations of the root monitor 1200, may analyze the digital data received from the satellite monitors 892(1 )-892(19) to determine whether any of the selected circuits are not operating within their specified operating ranges, and may generate result data that can be accessed by the user. In some implementations, the controller 1230 may determine whether a selected circuit is operating within a specified operating range by comparing the measured operating conditions stored in the status registers 1221 with
  • the controller 1230 may generate an alarm.
  • the alarm may cause the selected circuit to be disabled or powered-down, for example, until the operating conditions of the selected circuit are within its specified operating range.
  • the alarm may cause the programmable device 800 to be powered-down or to operate at a reduced power level, for example, until the operating conditions of the selected circuit are within the specified operating range.
  • a specified voltage range may include a minimum voltage value and a maximum voltage value.
  • the controller 1230 may compare the measured voltage of the selected circuit with the minimum and maximum voltage values stored in the alarms registers 1222, and may generate one or more alarms based on the comparison. For example, if the measured voltage is between the minimum and maximum voltage values, the controller 1230 may indicate that the selected circuit is operating within its specified voltage range. Conversely, if the measured voltage is less than the minimum voltage value or greater than the maximum voltage value, the controller 1230 may generate an alarm to indicate that the selected circuit is not operating within its specified voltage range.
  • Other specified operating ranges stored in the alarms registers 1222 may include a reference value that defines an upper operational limit.
  • a specified temperature range for a selected circuit may be defined by a reference temperature value.
  • the controller 1230 may compare the measured temperature of the selected circuit with the reference temperature value stored in the alarms registers 1222, and may generate one or more alarms based on the comparison. For example, if the measured temperature is less than (or equal to) the reference temperature value, the controller 1230 may indicate that the selected circuit is operating within its specified temperature range. Conversely, if the measured temperature is greater than the reference temperature value, the controller 1230 may generate an alarm to indicate that the selected circuit is too hot or overheated.
  • the controller 1230 may be configured to generate control signals CTRL[1 :19] that can be used by respective satellite monitors 892(1 )-892( 19) to operate in either a calibration mode or a monitoring mode.
  • a respective satellite monitor 892 may access the temperature-independent reference voltage VREF from the one or more analog channels 821 , and may use VREF to generate a correction factor indicative of analog-to-digital conversion errors resulting from inaccuracies in the relatively imprecise local reference voltage (such as described with respect to FIG. 13).
  • the respective satellite monitor 892 may convert analog signals generated by one or more sensors (S) into digital codes, and may correct the digital codes based on the correction factor (such as described with respect to FIG. 13).
  • the controller 1230 may selectively assert the control signals CTRL[1 :19] based on a timing schedule such that only one of the satellite monitors 892(1 )-892(19) may access VREF from the one or more analog channels 821 at the same time. In this manner, the root monitor 1200 may prevent dips in the temperature-independent reference voltage VREF caused by more than one of the satellite monitors 892(1 )-892( 19) accessing the temperature-independent reference voltage VREF at the same time.
  • the timing schedule which may be stored in the memory 1220, may also include a schedule for periodically calibrating each of the satellite monitors 892(1 )- 892(19) using VREF, for example, to ensure that any periodic drifts in the local reference voltages used by and/or stored in the each of the satellite monitors 892(1 )-892( 19) are compensated by corresponding updates to the correction factors.
  • the controller 1230 may sequentially assert the control signals CTRL[1 :19] every N milliseconds so that each of the satellite monitors 892(1 )-892(19) performs a calibration operation every N milliseconds, where N may be any suitable number.
  • the timing schedule may also include a schedule for periodically charging the voltage store within each of the satellite monitors 192(1 )— 192(19) using VREF, for example, to maintain the local reference voltage held by the voltage store within a range (such as within a value of the temperature-independent reference voltage).
  • FIG. 13 shows a block diagram of an example satellite monitor 1300, in accordance with some implementations.
  • the satellite monitor 1300 which may be one example of any number of the satellite monitors 892(1 )-892( 19) of FIG. 8 or the satellite monitors SAT1-SAT15 of FIG. 1 1 (or both), is shown to include an ADC 1310, a memory 1320, a local voltage source 1330, a calibration circuit 1340, a correction circuit 1345, and a switch SW.
  • the switch SW includes a first input terminal coupled to receive the temperature-independent reference voltage VREF from the one or more analog channels 821 , a second input terminal coupled to receive the analog signals generated by one or more associated sensors 20, a control terminal coupled to receive a corresponding control signal CTRL generated by the root monitor 1200, and an output terminal coupled to an input terminal of the ADC 1310.
  • the sensors 20 may include (but are not limited to) temperature sensors 21 , supply voltage sensors 22, and external sensors 23.
  • the ADC 1310 includes an output terminal coupled to the memory 1320, and includes one or more reference terminals coupled to the local voltage source 1330.
  • the ADC 1310 may be (or may include) any suitable ADC that can convert analog signals generated by one or more of the sensors 20 into digital data or digital codes.
  • the ADC 1310 may utilize a scaled architecture to digitize analog sensing data provided by the sensors 20.
  • the memory 1320 which may be any suitable storage device, includes an input coupled to the output terminal of the ADC 1310, and includes an output coupled to the NoC interconnect system 820.
  • the memory 1320 may store digital data generated by the ADC 1310 in response to analog signals provided by one or more of the sensors 20, and may provide the digital data to the NoC interconnect system 820 for routing to the root monitor 1200 of FIG. 12.
  • the memory 1320 may be or may include a plurality of registers each for storing digital data indicative of the operating conditions of a
  • the satellite monitor 1300 may receive analog signals indicative of operating conditions of a corresponding one of the selected circuits from the sensors 20, may convert the analog signals into digital data, and may provide digital data indicative of the operating conditions of the selected circuit to the root monitor 1200 via the NoC interconnect system 820.
  • the local voltage source 1330 may be any suitable relatively small or area- efficient voltage source that can generate a local reference voltage VREF LOCAL suitable for use by the ADC 1310 (and that does not need to be trimmed during manufacturing).
  • the local voltage source 1330 may be constructed using as few as 10 transistors, and occupies significantly less circuit area than the bandgap voltage generator 1210 of FIG. 12. In some implementations, the local voltage source 1330 may occupy at least an order of magnitude less circuit area than the bandgap voltage generator 1210 of FIG. 12). For example, in one or more implementations, the circuit area occupied by the local voltage source may be on the order of tens of square microns.
  • the local reference voltage VREF LOCAL may be relatively imprecise compared to the temperature-independent reference voltage VREF generated by the bandgap voltage generator 1210, and may cause errors in the digital codes generated by the ADC 1310.
  • the local reference voltage provided by the local voltage source 1330 may be at least one order of magnitude less accurate than the temperature-independent reference voltage generated by the bandgap voltage generator 1210.
  • the local reference voltage may have an accuracy of approximately 5% within a target voltage, while the temperature-independent reference voltage may have an accuracy of approximately 0.5% within the target voltage.
  • the calibration circuit 1340 may include an input coupled to receive digital codes from the output terminal of the ADC 1310, an output to provide the correction factor to the correction circuit 1345, and a control terminal to receive the
  • the correction circuit 1345 which may be coupled between the ADC 1310 and the memory 1320, includes a terminal to receive the correction factor provided by the calibration circuit 1340.
  • the calibration circuit 1340 may be configured to generate the correction factor to compensate for errors in the digital codes generated by the ADC 1310, and the correction circuit 1345 may be configured to correct the digital codes generated by the ADC 1310 based on the correction factor.
  • an asserted state of the control signal CTRL may cause the switch SW to provide the temperature- independent reference voltage VREF as an input signal to the ADC 1310, and may also enable the calibration circuit 1340.
  • the ADC 1310 may sample the
  • the calibration circuit 1340 may generate the correction factor based on a difference between the reference code generated by the ADC 1310 and a predetermined digital code indicative of known value of VREF.
  • a de-asserted state of the control signal CTRL may cause the switch SW to provide analog signals from the sensors 20 as input signals to the ADC 1310, and may isolate the satellite monitor 1300 from VREF and/or the NoC interconnect system 820.
  • the ADC 1310 may sample the analog signals provided by the sensors 20 and generate digital codes.
  • the correction circuit 1345 may use the correction factor to correct the digital codes, for example, by adjusting the digital codes based on the correction factor.
  • FIG. 14 is an illustrative flow chart depicting an example operation 1400 for monitoring operating conditions of a plurality of circuits distributed in various locations across a programmable device, in accordance with some
  • the example operation 1400 is described below with respect to the programmable device 800 of FIG. 8, the monitoring system 1 100 of FIG. 1 1 , the root monitor 1200 of FIG. 12, and the satellite monitor 1300 of FIG. 13 for illustrative purposes only. It is to be understood that the example operation 1400 may be performed by other programmable devices disclosed herein and/or by other suitable devices.
  • the operation 1400 may begin at block 1401 by generating an analog signal indicative of the operating conditions of each of the plurality of circuits using a corresponding one of a plurality of sensors distributed in the various locations across the programmable device.
  • each of the number of sensors 20 may be located in the vicinity of the associated circuit.
  • the sensor 20 may be (or may include) at least one of a temperature sensor 21 , a supply voltage sensor 22, or an external sensor 23.
  • the root monitor 890 may generate a trimmed and temperature- independent reference voltage VREF, for example, using the bandgap circuit 1 21 2 of FIG. 12.
  • the operation 1400 may proceed at block 1402 by providing each of the analog signals to a corresponding one of a plurality of satellite monitors distributed in the various locations across the programmable device.
  • the analog signals generated by the sensors 20 may be provided to corresponding satellite monitors 892(1 )-892(19) using relatively short local signal wires, for example, in contrast to conventional programmable devices in which analog signals indicative of operating conditions of various circuits are routed across the device and provided to a central monitor using a metal-layer signal routing structure.
  • the operation 1400 may proceed at block 1403 by generating, in each of the plurality of satellite monitors 892(1 )— 892(19), a local reference voltage using a local voltage source 1330 (e.g., based on the temperature-independent reference voltage).
  • the local voltage source 1330 may be relatively small and“area-efficient” compared to the bandgap voltage generator 1210 provided in the root monitor 1200.
  • the local voltage source 1330 may include fewer than a dozen transistors, and may consume at least one order of magnitude less circuit area than the bandgap voltage generator 1210. In one or more
  • the circuit area occupied by the local voltage source 1330 may be on the order of tens of square microns, while the circuit area occupied by the bandgap voltage generator 1210 may be on the order of hundreds of square microns (or even a thousand square microns).
  • the local reference voltage may be relatively imprecise compared to the temperature-independent reference voltage generated by the bandgap voltage generator 1210.
  • the local reference voltage provided by and/or stored in the local voltage source 1330 may be at least one order of magnitude less accurate than the temperature-independent reference voltage generated by the bandgap voltage generator 1210. In one or more
  • the local reference voltage may have an accuracy of
  • the temperature-independent reference voltage may have an accuracy of approximately 0.5% within the target voltage.
  • the operation 1400 may proceed at block 1404 by converting, in each of the plurality of satellite monitors 892(1 )— 892(19), a corresponding analog signal into a digital code using an analog-to-digital converter (ADC) based on the local reference voltage.
  • ADC analog-to-digital converter
  • the ADC circuit 1310 provided within each of the satellite monitors 892(1 )-892(19) may convert the analog signals into digital data that can be stored in the memory 1320 of each of the satellite monitors 892(1 )- 892(19).
  • the memory 1320 may selectively provide the stored digital data to the interconnect system 820 for routing to the root monitor 890.
  • the operation 1400 may proceed at block 1405 by distributing a
  • the temperature-independent reference voltage may be distributed to each of the plurality of satellite monitors 892(1 )-892(19) using one or more analog channels 821 spanning the programmable fabric.
  • the operation 1400 may proceed at block 1406 by correcting the digital code generated by the ADC 1310 within each of the plurality of satellite monitors 892(1 )- 892(19) based at least in part on the distributed temperature-independent reference voltage.
  • the digital codes may be adjusted based on a correction factor indicative of analog-to-digital conversions errors resulting from inaccuracies in the local reference voltage.
  • the operation 1400 may proceed at block 1407 by selectively routing the corrected digital codes from the plurality of satellite monitors 892(1 )-892( 19) to the root monitor 890.
  • the corrected digital codes may be selectively routed from the plurality of satellite monitors 892(1 )-892(19) to the root monitor 890 using the NoC interconnect system 820.
  • each of the satellite monitors 892(1 )-892( 19) may provide corrected digital codes to the NoC interconnect system 820 in response to a signal (such as a trigger signal) generated by the root monitor 890, for example, to schedule or prioritize the delivery of digital data from the satellite monitors 892(1 )-892(19) to the root monitor 890.
  • a signal such as a trigger signal
  • the satellite monitors 892(1 )-892(19) may provide digital data to the NoC interconnect system 820 without prompting and/or without control by the root monitor 890.
  • FIG. 15 is an illustrative flow chart depicting an example operation 1500 for correcting the digital code generated by an ADC provided within each of the satellite monitors.
  • the example operation 1500 is described below with respect to the programmable device 800 of FIG. 8, the monitoring system 1 100 of FIG. 1 1 , the root monitor 1200 of FIG. 12, and the satellite monitor 1300 of FIG. 13 for illustrative purposes only. It is to be understood that the example operation 1500 may be performed by other programmable devices disclosed herein and/or by other suitable devices. In some implementations, the example operation may be an example of the process 1408 of the operation 1400 described above with respect to FIG. 14.
  • the operation 1500 may begin at block 1501 by providing the temperature- independent reference voltage as an input signal to the ADC 1310.
  • the operation 1500 may proceed at block 1502 by converting the temperature-independent reference voltage into a reference code using the ADC 1310.
  • the operation 1500 may proceed at block 1503 by generating a correction factor based on differences between the reference code and a predetermined digital code indicative of the temperature-independent reference voltage.
  • the operation 1500 may proceed at block 1504 by adjusting the digital code based on the correction factor.
  • FIG. 16 shows a block diagram of an example satellite monitor 1600, in accordance with some implementations.
  • the satellite monitor 1600 which may be one example of any number of the satellite monitors 892(1 )-892( 19) of FIG. 8 or the satellite monitors SAT1-SAT15 of FIG. 4 (or both), is shown to include an ADC 1610, a memory 1620, a voltage store 1630, a calibration circuit 1640, a correction circuit 1645, a first switch SW1 , and a second switch SW2.
  • the first switch SW1 includes a first input terminal coupled to receive the temperature-independent reference voltage VREF from the one or more analog channels 821 , a second input terminal coupled to receive the analog signals generated by one or more
  • the second switch SW2 includes an input terminal coupled to receive the temperature-independent reference voltage from the one or more analog channels, a control terminal coupled to receive a corresponding one of the second control signals CTRL2, and an output terminal coupled to the voltage store 1630.
  • the sensors 20 may include (but are not limited to) temperature sensors 21 , supply voltage sensors 22, and external sensors 23.
  • the ADC 1610 includes an output terminal coupled to the memory 1620, and includes one or more reference terminals coupled to the voltage store 1630.
  • the ADC 1610 may be (or may include) any suitable ADC that can convert analog signals generated by one or more of the sensors 20 into digital data or digital codes.
  • the ADC 1610 may utilize a scaled architecture to digitize analog sensing data provided by the sensors 20.
  • the memory 1620 which may be any suitable storage device, includes an input coupled to the output terminal of the ADC 1610, and includes an output coupled to the NoC interconnect system 820.
  • the memory 1620 may store digital data generated by the ADC 1610 in response to analog signals provided by one or more of the sensors 20, and may provide the digital data to the NoC interconnect system 820 for routing to the root monitor 1200 of FIG. 12.
  • the memory 1620 may be or may include a plurality of registers each for storing digital data indicative of the operating conditions of a corresponding one of a plurality of circuits selected for monitoring.
  • the satellite monitor 1600 may receive analog signals indicative of operating conditions of a corresponding one of the selected circuits from the sensors 20, may convert the analog signals into digital data, and may provide digital data indicative of the operating conditions of the selected circuit to the root monitor 1200 via the NoC interconnect system 820.
  • the voltage store 1630 may be any suitable device or component that can store a local reference voltage VREF LOCAL suitable for use by the ADC 1610.
  • the voltage store 1630 may be a capacitor, for example, as depicted in FIG. 16. More specifically, in some implementations, the voltage store 1630 may be implemented as capacitor C1 , and the second switch SW2 may be implemented as a CMOS transistor M1 .
  • the capacitor C1 is coupled between the transistor M1 (operating as the second switch SW2) and the reference terminals of the ADC 1610, and may occupy significantly less circuit area than the bandgap voltage generator 1210 of FIG. 12. In addition, the capacitor does not need to be trimmed during manufacture, for example, as does an accurate voltage reference such as the bandgap voltage generator 1210.
  • the voltage store 1630 may occupy at least an order of magnitude less circuit area than the bandgap voltage generator 1210 of FIG. 12.
  • the circuit area occupied by the local voltage store 1630 may be on the order of tens of square microns.
  • the local reference voltage VREF LOCAL may be relatively imprecise compared to the temperature-independent reference voltage VREF generated by the bandgap voltage generator 1210, and may cause errors in the digital codes generated by the ADC 1610.
  • the local reference voltage provided by the local voltage store 1630 may be at least one order of magnitude less accurate than the temperature-independent reference voltage generated by the bandgap voltage generator 1210.
  • the local reference voltage may have an accuracy of approximately 5% within a target voltage, while the
  • temperature-independent reference voltage may have an accuracy of
  • the calibration circuit 1640 may include an input coupled to receive digital codes from the output terminal of the ADC 1610, an output to provide the correction factor to the correction circuit 1645, and a control terminal to receive the corresponding first control signal CTRL1 from the root monitor 1200.
  • the correction circuit 1645 which may be coupled between the ADC 1610 and the memory 1620, includes a terminal to receive the correction factor provided by the calibration circuit 1640.
  • the calibration circuit 1640 may be configured to generate the correction factor to compensate for errors in the digital codes generated by the ADC 1610, and the correction circuit 1645 may be configured to correct the digital codes generated by the ADC 1610 based on the correction factor.
  • the first control signal CTRL1 may be asserted (e.g., to logic high), and the second control signal CTRL2 may be asserted (e.g., to logic high).
  • the asserted state of the first control signal CTRL1 may cause the first switch SW1 to provide the temperature-independent reference voltage VREF as an input signal to the ADC 1610, and may also enable the calibration circuit 1640.
  • the asserted state of the second control signal CTRL2 may open the second switch SW2 and couple the voltage store 1630 to the one or more analog channels 821 , thereby allowing the voltage store 1630 to be charged to a value approximately equal to the temperature-independent reference voltage (such that the stored charge may be used by the ADC 1610 as the local reference voltage VREF LOCAL).
  • the conductive states of the switches SW1 and SW2 may cause a disturbance (such as a dip) in the temperature-independent reference voltage, for example, caused by V REF being coupled to the input terminal of the ADC 1610 and to the voltage store 1630.
  • the second control signal CTRL2 may be de-asserted (e.g., to logic low).
  • the de-asserted state of the second control signal CTRL2 may close the second switch SW2 and prevent the voltage store 1630 from accessing the temperature-independent reference voltage from the one or more analog channels 821 .
  • De-assertion of the second control signal CTRL2 may also cause a disturbance (such as a dip) in the temperature-independent reference voltage V REF.
  • the first control signal CTRL1 may remain in the asserted state until disturbances in the temperature-independent reference voltage VREF settle.
  • the first control signal CTRL1 may be de-asserted (e.g., to logic low), and the ADC 1610 may sample the temperature-independent reference voltage VREF to generate a reference code.
  • the calibration circuit 1640 may generate the correction factor based on a difference between the reference code generated by the ADC 1610 and a predetermined digital code indicative of known value of VREF.
  • the correction factor may be provided to (and stored in) the correction circuit 1645.
  • the first control signal CTRL1 may remain in the de-asserted state, thereby allowing the first switch SW1 to provide analog signals generated by the sensors 20 as input signals to the ADC 1610 (and may also disable the calibration circuit 1640).
  • the ADC 1610 may sample the analog signals provided by the sensors 20 and generate digital codes indicative of the sampled analog signals.
  • the correction circuit 1645 may use the correction factor generated during the calibration operation to correct the digital codes, for example, by adjusting the digital codes based on the correction factor. In this manner, the satellite monitor 1600 may compensate for analog-to-digital conversion errors resulting from inaccuracies in the relatively imprecise local reference voltage VREF_LOCAL.
  • the calibration operation may be performed periodically (such as every N milliseconds, where N is any suitable number greater than zero) to maintain a minimum voltage level stored by the voltage store 1630 (as VREF LOCAL) and to ensure that the satellite monitor 1600 remains properly calibrated.
  • Example 1 A programmable device, comprising: a plurality of configurable logic resources; a root monitor including circuity configured to generate a reference voltage; a number of sensors distributed in various locations across the
  • each of the sensors configured to measure operating conditions of an associated circuit at a corresponding one of the various locations; a plurality of satellite monitors distributed in the various locations across the programmable device, each of the satellite monitors coupled to one or more associated sensors located in a vicinity of the corresponding satellite monitor; and an interconnect system coupled to the configurable logic resources, to the root monitor, and to each of the plurality of satellite monitors, wherein the interconnect system is configured to: distribute the reference voltage from the root monitor to each of the plurality of satellite monitors; and selectively route digital data from each of the plurality of satellite monitors to the root monitor, wherein the digital data is indicative of the measured operating conditions.
  • Example 2 The programmable device of Example 1 , wherein the operating conditions include at least one of a temperature or a voltage level.
  • Example 3 The programmable device of Example 1 , wherein the root monitor comprises a bandgap circuit configured to compensate the reference voltage for temperature variations.
  • Example 4 The programmable device of Example 1 , wherein each of the satellite monitors comprises: an analog-to-digital converter (ADC) including an input to receive analog signals indicative of operating conditions measured by the one or more associated sensors, an output to provide the digital data to the interconnect system, and a reference terminal to receive a local reference voltage.
  • ADC analog-to-digital converter
  • Example 5 The programmable device of Example 4, wherein the local reference voltage is based at least in part on the reference voltage distributed by the interconnect system.
  • Example 6 The programmable device of Example 4, wherein each of the satellite monitors further comprises: a memory including an input coupled to the output of the ADC, including an output coupled to the interconnect system, and configured to store the digital data provided by the ADC.
  • Example 7 The programmable device of Example 4, wherein each of the satellite monitors further comprises: a switch configured to selectively couple the reference voltage distributed by the interconnect system to the satellite monitor based on a control signal generated by the root monitor.
  • Example 8 The programmable device of Example 7, wherein the control signals are configured to couple the reference voltage distributed by the
  • Example 9 The programmable device of Example 1 , wherein at least some of the plurality of satellite monitors are integrated within the interconnect system.
  • Example 10 The programmable device of Example 1 , wherein the interconnect system further comprises: one or more analog channels configured to distribute the reference voltage from the root monitor to each of the plurality of satellite monitors; and one or more digital channels configured to selectively route the digital data from the satellite monitors to the root monitor as individually addressable data packets.
  • Example 1 1 The programmable device of Example 1 , wherein the root monitor further comprises: a memory configured to store the digital data received from each of the plurality of satellite monitors; and a controller configured to determine whether the measured operating conditions of at least one of the associated circuits are within a range.
  • Example 12 A system for monitoring a number of operating conditions of a programmable device, the system comprising: a root monitor including circuity configured to generate a reference voltage; a plurality of sensors distributed across the programmable device, each of the sensors configured to generate analog signals indicative of operating conditions of an associated circuit; a plurality of satellite monitors distributed across the programmable device, each of the satellite monitors configured to convert the analog signals generated by one or more corresponding sensors into digital data; and an interconnect system coupled to at least the root monitor and each of the plurality of satellite monitors, the interconnect system comprising: one or more analog channels configured to distribute the reference voltage from the root monitor to each of the plurality of satellite monitors; and one or more digital channels configured to selectively route the digital data from each of the plurality of satellite monitors to the root monitor.
  • Example 13 The system of Example 12, wherein the operating conditions include at least one of a temperature or a voltage level.
  • Example 14 The system of Example 12, wherein each of the satellite monitors comprises: an analog-to-digital converter (ADC) configured to convert the analog signals generated by the one or more associated sensors into the digital data.
  • ADC analog-to-digital converter
  • Example 15 The system of Example 14, wherein each of the satellite monitors further comprises: a switch configured to selectively couple the reference voltage distributed by the interconnect system to the satellite monitor based on a control signal generated by the root monitor.
  • Example 16 The system of Example 15, wherein the control signals are configured to couple the reference voltage distributed by the interconnect system to only one of the satellite monitors at the same time.
  • Example 17 A method of monitoring a number of operating conditions of a programmable device, the method comprising: generating a reference voltage using a voltage generator associated with a root monitor provided within the programmable device; distributing the reference voltage to each of a plurality of satellite monitors using one or more analog channels of an interconnect system integrated within the programmable device; generating, using each of a number of sensors, analog signals indicative of operating conditions of an associated circuit; providing the analog signals generated by the number of sensors to corresponding ones of the plurality of satellite monitors; converting the analog signals into digital data using the plurality of satellite monitors; and selectively routing the digital data from the plurality of satellite monitors to the root monitor using one or more digital channels of the interconnect system.
  • Example 18 The method of Example 17, wherein the operating conditions include at least one of a temperature or a voltage level.
  • Example 19 The method of Example 17, wherein distributing the reference voltage further comprises: selectively coupling each of the plurality of satellite monitors to the interconnect system based on a corresponding control signal generated by the root monitor.
  • Example 20 The method of Example 19, wherein the control signals are configured to couple the reference voltage distributed by the interconnect system to only one of the satellite monitors at the same time.
  • Example 21 A programmable device, comprising: programmable logic including a plurality of configurable logic resources; a root monitor including a bandgap voltage generator configured to generate a temperature-independent reference voltage; a plurality of sensors distributed in various locations across the programmable device, each of the sensors configured to generate analog signals indicative of measured operating conditions of one or more associated circuits in a vicinity of a corresponding one of the various locations; and a plurality of satellite monitors distributed across the programmable device in the various locations, each of the satellite monitors coupled to one or more associated sensors via one or more local signal lines and comprising: a relatively small local voltage source configured to generate a local reference voltage; an analog-to-digital converter (ADC) including a reference terminal to receive the local reference voltage and configured to convert the analog signals generated by the one or more associated sensors into digital codes indicative of the measured operating conditions; a calibration circuit configured to generate a correction factor indicative of errors in the digital codes; and a correction circuit configured to correct the digital codes based on the correction factor.
  • ADC
  • Example 22 The programmable device of Example 21 , wherein the local voltage source consists of fewer than a dozen transistors, and consumes at least one order of magnitude less circuit area than the bandgap voltage generator.
  • Example 23 The programmable device of Example 21 , wherein the errors in the digital codes are associated with deviations of the local reference voltage from the temperature-independent reference voltage.
  • Example 24 The programmable device of Example 21 , wherein the correction factor is based on differences between a reference code generated by the ADC in response to sampling the temperature-independent reference voltage and a predetermined digital code indicative of the temperature-independent reference voltage.
  • Example 25 The programmable device of Example 21 , further comprising: a network-on-chip (NoC) interconnect system spanning the programmable logic and configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor.
  • NoC network-on-chip
  • Example 26 The programmable device of Example 25, wherein the root monitor further comprises: a memory configured to store the digital data received from the plurality of satellite monitors via the NoC interconnect system; and a controller configured to determine whether the measured operating conditions embodied by the digital data are within a range.
  • Example 27 The programmable device of Example 25, further comprising: one or more analog channels configured to distribute the temperature-independent reference voltage from the root monitor to each of the plurality of satellite monitors.
  • Example 28 The programmable device of Example 27, wherein the NoC interconnect system comprises the one or more analog channels.
  • Example 29 The programmable device of Example 27, wherein each of the satellite monitors further comprises: a switch including a first input terminal coupled to receive the temperature-independent reference voltage from the one or more analog channels, a second input terminal coupled to receive the analog signals generated by the one or more associated sensors, a control terminal coupled to receive a control signal, and an output terminal coupled to an input terminal of the ADC within the satellite monitor.
  • a switch including a first input terminal coupled to receive the temperature-independent reference voltage from the one or more analog channels, a second input terminal coupled to receive the analog signals generated by the one or more associated sensors, a control terminal coupled to receive a control signal, and an output terminal coupled to an input terminal of the ADC within the satellite monitor.
  • Example 30 The programmable device of Example 29, wherein: during a calibration operation, the switch provides the temperature-independent reference voltage as an input signal to the ADC; and during a monitoring operation, the switch provides the analog signals from the sensors as input signals to the ADC.
  • Example 31 The programmable device of Example 30, wherein: during the calibration operation, the ADC samples the temperature-independent reference voltage to generate a reference code; and during the monitoring operation, the ADC samples the analog signals from the one or more associated sensors to generate the digital codes.
  • Example 32 The programmable device of Example 31 , wherein the calibration circuit is configured to generate the correction factor based on a difference between the reference code generated by the ADC and a predetermined digital code indicative of the temperature-independent reference voltage.
  • Example 33 The programmable device of Example 29, wherein the root monitor is configured to generate the control signals based at least in part on a timing schedule for calibrating the plurality of satellite monitors.
  • Example 34 The programmable device of Example 33, wherein the timing schedule is configured to sequentially enable calibration of each of the plurality of satellite monitors by providing the temperature-independent reference voltage to only one of the satellite monitors at a time.
  • Example 35 A method of monitoring operating conditions of a plurality of circuits distributed in various locations across a programmable device, the method comprising: generating an analog signal indicative of the operating conditions of each of the plurality of circuits using a corresponding one of a plurality of sensors distributed in the various locations across the programmable device; providing each of the analog signals to a corresponding one of a plurality of satellite monitors distributed in the various locations across the programmable device; generating, in each of the plurality of satellite monitors, a local reference voltage using a relatively small local voltage source; converting, in each of the plurality of satellite monitors, a corresponding one of the plurality of analog signals into a digital code using an analog-to-digital converter (ADC) based on the local reference voltage; distributing a temperature-independent reference voltage from a root monitor to each of the plurality of satellite monitors; correcting the digital code generated by the ADC within each of the plurality of satellite monitors based at least in part on the distributed temperature-independent reference voltage; and selective
  • Example 36 The method of Example 35, wherein the local voltage source consists of fewer than a dozen transistors, and consumes at least one order of magnitude less circuit area than the bandgap voltage generator.
  • Example 37 The method of Example 35, wherein: the corrected digital codes are selectively routed from the plurality of satellite monitors to the root monitor using a network-on-chip (NoC) interconnect system spanning the programmable device; and the temperature-independent reference voltage is distributed from the root monitor to the plurality of satellite monitors using one or more analog channels spanning the programmable device.
  • NoC network-on-chip
  • Example 38 The method of Example 35, wherein distributing the
  • temperature-independent reference voltage further comprises: sequentially enabling each of the plurality of satellite monitors to access the temperature- independent reference voltage based on a corresponding plurality of control signals generated by the root monitor.
  • Example 39 The method of Example 35, wherein the correcting comprises: providing the temperature-independent reference voltage as an input signal to the ADC; converting the temperature-independent reference voltage into a reference code using the ADC; generating a correction factor based on differences between the reference code and a predetermined digital code indicative of the temperature- independent reference voltage; and adjusting the digital code based on the correction factor.
  • Example 40 The method of Example 39, wherein the correction factor is configured to compensate for errors in the digital code associated with deviations of the local reference voltage from the temperature-independent reference voltage.
  • Example 41 A programmable device, comprising: programmable logic including a plurality of configurable logic resources; a root monitor including a bandgap voltage generator configured to generate a temperature-independent reference voltage; a plurality of sensors distributed in various locations across the programmable device, each of the sensors configured to generate analog signals indicative of measured operating conditions of one or more associated circuits in a vicinity of a corresponding one of the various locations; and a plurality of satellite monitors distributed across the programmable device in the various locations, each of the satellite monitors coupled to one or more associated sensors via one or more local signal lines and comprising: a voltage store configured to store a local reference voltage based on the temperature-independent reference voltage generated by the bandgap voltage generator; an analog-to-digital converter (ADC) including a reference terminal to receive the local reference voltage and configured to convert the analog signals
  • Example 42 The programmable device of Example 41 , wherein the local reference voltage is at least one order of magnitude less accurate than the temperature-independent reference voltage generated by the bandgap voltage generator.
  • Example 43 The programmable device of Example 41 , wherein the voltage store comprises a capacitor.
  • Example 44 The programmable device of Example 41 , wherein the errors in the digital codes are associated with deviations of the local reference voltage from the temperature-independent reference voltage.
  • Example 45 The programmable device of Example 41 , wherein the correction factor is based on differences between a reference code generated by the ADC in response to sampling the temperature-independent reference voltage and a predetermined digital code indicative of the temperature-independent reference voltage.
  • Example 46 The programmable device of Example 41 , further comprising: a network-on-chip (NoC) interconnect system spanning the programmable logic and configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor.
  • NoC network-on-chip
  • Example 47 The programmable device of Example 46, wherein the root monitor further comprises: a memory configured to store the digital data received from the plurality of satellite monitors via the NoC interconnect system; and a controller configured to determine whether the measured operating conditions embodied by the digital data are within a range.
  • Example 48 The programmable device of Example 46, further comprising: one or more analog channels configured to distribute the temperature-independent reference voltage from the root monitor to each of the plurality of satellite monitors.
  • Example 49 The programmable device of Example 48, wherein the NoC interconnect system comprises the one or more analog channels.
  • Example 50 The programmable device of Example 48, wherein each of the satellite monitors further comprises: a first switch including a first input terminal coupled to receive the temperature-independent reference voltage from the one or more analog channels, a second input terminal coupled to receive the analog signals generated by the one or more associated sensors, a control terminal coupled to receive a control signal, and an output terminal coupled to an input terminal of the ADC within the satellite monitor.
  • a first switch including a first input terminal coupled to receive the temperature-independent reference voltage from the one or more analog channels, a second input terminal coupled to receive the analog signals generated by the one or more associated sensors, a control terminal coupled to receive a control signal, and an output terminal coupled to an input terminal of the ADC within the satellite monitor.
  • Example 51 The programmable device of Example 50, wherein each of the satellite monitors further comprises: a second switch including an input terminal coupled to receive the temperature-independent reference voltage from the one or more analog channels, a control terminal coupled to receive the control signal, and an output terminal coupled to the voltage store.
  • a second switch including an input terminal coupled to receive the temperature-independent reference voltage from the one or more analog channels, a control terminal coupled to receive the control signal, and an output terminal coupled to the voltage store.
  • Example 52 The programmable device of Example 51 , wherein during a calibration operation: the first switch provides the temperature-independent reference voltage as an input signal to the ADC; the second switch charges the voltage store and then isolates the voltage store from the temperature-independent reference voltage; and the ADC samples the temperature-independent reference voltage to generate a reference code.
  • Example 53 The programmable device of Example 52, wherein during a monitoring operation: the first switch provides the analog signals from the sensors as input signals to the ADC; the second switch periodically provides the
  • Example 54 The programmable device of Example 51 , wherein the root monitor is configured to generate the control signals based at least in part on a timing schedule for calibrating the plurality of satellite monitors.
  • Example 55 The programmable device of Example 54, wherein the timing schedule is configured to sequentially enable calibration of each of the plurality of satellite monitors by providing the temperature-independent reference voltage to only one of the satellite monitors at a time.
  • Example 56 A method of monitoring operating conditions of a plurality of circuits distributed in various locations across a programmable device, the method comprising: generating an analog signal indicative of the operating conditions of each of the plurality of circuits using a corresponding one of a plurality of sensors distributed in the various locations across the programmable device; providing each of the analog signals to a corresponding one of a plurality of satellite monitors distributed in the various locations across the programmable device; storing, in each of the plurality of satellite monitors, a local reference voltage based on a temperature-independent reference voltage; converting, in each of the plurality of satellite monitors, a corresponding one of the plurality of analog signals into a digital code using an analog-to-digital converter (ADC) based on the local reference voltage; distributing the temperature-independent reference voltage from a root monitor to each of the plurality of satellite monitors; correcting the digital code generated by the ADC within each of the plurality of satellite monitors based at least in part on the distributed temperature-independent reference voltage;
  • Example 57 The method of Example 56, wherein: the corrected digital codes are selectively routed from the plurality of satellite monitors to the root monitor using a network-on-chip (NoC) interconnect system spanning the programmable device; and the temperature-independent reference voltage is distributed from the root monitor to the plurality of satellite monitors using one or more analog channels spanning the programmable device.
  • NoC network-on-chip
  • Example 58 The method of Example 57, wherein the storing comprises: selectively charging a capacitor provided within a respective satellite monitor using the temperature-independent reference voltage distributed by the one or more analog channels.
  • Example 59 The method of Example 56, wherein distributing the temperature-independent reference voltage further comprises: sequentially enabling each of the plurality of satellite monitors to access the temperature- independent reference voltage based on a corresponding plurality of control signals generated by the root monitor.
  • Example 60 The method of Example 56, wherein the correcting comprises: providing the temperature-independent reference voltage as an input signal to the ADC; converting the temperature-independent reference voltage into a reference code using the ADC; generating a correction factor based on differences between the reference code and a predetermined digital code indicative of the temperature- independent reference voltage; and adjusting the digital code based on the correction factor.
  • a software module may reside in RAM latch, flash latch, ROM latch, EPROM latch, EEPROM latch, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
  • An example storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

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US16/506,064 US11709275B2 (en) 2019-07-09 2019-07-09 Root monitoring on an FPGA using satellite ADCs
US16/535,713 US10705144B1 (en) 2019-08-08 2019-08-08 Device monitoring using satellite ADCs having local capacitors
US16/535,726 US10598729B1 (en) 2019-08-08 2019-08-08 Device monitoring using satellite ADCs having local voltage reference
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