EP3977515A1 - Transistor cell having an implanted expansion region - Google Patents

Transistor cell having an implanted expansion region

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Publication number
EP3977515A1
EP3977515A1 EP20728423.3A EP20728423A EP3977515A1 EP 3977515 A1 EP3977515 A1 EP 3977515A1 EP 20728423 A EP20728423 A EP 20728423A EP 3977515 A1 EP3977515 A1 EP 3977515A1
Authority
EP
European Patent Office
Prior art keywords
epitaxial layer
front side
trench
implanted
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP20728423.3A
Other languages
German (de)
French (fr)
Inventor
Dick Scholten
Alberto MARTINEZ-LIMIA
Holger Bartolf
Daniel Krebs
Wolfgang Feiler
Stephan Schwaiger
Jan-Hendrik Alsmeier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP3977515A1 publication Critical patent/EP3977515A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/7602—Making of isolation regions between components between components manufactured in an active substrate comprising SiC compounds
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/7605—Making of isolation regions between components between components manufactured in an active substrate comprising AIII BV compounds
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
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    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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    • H01L29/2003—Nitride compounds
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Definitions

  • the invention relates to a transistor cell with an expansion area, a transistor with a plurality of transistor cells with such a region
  • the gate oxide of an n-trench MOSFET is high in blocking mode
  • the disadvantage here is that the conductivity of the transistor is impaired in on-mode operation.
  • the object of the invention is to overcome this disadvantage. Disclosure of the invention
  • the transistor cell comprises a semiconductor substrate having a front side and a rear side, the front side being opposite the rear side.
  • An epitaxial layer is arranged on the front side.
  • Channel regions are arranged on the epitaxial layer.
  • Source regions are arranged on the channel regions.
  • a trench and field shielding regions extend from the front side of the semiconductor substrate into the epitaxial layer, the
  • Field shielding areas are each arranged laterally spaced from the trench.
  • the trench is less deep than the field shielding areas.
  • an implanted widening area with a certain thickness is arranged below the trench.
  • the implanted widening area is arranged at a depth of 0.5 ⁇ m to 3 ⁇ m, starting from the front side of the semiconductor substrate.
  • the advantage here is that commercially available implantation systems can be used.
  • the implanted widening area is arranged to the side of the trench. In other words, the implanted one
  • the expansion area is arranged both to the side of the trench and below the trench.
  • the advantage here is that the current-carrying, implanted region is arranged in a U-shape around the trench. This improves the power distribution effect.
  • the implanted widening area is arranged at a distance from the trench.
  • the implanted widening region has the same type of line carrier as the epitaxial layer, with one
  • Doping concentration of the implanted widening region is higher than a doping concentration of the epitaxial layer.
  • the doping concentration increases along the thickness of the implanted widening region, starting from a side facing the trench.
  • the implanted dilation area has a retrograde profile.
  • the advantage here is that the fields at the gate oxide are reduced and the JFET effect between the field shielding regions is reduced. This means that the conductivity in the case of passage and the field load of the oxide in the case of blocking are coordinated or optimized.
  • the semiconductor substrate comprises silicon carbide or gallium nitride.
  • the transistor according to the invention comprises a plurality of transistor cells which have a semiconductor substrate which comprises a front side and a rear side, the front side being opposite the rear side.
  • An epitaxial layer is arranged on the front side.
  • Channel regions are arranged on the epitaxial layer.
  • Source regions are arranged on the channel regions.
  • a trench and field shielding regions extend from the front side of the semiconductor substrate into the epitaxial layer, the
  • Field shielding areas are each arranged laterally spaced from the trench.
  • the trench is less deep than the field shielding areas.
  • an implanted widening area with a certain thickness is arranged below the trench.
  • the advantage here is that the conductivity of the transistor is high in on mode. In a further development, the transistor is a must.
  • the method according to the invention for producing a transistor with a plurality of transistor cells comprises the production of an epitaxial layer on a front side of a semiconductor substrate, the epitaxial layer having dopants and the production of field shielding regions that extend from a front side of the epitaxial layer into the epitaxial layer, the field shielding regions Have dopants.
  • the procedure includes that
  • the method comprises generating source regions which are arranged on the channel regions, the source regions having dopants, and implanting an expansion region with a specific thickness starting from the front side at a depth of 0.5 ⁇ m to 3 ⁇ m, the
  • Has expansion area dopants The method includes activating the dopants. Furthermore, the method comprises the creation of a multiplicity of trenches that extend from the front side of the
  • Semiconductor substrate extend into the epitaxial layer, the trenches having a shallower depth than the field shielding regions, the application of first isolation areas on the trench surfaces of the trenches, the production of gate electrodes, the production of second insulation areas, which are arranged above the gate electrodes, the production of a first Metal layer on the front side of the semiconductor substrate and the creation of a second one
  • the advantage here is that the doping concentration of the implanted widening regions or the widening layer can be set more precisely than during the application of an epitaxial widening layer.
  • FIG. 1 shows a transistor cell with an implanted expansion region
  • FIG. 2 shows a method for producing a transistor with a plurality of transistor cells with an implanted widening area.
  • FIG. 1 shows a transistor cell 100 with a semiconductor substrate 101 which has a front side and a rear side, the front side being opposite the rear side.
  • the transistor cell 100 has a width w, the so-called pitch.
  • An epitaxial layer 102 is arranged on the front side of the semiconductor substrate 101. On the epitaxial layer 102, channel regions 103 or
  • Source regions 104 are arranged on the channel regions 103.
  • a trench 105 and field shielding regions 108 extend from the front side of the semiconductor substrate 101 into the epitaxial layer 102.
  • the field shielding regions 108 have a greater depth than the trench 105. In other words, the field shielding regions 108 extend deeper into the epitaxial layer 102 than the trench 105
  • the field shielding regions 108 are laterally spaced from the trench 105. This means that the field shielding regions 108 are arranged at a certain distance to the side of the trench.
  • the specific distance is preferably 0.2 pm-1.5 pm.
  • An implanted widening region 112 having a specific thickness is arranged below the trench 105. The specific thickness is preferably 0.3 ⁇ m to 3 ⁇ m.
  • the implanted widening area 112 is thus between the
  • the implanted widening region 112 is implanted over the entire area, the field shielding regions 108 being significantly more highly doped than the implanted widening region 112, so that the field shielding regions 108 compensate for the implanted widening region 112.
  • the implanted widening region 112 is arranged starting from the front side of the semiconductor substrate 101 at a depth between 0.5 ⁇ m and 3 ⁇ m.
  • the implanted dilation area 112 is arranged both to the side of the trench 105 and below the trench 105. This means that the implanted expansion area 112 is directly adjacent to the side walls of the trench 105 and the trench bottom. Alternatively, the implanted expansion area 112 faces along a
  • the implanted widening region 112 has the same charge carrier type as the epitaxial layer, the doping concentration of the implanted widening region being higher than the doping concentration of the epitaxial layer.
  • the doping concentration of the implanted widening region 112 is between 8el5 cm A -3 and lel8 cm A -3 and the doping concentration of the epitaxial layer is between lel5 cm A -3 and lel7 cm A -3.
  • a first insulation layer or a first insulation region 106 is arranged on the trench surface of the trench 105.
  • the first isolation region 106 functions as a gate oxide.
  • the trench 106 is filled with a polysilicon, for example, wherein the polysilicon functions as a gate electrode 107.
  • a second insulation area 109 is arranged above the trench 105.
  • a first metal layer 110 is arranged on the front side of the semiconductor substrate 101. The first metal layer 110 functions as a front-side metallization and provides the
  • a second metal layer 111 is arranged on the rear side of the semiconductor substrate 101.
  • the second metal layer 111 functions as a rear-side metallization and represents the drain connection.
  • the semiconductor substrate 101, the epitaxial layer 102, the channel regions 104 and the implanted widening region 112 are n-doped.
  • the doping concentration of the semiconductor substrate 101 is between lel8 cm A -3 and lel9 cm A -3, the doping concentration of the epitaxial layer 102 between lel5 cm A -3 and lel7 cm A -3 and the doping concentration of the channel regions between lel7 cm A -3 and lel8 cm A -3.
  • Field shielding regions 108 are p-doped.
  • the doping concentration of the source regions is between lel8 cm A -3 and le20 cm A -3.
  • the semiconductor substrate 101 the epitaxial layer 102, the
  • Channel regions 104 and the implanted widening region 112 are p-doped.
  • the source regions 103 and the field shielding regions 108 are n-doped.
  • the semiconductor substrate 101 comprises silicon, silicon carbide or gallium nitride.
  • the doping concentration increases within the thickness of the implanted widening region 112 along the first
  • Main direction of extent y starting from a side facing the trench.
  • the implanted widening region 112 thus has a retrograde course, that in the direction of the trench 105 has a smaller one
  • a transistor comprises a plurality of transistor cells 100.
  • the transistor cells 100 are arranged along a second main direction of extent x, which is arranged perpendicular to the first main direction of extent y,
  • Such a transistor is a mosfet, for example.
  • the transistor is used in power electronic components such as inverters for electric vehicles or hybrid vehicles, inverters for photovoltaic systems and wind turbines, as well as in train drives and high-voltage rectifiers.
  • FIG. 2 shows a method 200 for producing a transistor having a plurality of transistor cells.
  • the method 200 starts with a step 201 in which an epitaxial layer is produced on a front side of a semiconductor substrate, the epitaxial layer having dopants.
  • a subsequent step 202 field shielding regions are generated which, starting from a front side of the epitaxial layer, extend into the epitaxial layer, the field shielding regions having dopants.
  • channel regions are generated which are arranged on the epitaxial layer. These are generated by implantation in the epitaxial layer. The channel regions also have dopants.
  • source regions that are arranged on the channel regions are generated. The source regions also have dopants.
  • Steps 201 to 204 are carried out using masks and implants.
  • a step 205 following step 204 an expansion area with a specific thickness is implanted starting from the front side at a depth of 0.5 ⁇ m to 3 ⁇ m.
  • high-energy ions of the charge carrier type n with an implantation energy from 0.5 eV to 3 eV are introduced or implanted into the epitaxial layer using several implantation energies and implantation doses, so that the expansion area is structured.
  • the same mask that is used for structuring the channel regions can be used during the implantation.
  • the dopants are activated by means of thermal treatment.
  • a plurality of trenches are made with the aid of
  • the trenches extend from the front side of the semiconductor substrate into the epitaxial layer, the trenches being smaller
  • first isolation regions are applied to trench surfaces of the trenches.
  • SiO2 is deposited in the process.
  • gate electrodes are produced by filling the trenches with a polysilicon, for example.
  • a first is on the front side of the semiconductor substrate
  • a second metal layer is produced on a rear side of the semiconductor substrate, the rear side being opposite the front side.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to a transistor cell (100), comprising a semiconductor substrate (101), which has a front side and a rear side, wherein: the front side is opposite the rear side; an epitaxial layer (102) is arranged on the front side; channel regions (103) are arranged on the epitaxial layer (102) and source regions (104) are arranged on the channel regions (103); a trench (105) and field shielding regions (108) extend from the front side of the semiconductor substrate (101) into the epitaxial layer (102); the field shielding regions (108) are each arranged at a lateral distance from the trench (105), and the trench (105) has a smaller depth than the field shielding regions (108), characterized in that an implanted expansion region (112) having a certain thickness is arranged below the trench (105).

Description

Beschreibung description
Transistorzelle mit implantiertem Aufweitungsgebiet Transistor cell with an implanted expansion area
Die Erfindung betrifft eine Transistorzelle mit einem Aufweitungsgebiet, einem Transistor mit einer Vielzahl von Transistorzellen mit solch einem The invention relates to a transistor cell with an expansion area, a transistor with a plurality of transistor cells with such a region
Aufweitungsgebiet und ein Verfahren zur Herstellung solch eines Transistors. Expansion area and a method of making such a transistor.
Stand der Technik State of the art
Das Gateoxid eines n-Trench-Mosfets wird im Sperrbetrieb vor hohen The gate oxide of an n-trench MOSFET is high in blocking mode
Feldstärken durch tiefreichende, hochdotierte p-Gebiete geschützt. Dabei weisen die hochdotierten Gebiete eine größere Tiefe auf als die Gräben. Field strengths protected by deep, highly doped p-regions. The highly doped areas have a greater depth than the trenches.
Nachteilig ist hierbei, dass die Leitfähigkeit des Transistors im Durchlassbetrieb verschlechtert wird. The disadvantage here is that the conductivity of the transistor is impaired in on-mode operation.
Das Dokument DE 10 2007 023 885 B4 beschreibt epitaktisch erzeugte The document DE 10 2007 023 885 B4 describes epitaxially generated
Aufweitungsschichten unterhalb des Grabens zur Verbesserung der Leitfähigkeit des Transistors im Durchlassbetrieb. Dabei wird die Dotierstoffkonzentration während des Erzeugens der Epitaxieschicht für eine bestimmte Zeitdauer verändert, sodass ein Bereich mit einer höheren Dotierungskonzentration entsteht. Expansion layers below the trench to improve the conductivity of the transistor in on mode. In this case, the dopant concentration is changed for a certain period of time during the creation of the epitaxial layer, so that a region with a higher doping concentration is created.
Nachteilig ist hierbei, dass die Dotierungskonzentration aufgrund der The disadvantage here is that the doping concentration due to the
Abhängigkeit der Wachstumstemperatur der Epitaxieschicht eine hohe Dependence on the growth temperature of the epitaxial layer has a high
Schwankung von ca. 25% aufweist. Das bedeutet die Einstellung der Has a fluctuation of approx. 25%. That means setting the
Dotierungskonzentration ist problematisch. Doping concentration is problematic.
Die Aufgabe der Erfindung ist es diesen Nachteil zu überwinden. Offenbarung der Erfindung The object of the invention is to overcome this disadvantage. Disclosure of the invention
Die Transistorzelle umfasst ein Halbleitersubstrat, das eine Vorderseite und eine Rückseite aufweist, wobei die Vorderseite der Rückseite gegenüberliegt. Auf der Vorderseite ist eine Epitaxieschicht angeordnet. Auf der Epitaxieschicht sind Kanalgebiete angeordnet. Auf den Kanalgebieten sind Sourcegebiete angeordnet. Ein Graben und Feldabschirmgebiete erstrecken sich von der Vorderseite des Halbleitersubstrats bis in die Epitaxieschicht, wobei die The transistor cell comprises a semiconductor substrate having a front side and a rear side, the front side being opposite the rear side. An epitaxial layer is arranged on the front side. Channel regions are arranged on the epitaxial layer. Source regions are arranged on the channel regions. A trench and field shielding regions extend from the front side of the semiconductor substrate into the epitaxial layer, the
Feldabschirmgebiete jeweils seitlich beabstandet zum Graben angeordnet sind. Der Graben weist eine geringere Tiefe auf als die Feldabschirmgebiete. Field shielding areas are each arranged laterally spaced from the trench. The trench is less deep than the field shielding areas.
Erfindungsgemäß ist unterhalb des Grabens ein implantiertes Aufweitungsgebiet mit einer bestimmten Dicke angeordnet. According to the invention, an implanted widening area with a certain thickness is arranged below the trench.
Der Vorteil ist hierbei, dass die Leitfähigkeit der Transistorzelle im The advantage here is that the conductivity of the transistor cell in
Durchlassbetrieb hoch ist, wobei gleichzeitig eine hohe Sperrfestigkeit gewährleistet ist. Forward operation is high, while at the same time a high blocking strength is ensured.
In einer Weiterbildung ist das implantierte Aufweitungsgebiet ausgehend von der Vorderseite des Halbleitersubstrats in einer Tiefe von 0,5 pm bis 3 pm angeordnet. In one development, the implanted widening area is arranged at a depth of 0.5 μm to 3 μm, starting from the front side of the semiconductor substrate.
Vorteilhaft ist hierbei, dass handelsübliche Implantationsanlagen verwendet werden können. The advantage here is that commercially available implantation systems can be used.
In einer weiteren Ausgestaltung ist das implantierte Aufweitungsgebiet seitlich des Grabens angeordnet. Mit anderen Worten das implantierte In a further embodiment, the implanted widening area is arranged to the side of the trench. In other words, the implanted one
Aufweitungsgebiet ist sowohl seitlich des Grabens als auch unterhalb des Grabens angeordnet. The expansion area is arranged both to the side of the trench and below the trench.
Der Vorteil ist hierbei, dass das stromtragende, implantierte Gebiet u-förmig um den Graben angeordnet ist. Dies verbessert den Stromverteilungseffekt. The advantage here is that the current-carrying, implanted region is arranged in a U-shape around the trench. This improves the power distribution effect.
In einer weiteren Ausgestaltung ist das implantierte Aufweitungsgebiet beabstandet zum Graben angeordnet. In einer Weiterbildung weist das implantierte Aufweitungsgebiet denselben Leitungsträgertyp auf wie die Epitaxieschicht, wobei eine In a further configuration, the implanted widening area is arranged at a distance from the trench. In one development, the implanted widening region has the same type of line carrier as the epitaxial layer, with one
Dotierungskonzentration des implantierten Aufweitungsgebiets höher ist als eine Dotierungskonzentration der Epitaxieschicht. Doping concentration of the implanted widening region is higher than a doping concentration of the epitaxial layer.
Vorteilhaft ist hierbei, dass sich die Leitfähigkeit der Transistorzelle erhöht. It is advantageous here that the conductivity of the transistor cell increases.
In einer weiteren Ausgestaltung nimmt die Dotierungskonzentration entlang der Dicke des implantierten Aufweitungsgebiets ausgehend von einer dem Graben zugewandten Seite zu. Mit anderen Worten das implantierte Aufweitungsgebiet weist ein retrogrades Profil auf. In a further refinement, the doping concentration increases along the thickness of the implanted widening region, starting from a side facing the trench. In other words, the implanted dilation area has a retrograde profile.
Der Vorteil ist hierbei, dass die Felder am Gateoxid reduziert werden und der JFET-Effekt zwischen den Feldabschirmgebieten verringert wird. Das bedeutet die Leitfähigkeit im Durchlassfall und die Feldbelastung des Oxids im Sperrfall sind aufeinander abgestimmt bzw. optimiert. The advantage here is that the fields at the gate oxide are reduced and the JFET effect between the field shielding regions is reduced. This means that the conductivity in the case of passage and the field load of the oxide in the case of blocking are coordinated or optimized.
In einer Weiterbildung umfasst das Halbleitersubstrat Siliziumkarbid oder Galliumnitrid. In one development, the semiconductor substrate comprises silicon carbide or gallium nitride.
Der erfindungsgemäße Transistor umfasst eine Vielzahl von Transistorzellen, die ein Halbleitersubstrat aufweisen, das eine Vorderseite und eine Rückseite umfasst, wobei die Vorderseite der Rückseite gegenüberliegt. Auf der The transistor according to the invention comprises a plurality of transistor cells which have a semiconductor substrate which comprises a front side and a rear side, the front side being opposite the rear side. On the
Vorderseite ist eine Epitaxieschicht angeordnet. Auf der Epitaxieschicht sind Kanalgebiete angeordnet. Auf den Kanalgebieten sind Sourcegebiete angeordnet. Ein Graben und Feldabschirmgebiete erstrecken sich von der Vorderseite des Halbleitersubstrats bis in die Epitaxieschicht, wobei die An epitaxial layer is arranged on the front side. Channel regions are arranged on the epitaxial layer. Source regions are arranged on the channel regions. A trench and field shielding regions extend from the front side of the semiconductor substrate into the epitaxial layer, the
Feldabschirmgebiete jeweils seitlich beabstandet zum Graben angeordnet sind. Der Graben weist eine geringere Tiefe auf als die Feldabschirmgebiete. Field shielding areas are each arranged laterally spaced from the trench. The trench is less deep than the field shielding areas.
Erfindungsgemäß ist unterhalb des Grabens ein implantiertes Aufweitungsgebiet mit einer bestimmten Dicke angeordnet. According to the invention, an implanted widening area with a certain thickness is arranged below the trench.
Der Vorteil ist hierbei, dass die Leitfähigkeit des Transistors im Durchlassbetrieb hoch ist. In einer Weiterbildung ist der Transistor ein Mostet. The advantage here is that the conductivity of the transistor is high in on mode. In a further development, the transistor is a must.
Das erfindungsgemäße Verfahren zur Herstellung eines Transistors mit einer Vielzahl von Transistorzellen umfasst das Erzeugen einer Epitaxieschicht auf einer Vorderseite eines Halbleitersubstrats, wobei die Epitaxieschicht Dotierstoffe aufweist und das Erzeugen von Feldabschirmgebieten, die sich ausgehend von einer Vorderseite der Epitaxieschicht in die Epitaxieschicht erstrecken, wobei die Feldabschirmgebiete Dotierstoffe aufweisen. Das Verfahren umfasst das The method according to the invention for producing a transistor with a plurality of transistor cells comprises the production of an epitaxial layer on a front side of a semiconductor substrate, the epitaxial layer having dopants and the production of field shielding regions that extend from a front side of the epitaxial layer into the epitaxial layer, the field shielding regions Have dopants. The procedure includes that
Erzeugen von Kanalgebieten, wobei die Kanalgebiete auf der Epitaxieschicht angeordnet sind und die Kanalgebiete Dotierstoffe aufweisen. Das Verfahren umfasst das Erzeugen von Sourcegebieten, die auf den Kanalgebieten angeordnet sind, wobei die Sourcegebiete Dotierstoffe aufweisen und das Implantieren eines Aufweitungsgebiets mit einer bestimmten Dicke ausgehend von der Vorderseite in einer Tiefe von 0,5 pm bis 3 pm, wobei das Production of channel regions, the channel regions being arranged on the epitaxial layer and the channel regions having dopants. The method comprises generating source regions which are arranged on the channel regions, the source regions having dopants, and implanting an expansion region with a specific thickness starting from the front side at a depth of 0.5 μm to 3 μm, the
Aufweitungsgebiet Dotierstoffe aufweist. Das Verfahren umfasst das Aktivieren der Dotierstoffe. Des Weiteren umfasst das Verfahren das Erzeugen einer Vielzahl von Gräben, die sich ausgehend von der Vorderseite des Has expansion area dopants. The method includes activating the dopants. Furthermore, the method comprises the creation of a multiplicity of trenches that extend from the front side of the
Halbleitersubstrats bis in die Epitaxieschicht erstrecken, wobei die Gräben eine geringere Tiefe aufweisen als die Feldabschirmgebiete, das Aufbringen von ersten Isolationsbereichen auf Grabenoberflächen der Gräben, das Erzeugen von Gateelektroden, das Erzeugen von zweiten Isolationsbereichen, die oberhalb der Gateelektroden angeordnet sind, das Erzeugen einer ersten Metallschicht auf der Vorderseite des Halbleitersubstrats und das Erzeugen einer zweiten Semiconductor substrate extend into the epitaxial layer, the trenches having a shallower depth than the field shielding regions, the application of first isolation areas on the trench surfaces of the trenches, the production of gate electrodes, the production of second insulation areas, which are arranged above the gate electrodes, the production of a first Metal layer on the front side of the semiconductor substrate and the creation of a second one
Metallschicht auf der Rückseite des Halbleitersubstrats, wobei die Rückseite der Vorderseite gegenüberliegt. Metal layer on the back of the semiconductor substrate, with the back facing the front.
Der Vorteil ist hierbei, dass die Dotierungskonzentration der implantierten Aufweitungsgebiete bzw. der Aufweitungsschicht genauer einstellbar ist als während des Aufbringens einer epitaktischen Aufweitungsschicht. The advantage here is that the doping concentration of the implanted widening regions or the widening layer can be set more precisely than during the application of an epitaxial widening layer.
Weitere Vorteile ergeben sich aus der nachfolgenden Beschreibung von Further advantages emerge from the following description of FIG
Ausführungsbeispielen bzw. den abhängigen Patentansprüchen. Kurze Beschreibung der Zeichnungen Embodiments and the dependent claims. Brief description of the drawings
Die vorliegende Erfindung wird nachfolgend anhand bevorzugter The present invention will hereinafter be made more preferred
Ausführungsformen und beigefügter Zeichnungen erläutert. Es zeigen: Embodiments and accompanying drawings explained. Show it:
Figur 1 eine Transistorzelle mit implantiertem Aufweitungsgebiet, und FIG. 1 shows a transistor cell with an implanted expansion region, and FIG
Figur 2 ein Verfahren zur Herstellung eines Transistors mit einer Vielzahl von Transistorzellen mit implantiertem Aufweitungsgebiet. FIG. 2 shows a method for producing a transistor with a plurality of transistor cells with an implanted widening area.
Figur 1 zeigt eine Transistorzelle 100 mit einem Halbleitersubstrat 101, das eine Vorderseite und eine Rückseite aufweist, wobei die Vorderseite der Rückseite gegenüberliegt. Die Transistorzelle 100 weist eine Weite w auf, den sogenannten Pitch. Auf der Vorderseite des Halbleitersubstrats 101 ist eine Epitaxieschicht 102 angeordnet. Auf der Epitaxieschicht 102 sind Kanalgebiete 103 bzw. FIG. 1 shows a transistor cell 100 with a semiconductor substrate 101 which has a front side and a rear side, the front side being opposite the rear side. The transistor cell 100 has a width w, the so-called pitch. An epitaxial layer 102 is arranged on the front side of the semiconductor substrate 101. On the epitaxial layer 102, channel regions 103 or
Bodygebiete angeordnet. Auf den Kanalgebieten 103 sind Sourcegebiete 104 angeordnet. Ein Graben 105 und Feldabschirmgebiete 108 erstrecken sich von der Vorderseite des Halbleitersubstrats 101 bis in die Epitaxieschicht 102. Die Feldabschirmgebiete 108 weisen eine größere Tiefe auf als der Graben 105. Mit anderen Worten die Feldabschirmgebiete 108 reichen tiefer in die Epitaxieschicht 102 hinein als der Graben 105. Die Feldabschirmgebiete 108 weisen einen seitlichen Abstand zum Graben 105 auf. Das bedeutet die Feldabschirmgebiete 108 sind seitlich des Grabens in einem bestimmten Abstand angeordnet. Der bestimmte Abstand beträgt vorzugsweise 0, 2 pm - 1,5 pm. Unterhalb des Grabens 105 ist ein implantiertes Aufweitungsgebiet 112 mit einer bestimmten Dicke angeordnet. Die bestimmte Dicke beträgt vorzugsweise 0,3 pm - 3 pm.Body areas arranged. Source regions 104 are arranged on the channel regions 103. A trench 105 and field shielding regions 108 extend from the front side of the semiconductor substrate 101 into the epitaxial layer 102. The field shielding regions 108 have a greater depth than the trench 105. In other words, the field shielding regions 108 extend deeper into the epitaxial layer 102 than the trench 105 The field shielding regions 108 are laterally spaced from the trench 105. This means that the field shielding regions 108 are arranged at a certain distance to the side of the trench. The specific distance is preferably 0.2 pm-1.5 pm. An implanted widening region 112 having a specific thickness is arranged below the trench 105. The specific thickness is preferably 0.3 μm to 3 μm.
Das implantierte Aufweitungsgebiet 112 ist somit zwischen den The implanted widening area 112 is thus between the
Feldabschirmgebieten 108 angeordnet, wobei die Feldabschirmgebiete 108 das implantierte Aufweitungsgebiet 112 überdecken bzw. überlappen. Mit anderen Worten das implantierte Aufweitungsgebiet 112 ist vollflächig implantiert, wobei die Feldabschirmgebiete 108 deutlich höher dotiert sind als das implantierte Aufweitungsgebiet 112, sodass die Feldabschirmgebiete 108 das implantierte Aufweitungsgebiet 112 kompensieren. Das implantierte Aufweitungsgebiet 112 ist ausgehend von der Vorderseite des Halbleitersubstrats 101 in einer Tiefe zwischen 0,5 pm und 3 pm angeordnet. Das implantierte Aufweitungsgebiet 112 ist sowohl seitlich des Grabens 105 als auch unterhalb des Grabens 105 angeordnet. Das bedeutet das implantierte Ausweitungsgebiet 112 grenzt unmittelbar an die Seitenwände des Grabens 105 und den Grabenboden an. Alternativ weist das implantierte Aufweitungsgebiet 112 entlang einer Arranged field shielding regions 108, wherein the field shielding regions 108 cover or overlap the implanted widening region 112. In other words, the implanted widening region 112 is implanted over the entire area, the field shielding regions 108 being significantly more highly doped than the implanted widening region 112, so that the field shielding regions 108 compensate for the implanted widening region 112. The implanted widening region 112 is arranged starting from the front side of the semiconductor substrate 101 at a depth between 0.5 μm and 3 μm. The implanted dilation area 112 is arranged both to the side of the trench 105 and below the trench 105. This means that the implanted expansion area 112 is directly adjacent to the side walls of the trench 105 and the trench bottom. Alternatively, the implanted expansion area 112 faces along a
Haupterstreckungsrichtung y einen bestimmten Abstand zum Graben 105 auf. Das implantierte Aufweitungsgebiet 112 weist denselben Ladungsträgertyp auf wie die Epitaxieschicht, wobei die Dotierungskonzentration des implantierten Aufweitungsgebiets höher ist als die Dotierungskonzentration der Epitaxieschicht. Die Dotierungskonzentration des implantierten Aufweitungsgebiets 112 beträgt dabei zwischen 8el5cmA-3 und lel8cmA-3 und die Dotierungskonzentration der Epitaxieschicht zwischen lel5cmA-3 und lel7 cmA-3. Auf einer Main direction of extent y a certain distance from the trench 105. The implanted widening region 112 has the same charge carrier type as the epitaxial layer, the doping concentration of the implanted widening region being higher than the doping concentration of the epitaxial layer. The doping concentration of the implanted widening region 112 is between 8el5 cm A -3 and lel8 cm A -3 and the doping concentration of the epitaxial layer is between lel5 cm A -3 and lel7 cm A -3. On a
Grabenoberfläche des Grabens 105 ist eine erste Isolationsschicht bzw. ein erster Isolationsbereich 106 angeordnet. Der erste Isolationsbereich 106 fungiert als Gateoxid. Der Graben 106 ist beispielsweise mit einem Polysilizium verfüllt, wobei das Polysilizium als Gateelektrode 107 fungiert. Oberhalb des Grabens 105 ist ein zweiter Isolationsbereich 109 angeordnet. Auf der Vorderseite des Halbleitersubstrats 101 ist eine erste Metallschicht 110 angeordnet. Die erste Metallschicht 110 fungiert als Vorderseitenmetallisierung und stellt den On the trench surface of the trench 105, a first insulation layer or a first insulation region 106 is arranged. The first isolation region 106 functions as a gate oxide. The trench 106 is filled with a polysilicon, for example, wherein the polysilicon functions as a gate electrode 107. A second insulation area 109 is arranged above the trench 105. A first metal layer 110 is arranged on the front side of the semiconductor substrate 101. The first metal layer 110 functions as a front-side metallization and provides the
Sourceanschluss dar. Auf der Rückseite des Halbleitersubstrats 101 ist eine zweite Metallschicht 111 angeordet. Die zweite Metallschicht 111 fungiert als Rückseitenmetallisierung und stellt den Drainanschluss dar. A second metal layer 111 is arranged on the rear side of the semiconductor substrate 101. The second metal layer 111 functions as a rear-side metallization and represents the drain connection.
Das Halbleitersubstrat 101, die Epitaxieschicht 102, die Kanalgebiete 104, sowie das implantierte Aufweitungsgebiet 112 sind n-dotiert. Die The semiconductor substrate 101, the epitaxial layer 102, the channel regions 104 and the implanted widening region 112 are n-doped. The
Dotierungskonzentration des Halbleitersubstrats 101 beträgt zwischen lel8 cmA- 3 und lel9 cmA-3, die Dotierungskonzentration der Epitaxieschicht 102 zwischen lel5 cmA-3 und lel7 cmA-3 und die Dotierungskonzentration der Kanalgebiete zwischen lel7 cmA-3 und lel8 cmA-3. Die Sourcegebiete 103 und die The doping concentration of the semiconductor substrate 101 is between lel8 cm A -3 and lel9 cm A -3, the doping concentration of the epitaxial layer 102 between lel5 cm A -3 and lel7 cm A -3 and the doping concentration of the channel regions between lel7 cm A -3 and lel8 cm A -3. The source areas 103 and the
Feldabschirmgebiete 108 sind p-dotiert. Die Dotierungskonzentration der Sourcegebiete beträgt zwischen lel8 cmA-3 und le20 cmA-3. Field shielding regions 108 are p-doped. The doping concentration of the source regions is between lel8 cm A -3 and le20 cm A -3.
Alternativ sind das Halbleitersubstrat 101, die Epitaxieschicht 102, die Alternatively, the semiconductor substrate 101, the epitaxial layer 102, the
Kanalgebiete 104, sowie das implantierte Aufweitungsgebiet 112 p-dotiert. Die Sourcegebiete 103 und die Feldabschirmgebiete 108 sind n-dotiert. Das Halbleitersubstrat 101 umfasst Silizium, Siliziumkarbid oder Galliumnitrid. Channel regions 104 and the implanted widening region 112 are p-doped. The source regions 103 and the field shielding regions 108 are n-doped. The semiconductor substrate 101 comprises silicon, silicon carbide or gallium nitride.
In einem Ausführungsbeispiel nimmt die Dotierungskonzentration innerhalb der Dicke des implantierten Aufweitungsgebiets 112 entlang der ersten In one embodiment, the doping concentration increases within the thickness of the implanted widening region 112 along the first
Haupterstreckungsrichtung y ausgehend von einer dem Graben zugewandten Seite zu. Somit weist das implantierte Aufweitungsgebiet 112 einen retrograden Verlauf auf, das in Richtung des Grabens 105 eine geringere Main direction of extent y starting from a side facing the trench. The implanted widening region 112 thus has a retrograde course, that in the direction of the trench 105 has a smaller one
Dotierungskonzentration aufweist als in Richtung der Rückseitenmetallisierung. Has doping concentration than in the direction of the rear side metallization.
Ein Transistor umfasst eine Vielzahl von Transistorzellen 100. Dabei werden die Transistorzellen 100 entlang einer zweiten Haupterstreckungsrichtung x, die senkrecht zur ersten Haupterstreckungsrichtung y angeordnet ist, A transistor comprises a plurality of transistor cells 100. In this case, the transistor cells 100 are arranged along a second main direction of extent x, which is arranged perpendicular to the first main direction of extent y,
aneinandergereiht. Solch ein Transistor ist beispielsweise ein Mosfet. lined up. Such a transistor is a mosfet, for example.
Der Transistor findet in leistungselektronischen Bauelementen, wie Invertern für Elektrofahrzeuge oder Hybridfahrzeuge, Invertern für Photovoltaikanlagen und Windkraftanlagen, sowie in Zugantrieben und Hochspannungsgleichrichtern, Anwendung. The transistor is used in power electronic components such as inverters for electric vehicles or hybrid vehicles, inverters for photovoltaic systems and wind turbines, as well as in train drives and high-voltage rectifiers.
Figur 2 zeigt ein Verfahren 200 zur Herstellung eines Transistors mit einer Vielzahl von Transistorzellen. Das Verfahren 200 startet mit einem Schritt 201, in dem eine Epitaxieschicht auf einer Vorderseite eines Halbleitersubstrats erzeugt wird, wobei die Epitaxieschicht Dotierstoffe aufweist. In einem folgenden Schritt 202 werden Feldabschirmgebiete erzeugt, die sich ausgehend von einer Vorderseite der Epitaxieschicht in die Epitaxieschicht erstrecken, wobei die Feldabschirmgebiete Dotierstoffe aufweisen. In einem folgenden Schritt 203 werden Kanalgebiete erzeugt, die auf der Epitaxieschicht angeordnet sind. Diese werden durch Implantation in die Epitaxieschicht erzeugt. Auch die Kanalgebiete weisen Dotierstoffe auf. In einem folgenden Schritt 204 werden Sourcegebiete erzeugt, die auf den Kanalgebieten angeordnet sind. Auch die Sourcegebiete weisen Dotierstoffe auf. Die Schritte 201 bis 204 werden mittels Masken und Implantationen durchgeführt. In einem auf den Schritt 204 folgenden Schritt 205 wird ein Aufweitungsgebiet mit einer bestimmten Dicke ausgehend von der Vorderseite in einer Tiefe von 0,5 pm bis 3 pm implantiert. Dabei werden hochenergetische Ionen vom Ladungsträgertyp n mit einer Implantationsenergie von 0,5 eV bis 3 eV unter Verwendung mehrerer Implantationsenergien und Implantationsdosen in die Epitaxieschicht eingebracht bzw. implantiert, sodass das Aufweitungsgebiet strukturiert wird. Somit weist das implantierte FIG. 2 shows a method 200 for producing a transistor having a plurality of transistor cells. The method 200 starts with a step 201 in which an epitaxial layer is produced on a front side of a semiconductor substrate, the epitaxial layer having dopants. In a subsequent step 202, field shielding regions are generated which, starting from a front side of the epitaxial layer, extend into the epitaxial layer, the field shielding regions having dopants. In a subsequent step 203, channel regions are generated which are arranged on the epitaxial layer. These are generated by implantation in the epitaxial layer. The channel regions also have dopants. In a subsequent step 204, source regions that are arranged on the channel regions are generated. The source regions also have dopants. Steps 201 to 204 are carried out using masks and implants. In a step 205 following step 204, an expansion area with a specific thickness is implanted starting from the front side at a depth of 0.5 μm to 3 μm. Here, high-energy ions of the charge carrier type n with an implantation energy from 0.5 eV to 3 eV are introduced or implanted into the epitaxial layer using several implantation energies and implantation doses, so that the expansion area is structured. Thus, the implanted
Aufweitungsgebiet Dotierstoffe auf. Bei der Implantation kann die gleiche Maske verwendet werden, die zur Strukturierung der Kanalgebiete verwendet wird.Expansion area dopants on. The same mask that is used for structuring the channel regions can be used during the implantation.
Dadurch reduzieren sich die Herstellungskosten. In einem folgenden Schritt 206 werden die Dotierstoffe mittels thermischer Behandlung aktiviert. In einem folgenden Schritt 207 werden eine Vielzahl von Gräben mit Hilfe von This reduces the manufacturing costs. In a subsequent step 206, the dopants are activated by means of thermal treatment. In a following step 207, a plurality of trenches are made with the aid of
Ätzverfahren erzeugt. Die Gräben erstrecken sich von der Vorderseite des Halbleitersubstrats bis in die Epitaxieschicht, wobei die Gräben eine geringereEtching process generated. The trenches extend from the front side of the semiconductor substrate into the epitaxial layer, the trenches being smaller
Tiefe aufweisen als die Feldabschirmgebiete. In einem folgenden Schritt 208 werden erste Isolationsbereiche auf Grabenoberflächen der Gräben aufgebracht. Dabei wird beispielsweise Si02 abgeschieden. In einem folgenden Schritt 209 werden Gateelektroden erzeugt, indem die Gräben beispielsweise mit einem Polysilizium verfüllt werden. In einem folgenden Schritt 210 werden zweiteHave depth than the field shielding areas. In a subsequent step 208, first isolation regions are applied to trench surfaces of the trenches. For example, SiO2 is deposited in the process. In a subsequent step 209, gate electrodes are produced by filling the trenches with a polysilicon, for example. In a following step 210, second
Isolationsbereiche oberhalb der Gateelektroden erzeugt. In einem folgenden Schritt 211 wird auf der Vorderseite des Halbleitersubstrats eine erste Isolation areas generated above the gate electrodes. In a following step 211, a first is on the front side of the semiconductor substrate
Metallschicht erzeugt. In einem folgenden Schritt 212 wird auf einer Rückseite des Halbleitersubstrats eine zweite Metallschicht erzeugt, wobei die Rückseite der Vorderseite gegenüberliegt. Metal layer generated. In a subsequent step 212, a second metal layer is produced on a rear side of the semiconductor substrate, the rear side being opposite the front side.

Claims

Ansprüche Expectations
1. Transistorzelle (100) mit einem Halbleitersubstrat (101), das eine Vorderseite und eine Rückseite aufweist, wobei die Vorderseite der Rückseite 1. A transistor cell (100) having a semiconductor substrate (101) which has a front side and a rear side, the front side being the rear side
gegenüberliegt, wobei auf der Vorderseite eine Epitaxieschicht (102) angeordnet ist, wobei auf der Epitaxieschicht (102) Kanalgebiete (103) angeordnet sind und auf den Kanalgebieten (103) Sourcegebiete (104) angeordnet sind, wobei sich ein Graben (105) und Feldabschirmgebiete (108) von der Vorderseite des Halbleitersubstrats (101) bis in die Epitaxieschicht (102) erstrecken, wobei die Feldabschirmgebiete (108) jeweils seitlich beabstandet zum Graben (105) angeordnet sind und der Graben (105) eine geringere Tiefe aufweist als die Feldabschirmgebiete (108), dadurch gekennzeichnet, dass unterhalb des Grabens (105) ein implantiertes Aufweitungsgebiet (112) mit einer bestimmten Dicke angeordnet ist. opposite, wherein an epitaxial layer (102) is arranged on the front side, channel regions (103) are arranged on the epitaxial layer (102) and source regions (104) are arranged on the channel regions (103), with a trench (105) and field shielding regions (108) extend from the front side of the semiconductor substrate (101) into the epitaxial layer (102), the field shielding regions (108) each being arranged laterally spaced from the trench (105) and the trench (105) having a shallower depth than the field shielding regions ( 108), characterized in that an implanted widening area (112) with a certain thickness is arranged below the trench (105).
2. Transistorzelle (100) nach Anspruch 1, dadurch gekennzeichnet, dass das implantierte Aufweitungsgebiet (112) ausgehend von der Vorderseite des Halbleitersubstrats (101) in einer Tiefe von 0,5 pm bis 3 pm angeordnet ist. 2. transistor cell (100) according to claim 1, characterized in that the implanted expansion region (112) is arranged starting from the front side of the semiconductor substrate (101) at a depth of 0.5 pm to 3 pm.
3. Transistorzelle (100) nach einem der Ansprüche 1 oder 2, dadurch 3. transistor cell (100) according to one of claims 1 or 2, characterized
gekennzeichnet, dass das implantierte Aufweitungsgebiet (112) seitlich des Grabens (105) angeordnet ist. characterized in that the implanted widening area (112) is arranged to the side of the trench (105).
4. Transistorzelle (100) nach einem der Ansprüche 1 oder 2, dadurch 4. transistor cell (100) according to one of claims 1 or 2, characterized
gekennzeichnet, dass das implantierte Aufweitungsgebiet (112) beabstandet zum Graben (105) angeordnet ist. characterized in that the implanted widening region (112) is arranged at a distance from the trench (105).
5. Transistorzelle (100) nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass das implantierte Aufweitungsgebiet (112) denselben Leitungsträgertypen aufweist wie die Epitaxieschicht (102), wobei eine Dotierungskonzentration des implantierten Aufweitungsgebiets (112) höher ist als eine Dotierungskonzentration der Epitaxieschicht (102). 5. transistor cell (100) according to any one of the preceding claims, characterized in that the implanted widening region (112) has the same line carrier types as the epitaxial layer (102), wherein one Doping concentration of the implanted widening region (112) is higher than a doping concentration of the epitaxial layer (102).
6. Transistorzelle (100) nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass die Dotierungskonzentration entlang der Dicke des implantierten Aufweitungsgebiets (112) ausgehend von einer dem Graben zugewandten Seite zunimmt. 6. transistor cell (100) according to any one of the preceding claims, characterized in that the doping concentration increases along the thickness of the implanted widening region (112) starting from a side facing the trench.
7. Transistorzelle (100) nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass das Halbleitersubstrat Siliziumkarbid oder Galliumnitrid aufweist. 7. transistor cell (100) according to any one of the preceding claims, characterized in that the semiconductor substrate comprises silicon carbide or gallium nitride.
8. Transistor mit einer Vielzahl von Transistorzellen nach einem der 8. Transistor with a plurality of transistor cells according to one of the
vorhergehenden Ansprüche. preceding claims.
9. Transistor nach Anspruch 8, dadurch gekennzeichnet, dass der Transistor ein MOSFET ist. 9. Transistor according to claim 8, characterized in that the transistor is a MOSFET.
10. Verfahren zur Herstellung eines Transistors mit einer Vielzahl von 10. A method of manufacturing a transistor with a plurality of
Transistorzellen mit den Schritten: Transistor cells with the steps:
• Erzeugen (201) einer Epitaxieschicht auf einer Vorderseite eines • Generating (201) an epitaxial layer on a front side of a
Halbleitersubstrats, wobei die Epitaxieschicht Dotierstoffe aufweist, Semiconductor substrate, the epitaxial layer having dopants,
• Erzeugen (202) von Feldabschirmgebieten, die sich ausgehend von einer Vorderseite der Epitaxieschicht bis in die Epitaxieschicht erstrecken, wobei die Feldabschirmgebiete Dotierstoffe aufweisen, • Generating (202) field shielding regions which, starting from a front side of the epitaxial layer, extend into the epitaxial layer, the field shielding regions having dopants,
• Erzeugen (203) von Kanalgebieten, die auf der Epitaxieschicht • Creation (203) of channel regions on the epitaxial layer
angeordnet sind, wobei die Kanalgebiete Dotierstoffe aufweisen, are arranged, wherein the channel regions have dopants,
• Erzeugen (204) von Sourcegebieten, die auf den Kanalgebieten • Generating (204) source areas that are on the channel areas
angeordnet sind, wobei die Sourcegebiete Dotierstoffe aufweisen, are arranged, the source regions having dopants,
• Implantieren (205) eines Aufweitungsgebiets mit einer bestimmten Dicke ausgehend von der Vorderseite in einer Tiefe von 0,5 pm - 3 pm, wobei das Aufweitungsgebiet Dotierstoffe aufweist, • Implanting (205) an expansion area with a certain thickness starting from the front side at a depth of 0.5 pm - 3 pm, the expansion area having dopants,
• Aktivieren (206) der Dotierstoffe, • activating (206) the dopants,
• Erzeugen (207) einer Vielzahl von Gräben, die sich ausgehend von der Vorderseite des Halbleitersubstrats bis in die Epitaxieschicht erstrecken, wobei die Gräben eine geringere Tiefe aufweisen als die • Generating (207) a large number of trenches which, starting from the front side of the semiconductor substrate, extend into the epitaxial layer, wherein the trenches have a shallower depth than that
Feldabschirmgebiete, Field shielding areas,
• Aufbringen (208) von ersten Isolationsbereichen auf Grabenoberflächen der Gräben, • application (208) of first isolation areas on trench surfaces of the trenches,
• Erzeugen (209) von Gateelektroden, • Generation (209) of gate electrodes,
• Erzeugen (210) von zweiten Isolationsbereichen, die oberhalb der • Creation (210) of second isolation areas above the
Gatelektroden angeordnet sind, Gate electrodes are arranged,
• Erzeugen (211) einer ersten Metallschicht auf der Vorderseite des • Generating (211) a first metal layer on the front side of the
Halbleitersubstrats, und Semiconductor substrate, and
• Erzeugen (212) einer zweiten Metallschicht auf einer Rückseite des Halbleitersubstrats, wobei die Rückseite der Vorderseite gegenüberliegt. • Generating (212) a second metal layer on a rear side of the semiconductor substrate, the rear side being opposite the front side.
EP20728423.3A 2019-05-27 2020-05-18 Transistor cell having an implanted expansion region Withdrawn EP3977515A1 (en)

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Publication number Priority date Publication date Assignee Title
US5814858A (en) * 1996-03-15 1998-09-29 Siliconix Incorporated Vertical power MOSFET having reduced sensitivity to variations in thickness of epitaxial layer
JP3964819B2 (en) * 2003-04-07 2007-08-22 株式会社東芝 Insulated gate semiconductor device
JP2008016747A (en) 2006-07-10 2008-01-24 Fuji Electric Holdings Co Ltd Trench-mos silicon carbide semiconductor device and method for manufacturing the same
CN106558616B (en) * 2015-09-24 2019-11-12 丰田合成株式会社 Longitudinal type field effect transistor and power inverter
US20180366569A1 (en) * 2016-06-10 2018-12-20 Maxpower Semiconductor Inc. Trench-Gated Heterostructure and Double-Heterostructure Active Devices
JP2017224719A (en) * 2016-06-15 2017-12-21 サンケン電気株式会社 Semiconductor device
JP6830627B2 (en) * 2016-12-22 2021-02-17 国立研究開発法人産業技術総合研究所 Semiconductor devices and methods for manufacturing semiconductor devices
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