EP3966919A1 - On-time timer circuit with external clock for switching converter control - Google Patents
On-time timer circuit with external clock for switching converter controlInfo
- Publication number
- EP3966919A1 EP3966919A1 EP20785360.7A EP20785360A EP3966919A1 EP 3966919 A1 EP3966919 A1 EP 3966919A1 EP 20785360 A EP20785360 A EP 20785360A EP 3966919 A1 EP3966919 A1 EP 3966919A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- input node
- coupled
- time
- switching converter
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 46
- 238000010586 diagram Methods 0.000 description 32
- 230000008859 change Effects 0.000 description 5
- 230000009467 reduction Effects 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 4
- 238000012356 Product development Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0041—Control circuits in which a clock signal is selectively enabled or disabled
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
- H02M1/15—Arrangements for reducing ripples from dc input or output using active elements
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
Definitions
- an electrical system comprises a battery configured to provide an input supply voltage.
- the electrical system also comprises a switching converter coupled to the battery, where the switching converter circuitry includes a power switch.
- the electrical system also comprises a load coupled to an output of the switching converter.
- the electrical system also includes a control circuit coupled to the power switch.
- the control circuit comprises a switch driver circuit coupled to the power switch.
- the control circuit also comprises a summing comparator circuit configured to output a first control signal that indicates when to turn the power switch on.
- the control circuit also comprises an on-time timer circuit configured to output a second control signal separate from the first control signal. The second control signal is separate from the first control signal and is based on a latched external clock signal.
- a switching converter comprises a power switch and a control circuit coupled to the power switch.
- the control circuit comprises a switch driver circuit and a summing comparator circuit coupled to the switch driver circuit.
- the control circuit also comprises an on- time timer circuit coupled to the switch driver circuit.
- the on-time timer circuit comprises an up/down counter with a clock input node.
- the on-time timer circuit also comprises a latch with an input coupled to an external clock signal and with an output coupled to the clock input node.
- the on-time timer circuit also comprises an on-time capacitor array with a control terminal coupled an output of the up/down counter.
- a switching converter controller comprises an on-time timer circuit coupled to the switch driver circuit.
- the on-time timer circuit comprises an up/down counter with a clock input node.
- the on-time timer circuit also comprises a latch with an input coupled to an external clock signal and with an output coupled to the clock input node.
- the on-time timer circuit also comprises an on-time capacitor array with a control terminal coupled an output of the up/down counter.
- FIG. 1 is a schematic diagram showing a switching converter with a constant on-time controller
- FIG. 2 is a diagram showing an on-time timer circuit for a switching converter with a constant on-time controller
- FIG. 3 is a timing diagram showing VOU T and I I waveforms of a switching converter with a constant on-time controller in forced continuous conduction mode (FCCM);
- FIG. 4 is a timing diagram showing simulated waveforms of a switching converter with a constant on-time controller in FCCM;
- FIG. 5 is a timing diagram showing simulated waveforms of a switching converter with a constant on-time controller in discontinuous conduction mode (DCM);
- DCM discontinuous conduction mode
- FIG. 6 is a diagram showing another on-time timer circuit for a switching converter with a constant on-time controller in FCCM;
- FIG. 7 is a timing diagram showing simulated waveforms of a switching converter with the on-time timer circuit in FCCM;
- FIG. 8 is a diagram showing another on-time timer circuit for a switching converter with a constant on-time controller in FCCM;
- FIG. 9 is a timing diagram showing simulated waveforms of the switching converter with the constant on-time controller of FIG. 8 in FCCM;
- FIG. 10 is a diagram showing an on-time timer circuit for a switching converter with a constant on-time controller in DCM;
- FIG. 11 is a timing diagram showing simulated waveforms of the switching converter with the constant on-time controller of FIG. 10 in DCM.
- FIG. 12 is a block diagram of an electrical system.
- the constant on-time control is based in part on an on-time timer circuit with an up/down counter having a latched clock input.
- the latched clock input of the up/down counter is based on an external clock signal.
- An external clock may encompass a clock signal independent of a converter’s switching frequency (e.g., the frequency at a switching converter’s switch node).
- the on-time timer circuit may use a low- side switch blanking time signal to ensure an on-time capacitor array finishes discharging to zero.
- the latch used to provide a latched clock input to the up/down counter of the on- time timer circuit corresponds to a D-type (D) flip-flop, where the low-side switch blanking time signal is one of the inputs to the D flip-flop to avoid abrupt changes to the on-time and thus smooth on-time control changes are achieved.
- D D-type
- the constant on-time control options of some examples abrupt on-time changes are avoided and better load/line transient response is achieved.
- the constant on-time control options of some examples avoid randomly changing the on-time during line/load transients or power on/off events.
- FIG. 1 is a schematic diagram showing a switching converter with a constant on-time controller.
- the constant on-time controller corresponds to an on-time timer circuit and other components that determine when a high-side switch (Ml) is turned on.
- the switching converter includes Ml and a low-side switch (M2), where respective high-side and low- side drivers are used to generate drive signals for Ml and M2.
- the timing of the drive signals provided by the high-side and low-side drivers are based on respective control signals input into the high-side and low-side drivers.
- the control signals input into the high-side and low-side drivers are based on the operations of various circuits represented in FIG.
- a current information generator circuit e.g., with resistors Rsl and Rs2, and with capacitors Csl and Cs2
- GM1 transconductance stage
- GM1 transconductance stage
- PWM pulse-width modulation
- ZC zero crossing
- various logic gates e.g., AND gates, OR gates, or inverters. While the on-time of Ml is a function of various signals (the output of the loop comparator, the output of the on-time timer circuit, the output of the minimum off-time timer circuit), the constant on-time controller of FIG. 1 corresponds to the on-time timer circuit.
- the on-time timer circuit is configured to generate a reset signal (SHOT) to reset the PWM latch so as to switch off Ml through the high-side driver when an on- time of Ml expires.
- the on-time of the on-time timer circuit is based on charging an on-time capacitor (CON) with a current (ION) from a current source until a voltage across CON reaches a reference voltage (VON) that is proportional to the output voltage (VOUT) of the switching converter.
- the charging is triggered based on voltage level at the switch node (SW).
- FIG. 2 is a diagram showing an on-time timer circuit 200 for a switching converter with a constant on-time controller (see e.g., the switching converter 100 in FIG. 1).
- the on-time timer circuit 200 includes an up/down counter 202, an on-time capacitor array 204, a comparator 206, and a resistor (RON) ⁇
- functions such as ripple reduction are realized for some applications (e.g., when the load is light).
- ripple of VOUT is reduced by increasing the system switching frequency through adjustment of the on-time of Ml .
- the on-time capacitor array 204 includes a plurality of on-time capacitors coupled in parallel.
- the up/down counter 202 controls a capacitance of the on- time capacitor array 204 based on the clock signal (CLK).
- CLK clock signal
- the up/down counter 202 is configured to generate a selection signal (Q ⁇ 5:0>) to selectively switch on or off respective switches in the on-time capacitor array 204 to adjust the total capacitance so as to adjust the on- time of Ml, where Q ⁇ 5:0> is adjusted step by step based on CLK.
- CLK is provided externally (e.g., by an oscillator), when adjusting capacitance of the on-time capacitor array 204 is needed.
- FIG. 3 is a timing diagram 300 showing VOU T and I I (inductor current) waveforms of a switching converter with a constant on-time controller (see e.g., the switching converter 100 in FIG. 1) in forced continuous conduction mode (FCCM).
- FCCM forced continuous conduction mode
- an on-time timer circuit e.g., the on-time timer circuit 200 in FIG. 2 with the clock signal (e.g., CLK) of an up/down counter is provided by an external independent clock to adjust the capacitance of an on-time capacitor array so as to control the on-time.
- CLK clock signal
- the external independent clock functions as a frequency lock that locks the switching converter to its desired system switching frequency.
- the up/down counter uses the external clock directly, abrupt changes to the on-time occur as represented in the timing diagram 300, where abrupt changes in the on-time during transients results in poor load transient performance.
- FIG. 4 is a timing diagram 400 showing simulated waveforms of a switching converter with a constant on-time controller (see e.g., the switching converter 100 in FIG. 1) in FCCM.
- waveforms for an external clock signal EXTERNAL CLK
- a counter output signal e.g., labeled“COUNTER”, where Q ⁇ 5:0> is an example
- I L a ramp on signal
- Ramp on a ramp on signal
- FIG. 5 is a timing diagram 500 showing simulated waveforms of a switching converter with a constant on-time controller (see e.g., the switching converter 100 in FIG. 1) in discontinuous conduction mode (DCM).
- DCM discontinuous conduction mode
- waveforms for the input supply voltage (VIN), VOUT, and U of switching converter with a constant on-time controller operated in a pulse skip mode (PSM) or DCM are represented.
- PSM pulse skip mode
- an on-time timer circuit e.g., the on-time timer circuit 200 in FIG.
- an up/down counter uses a system driving signal (e.g., the M2 on signal) to control the external clock and on-time capacitor array to achieve ripple reduction and out of audio (OOA) functions in DCM.
- the OOA function refers to adjusting the system switching frequency to be out of the audible range.
- the up/down counter adjusts the on-time by adjusting the total capacitance of the on-time capacitor array in a step down or step up mode, the duration of each step is based on a frequency of the system driving signal, which causes a long period of regulation time.
- on-time timer circuits e.g., the on-time timer circuit 200 in FIG.
- on-time timer circuits e.g., the on-time timer circuit 200 in FIG. 2 may suffer from a long regulation time, where the regulation time cannot be adjusted.
- FIG. 6 is a diagram showing another on-time timer circuit 600 for a switching converter with a constant on-time controller (e.g., replacing the on-time timer in the switching converter 100 in FIG. 1) in FCCM.
- LS COMP EN is a signal indicating the completion of a low-side switch blanking time, which corresponds to the minimum off-time of M2.
- LS COMP EN is provided to the data (D) input of a D flip flop 608.
- an external clock signal (EXTERNAL CLK) is provided to the clock terminal of the D flip flop 608 through a delay unit 610.
- the delay unit 610 has a duty cycle no less than 50% and has a frequency lower than the system switching frequency (the frequency of switching at SW). Also, in some examples, the delay unit 610 is configured to avoid logic error (sometimes referred to as race and competition).
- EXTERNAL CLK is also provided to a reset terminal of the D flip flop 608 such that the D flip flop 608 is reset when EXTERNAL CLK is de-asserted.
- the output of the D flip flop 608 is provided as a new clock of the up/down counter 602. Therefore, the new clock for the up/down counter 602 is only asserted when LS COMP EN is high so as to avoid capacitance change of the on-time capacitor array 604 during the on-time of Ml.
- LS COMP EN Using the completion of low side switch blanking time (indicated by LS COMP EN) can ensure the on-time capacitors of the on-time capacitor array 604 are completely discharged to zero.
- the capacitance of the on-time capacitor array 604 is used to adjust a voltage value (Ramp on) at the positive input of the comparator 606, where the comparator 606 provides SHOT based on a comparison of Ramp on with VON ⁇
- FIG. 7 is a timing diagram 700 showing simulated waveforms of a switching converter with the on-time timer circuit 600 in FCCM.
- waveforms for a counter output signal e.g., labeled“COUNTER”, where Q ⁇ 5:0> is an example
- an external clock signal (EXTERNAL CLK)
- a new clock signal (NEW CLK)
- I L a ramp on signal
- Ramp on a low- side switch blanking time completion signal
- LS COMP EN low- side switch blanking time completion signal
- EXTERNAL CLK cannot trigger the up/down counter every cycle. If the rising edge of EXTERNAL CLK happens when LS_ COMP EN is low, the output of the D flip flop 608 is low.
- FIG. 8 is a diagram showing another on-time timer circuit 800 (e.g., replacing the on-time timer in the switching converter 100 in FIG. 1) for a switching converter with a constant on-time controller in FCCM.
- the on-time timer circuit 800 includes an up/down counter 802 configured to provide a control signal (e.g., Q ⁇ 5:0>) to an on-time capacitor array 804.
- the capacitance of the on-time capacitor array 804 is used to adjust the value of Ramp on at the positive input of the comparator 806, where the comparator 806 provides SHOT based on a comparison of Ramp on with VON ⁇
- the on-time timer circuit 800 varies with regard to how NEW CLK is provided to an up/down counter. More specifically, in the example of FIG. 8, EXTERNAL CLK is provided to the data (D) input of a D flip flop 808 and is sampled by LS COMP EN, which has a frequency much higher than the frequency of EXTERNAL CLK. Therefore, the on-time timer circuit 800 can achieve a higher regulation speed compared to the on- time timer circuit 600 in FIG. 6.
- FIG. 9 is a timing diagram 900 showing simulated waveforms of the switching converter with the constant on-time controller of FIG. 8 in FCCM.
- waveforms for a counter output signal e.g., labeled“COUNTER”, where Q ⁇ 5:0> is an example
- an external clock signal EXTERNAL CLK
- a new clock signal NW CLK
- I L I L
- Ramp on a ramp on signal
- LS COMP EN low-side switch blanking time completion signal
- the left portion 902A and the right portion 902B of FIG. 9 illustrate that NEW CLK is asserted by LS_COMP_EN when Ml is off regardless whether EXTERNAL CLK is asserted when Ml is off or on.
- FIG. 10 is a diagram showing an on-time timer circuit 1000 for a switching converter with a constant on-time controller in DCM mode.
- the on-time timer circuit 1000 includes an up/down counter 1002 configured to provide a control signal (e.g., Q ⁇ 5:0>) to an on- time capacitor array 1004.
- the capacitance of the on-time capacitor array 1004 is used to adjust the value of Ramp on at the positive input of the comparator 1006, where the comparator 1006 provides SHOT based on a comparison of Ramp on with VON ⁇
- LS COMP EN or a DCM signal is forwarded to the data (D) input of a D flip flop 1008 via an OR gate 1012.
- an external clock signal (EXTERNAL CLK) is provided to the clock terminal of the D flip flop 1008 through a delay unit 1010.
- the delay unit 1010 has a duty cycle no less than 50% and has a frequency lower than the system switching frequency (the frequency of switching at SW). Also, in some examples, the delay unit 1010 is configured to avoid race and competition.
- EXTERNAL CLK is also provided to a reset terminal of the D flip flop 1008 such that the D flip flop 1008 is reset when EXTERNAL CLK is de-asserted.
- the output of the D flip flop 1008 is provided as a new clock of the up/down counter 1002. Therefore, the new clock for the up/down counter 1002 is only asserted when LS COMP EN or DCM is high so as to avoid capacitance change of the on-time capacitor array 604 during the on-time of Ml.
- LS COMP EN the completion of low side switch blanking time (indicated by LS COMP EN) can ensure the on-time capacitors of the on-time capacitor array 604 are completely discharged to zero.
- the up/down counter 1002 can be enabled in a continuous working mode as well as a discontinuous working mode. Similar to the on-time timer circuit 600 of FIG. 6, the on-time timer circuit 1000 uses EXTERNAL CLK to adjust the capacitance of an on-time capacitor array (e.g., the on-time capacitor array 1004), therefore the regulation time can be controlled based on the frequency of EXTERNAL CLK and a reduced regulation time is achieved. In this manner, the on- time timer circuit 1000 can realize an OO A function in less regulation time compared to the on- time timer circuit 600 of FIG. 6.
- FIG. 11 is a timing diagram 1100 showing simulated I I waveforms with and without a on-time timer circuit in DCM. As represented in the timing diagram 1100, many examples realize OOA function in less regulation time.
- FIG. 12 is a block diagram of an electrical system 1200.
- the electrical system 1200 includes switching converter circuitry 1250 and a control circuit 1260 for one or more power switches (e.g., SI or S2) of the switching converter circuitry 1250.
- the switching converter circuitry 1250 corresponds to a buck converter topology with a high-side switch (SI), a low-side switch (S2), an inductor (L), and an output capacitor (COUT) ⁇
- the switching converter circuitry 1250 could have a boost converter topology, or another switching converter topology.
- SI and S2 are coupled between a battery 1240 configured to provide V IN and a ground node 1256.
- a first end of L is coupled to a switch node 1252 between SI and S2.
- a second end of L is coupled to an output node 1254.
- COUT and a load (RLOAD) are coupled in parallel between the output node 1254 and a ground node.
- I L inductor current
- I off, S2 on I L ramps down.
- the timing of the first and second phases is controlled by the control circuit 1260. As the V IN provided by the battery 1240 drops, the control circuit 1260 adjusts the timing of the first and second phases to account this change (e.g., by increasing the total amount of first phase time subject to certain limits such as a minimum off-time).
- the timing of the first phase and the second phase are a function of various signals including a first control signal (LOOPRAW) output from a summing comparator circuit 1270 and a second control signal (SHOT) output from an on-time timer circuit 1210.
- the on-time timer circuit 1210 provides SHOT based on an up/down counter with a latched clock input (see e.g., the on-time timer circuit 600 in FIG. 6, the on-time timer circuit 800 in FIG. 8, the on-time timer circuit 1000 in FIG. 10).
- the latched clock input of the up/down counter is based in part on an external clock (e.g., External CLK in FIGS. 6, 8, and 10).
- LOOPRAW indicates when to turn SI on (i.e., LOOPRAW is used to generate a switch on signal, S ON).
- SHOT indicates when to turn SI off. More specifically, S ON is output from an AND gate 1208 that receives LOOPRAW and a minimum off-time signal (CONT) to ensure S ON is off for a minimum off-time. Thus, when LOOPRAW and CONT are high, S ON is high. Otherwise, when either or both of LOOPRAW or CONT are low, S ON is low.
- CONT is provided by a minimum off-time signal generator (not shown). Often the minimum off-time is a fixed value in an IC specification. When the minimum off-time of the low-side switch arrives, CONT is asserted.
- S ON is provided to a latch 1232.
- the latch 1232 is coupled to is part of (as shown) a switch driver circuit 1230 configured to provide a high-side drive signal (HG) to SI and to provide a low-side drive signal (LG) to S2.
- the Q and QN outputs of the latch 1232 can be provided to a driver circuit 1234, which is configured to provide sufficient current to drive SI and S2.
- the switch driver circuit 1230 directs the switching converter circuitry 1250 to transition to phase 2 (SI off, S2 on).
- the latch 1232 is an SR latch with a set (S) input node and a reset (R) input node, where the R input node is configured to receive SHOT from the on-time timer circuit 1210.
- the summing comparator circuit 1270 comprises a comparator 1202 that compares a feedback voltage (VFB) with a target reference voltage (VREF). More specifically, the positive input node of the comparator 1202 is configured to receive VREF from a voltage reference source 1207. Meanwhile, the negative input node of the comparator 1202 is configured to receive VFB (e.g., via a feedback loop that connects to the output node 1254 of the switching converter circuitry 1250). Also, VREF may be modified based on a ramp compensation signal (Vramp) that is selectively applied to VREF by an adder circuit 1204. Also, VFB may be modified based on a ripple signal (Vripple) that is applied to VFB by the adder circuit 1206.
- Vramp ramp compensation signal
- VFB may be modified based on a ripple signal (Vripple) that is applied to VFB by the adder circuit 1206.
- an electrical system (e.g., the electrical system 1200 in FIG. 12) includes a battery (e.g., the battery 1240 in FIG. 12) configured to provide an input supply voltage (V IN ).
- the electrical system also includes a switching converter (e.g., the switching converter circuitry 1250 in FIG. 12) coupled to the battery, where the switching converter includes a power switch (e.g., SI or S2 in FIG. 12).
- the electrical system also includes a load (e.g., RLOAD in FIG. 12) coupled to an output of the switching converter.
- the electrical system also includes a control circuit 1260 coupled to the power switch.
- the control circuit includes a switch driver circuit (e.g., the switch driver circuit 1230 in FIG.
- the control circuit also includes summing comparator circuit (e.g., the summing comparator circuit 1270 in FIG. 12) configured to output a first control signal (e.g., LOOPRAW in FIG. 12) that indicates when to turn the power switch on.
- the control circuit also includes an on-time timer circuit (e.g., the on-time timer circuit 1210 in FIG. 12) configured to output a second control signal (e.g., SHOT in FIG. 12) separate from the first control signal, where the second control signal is based on a latched external clock signal (e.g., EXTERNAL CLK in FIGS. 6, 8, or 10).
- a latched external clock signal e.g., EXTERNAL CLK in FIGS. 6, 8, or 10
- the on-time timer circuit includes an up/down counter (e.g., the up/down counters in FIGS. 6, 8, and 10) and a latch (e.g., the D flip flop in FIGS. 6, 8, and 10), where an output of the latch is coupled to a clock input of the up/down counter.
- the on-time timer circuit further comprises a delay circuit (the delay unit 610 in FIG. 6, or the delay unit 1010 in FIG. 10), and where the latch comprises a D flip flop (e.g., the D flip flop 608 in FIG. 6) having a data input node, a clock input node coupled to an output of the delay circuit, and a reset input node.
- the data input node of the D flip flop is configured to receive a low-side switch blanking time completion signal (e.g., LS COMP EN in FIGS. 6, 8, and 10). Also, the external clock signal is coupled to an input of the delay circuit and to the reset input node of the D flip flop.
- a low-side switch blanking time completion signal e.g., LS COMP EN in FIGS. 6, 8, and 10.
- the external clock signal is coupled to an input of the delay circuit and to the reset input node of the D flip flop.
- the on-time timer circuit also includes an OR gate (e.g., the OR gate 1012 in FIG. 10) with an output coupled to the data input node, where the OR gate is configured to receive the low-side switch blanking time completion signal and a DCM signal as inputs.
- the latch includes a D flip flop (e.g., the D flip flop 808 in FIG. 8) having a data input node, a clock input node, and a reset input node, where the data input node and the reset input node are configured to receive the external clock signal, and where the clock input node is configured to receive a low-side switch blanking time completion signal (e.g., LS COMP EN in FIGS. 6, 8, and 10).
- a low-side switch blanking time completion signal e.g., LS COMP EN in FIGS. 6, 8, and 10
- the on-time timer circuit also includes a comparator (e.g., the comparator in FIGS. 6, 8, and 10).
- the on-time timer circuit also includes an on- time capacitor array (e.g., the on-time capacitor array in FIGS. 6, 8, and 10) with a control terminal, a first terminal, and a second terminal, where the control terminal is coupled to an output of the up/down counter, where the first terminal is coupled to an input of the comparator, and where the second terminal is coupled to a ground node.
- the external clock is provided by an external source is independent of a converter’s switching frequency.
- a switching converter (e.g., an integrated circuit, a chip, or printed circuit board with integrated circuit components and/or discrete components) includes a power switch (e.g., SI or S2 in FIG. 12) and a control circuit (e.g., control circuit 1260 in FIG. 12) coupled to the power switch.
- the control circuit includes a switch driver circuit (e.g., the switch driver circuit 1230 in FIG. 12) and a summing comparator circuit (e.g., the summing comparator circuit 1270 in FIG. 12) coupled to the switch driver circuit.
- the control circuit also includes an on-time timer circuit (e.g., the on-time timer circuit 1210 in FIG.
- the on-time timer circuit includes an up/down counter (e.g., the up/down counter of FIGS. 6, 8, and 10) with a clock input node.
- the on-time timer circuit also includes a latch (e.g., the D flip flop in FIGS. 6, 8, or 10) with an input coupled to an external clock signal (e.g., EXTERNAL CLK in FIGS. 6, 8, or 10) and with an output coupled to the clock input node.
- the on-time timer circuit also includes an on-time capacitor array (e.g., the on-time capacitor array in FIGS. 6, 8, or 10) with a control terminal coupled an output of the up/down counter.
- the on-time timer circuit also includes a delay circuit (e.g., the delay until 610 in FIG. 6, or the delay unit 1010 in FIG. 10), and the latch includes a D flip flop having: a data input node, a clock input node coupled to an output of the delay circuit, and a reset input node (see e.g., the D flip flop 608 of FIG. 6).
- the data input node is configured to receive a low-side switch blanking time completion signal (e.g., LS COMP EN in FIG. 6), and the external clock signal is coupled to an input of the delay circuit and to the reset input node.
- a low-side switch blanking time completion signal e.g., LS COMP EN in FIG. 6
- the on-time timer circuit also includes comprises an OR gate (e.g., the OR gate 1012 in FIG. 10) with an output coupled to the data input node, and the OR gate is configured to receive the low-side switch blanking time completion signal and a DCM signal as inputs.
- the latch includes a D flip flop (e.g., the D flip flop 808 in FIG. 8) having a data input node, a clock input node, and a reset input node, where the data input node and the reset input node are configured to receive the external clock signal, and where the clock input node of the D flip flop is configured to receive a low-side switch blanking time completion signal.
- the external clock signal is provided by an external source independent of a converter’s switching frequency.
- the switching converter also includes an AND gate (e.g., the AND gate 1208 in FIG. 12), where a first input node of the AND gate is coupled to an output of the summing comparator circuit (e.g., the summing comparator circuit 1270 in FIG. 12), and where a second input node of the AND gate is coupled to a minimum off-time control signal (e.g., CONT in FIG. 12).
- the switch driver circuit comprises an SR latch (e.g., the SR latch 1232 in FIG.
- the OR gate is configured to receive a maximum on-time control signal (e.g., HTO in FIG. 12) as an input.
- the on-time timer circuits are parts of a switching converter controller (e.g., an integrated circuit or chip) designed to provide the control signals (e.g., HG and LG) for use by power switches (e.g., SI and S2) of a switching converter.
- a switching converter controller e.g., an integrated circuit or chip
- the control signals e.g., HG and LG
- power switches e.g., SI and S2
- different on- time timer circuits see e.g., FIGS 6, 8, 10) are possible, and are compatible with other control options of a control circuit (e.g., the control circuit 1260 in FIG. 12).
- the technical advantages of the on-time timer circuit options includes, but are not limited to, resolution of issues such as abrupt on-time changes. In some examples this is accomplished by adjustment of an on-time capacitor array based on the completion of low side switch blanking time signal (e.g., LS COMP EN). This solution can realize ripple reduction, OOA, and frequency lock functions more efficiently, which provides a more competitive switching converter and related products.
- the on-time timer options may be used for all power converters with constant on-time control.
- the term“couple” or“couples” means either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections.
- the recitation“based on” means“based at least in part on.” Therefore, if X is based on Y, X may be a function of Y and any number of other factors.
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US201962827638P | 2019-04-01 | 2019-04-01 | |
US16/685,357 US10969808B2 (en) | 2019-04-01 | 2019-11-15 | On-time timer circuit with external clock for switching converter control |
PCT/US2020/026084 WO2020205918A1 (en) | 2019-04-01 | 2020-04-01 | On-time timer circuit with external clock for switching converter control |
Publications (2)
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EP3966919A1 true EP3966919A1 (en) | 2022-03-16 |
EP3966919A4 EP3966919A4 (en) | 2022-08-24 |
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EP20785360.7A Pending EP3966919A4 (en) | 2019-04-01 | 2020-04-01 | On-time timer circuit with external clock for switching converter control |
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US (1) | US10969808B2 (en) |
EP (1) | EP3966919A4 (en) |
WO (1) | WO2020205918A1 (en) |
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US11469669B2 (en) * | 2020-01-31 | 2022-10-11 | Texas Instruments Incorporated | Methods and circuitry to detect PFM mode entry in wide duty range DC converter |
US20220209669A1 (en) * | 2020-12-29 | 2022-06-30 | Texas Instruments Incorporated | DC-DC Converter with Out-of-Audio Circuit |
US11552633B1 (en) * | 2021-10-15 | 2023-01-10 | Stmicroelectronics S.R.L. | Driver circuit with enhanced control for current and voltage slew rates |
Family Cites Families (13)
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US6946753B2 (en) | 2002-11-14 | 2005-09-20 | Fyre Storm, Inc. | Switching power converter controller with watchdog timer |
US7131092B2 (en) | 2004-12-21 | 2006-10-31 | Via Technologies, Inc. | Clock gating circuit |
CN102460338B (en) | 2009-05-19 | 2014-08-13 | 最大输出可再生能源公司 | Architecture for power plant comprising clusters of power-generation devices |
US8407528B2 (en) | 2009-06-30 | 2013-03-26 | Texas Instruments Incorporated | Circuits, systems, apparatus and processes for monitoring activity in multi-processing systems |
TWI400864B (en) | 2010-07-26 | 2013-07-01 | Richtek Technology Corp | Control circuit and method for reducing output ripple in constant on-time switching regulator |
TWI418132B (en) | 2011-02-14 | 2013-12-01 | Richtek Technology Corp | Frequency control circuit and method for a ripple regulator |
KR102194973B1 (en) * | 2014-01-28 | 2020-12-24 | 삼성전자주식회사 | Voltage converter and power management device including the same |
KR102452492B1 (en) * | 2015-05-06 | 2022-10-07 | 삼성전자주식회사 | Voltage converter and power management device including the same |
US20170099011A1 (en) | 2015-10-02 | 2017-04-06 | Advanced Charging Technologies, LLC | Electrical circuit for delivering power to consumer electronic devices |
US10063144B2 (en) * | 2016-10-26 | 2018-08-28 | Taiwan Semiconductor Manufacturing Company Ltd. | Multiphase buck converter and method for operating the same |
US10381919B2 (en) | 2016-12-14 | 2019-08-13 | Infineon Technologies Ag | Rectifier device with safety threshold |
US10581416B2 (en) * | 2018-06-26 | 2020-03-03 | Texas Instruments Incorporated | External and dual ramp clock synchronization |
US10770963B2 (en) * | 2018-10-30 | 2020-09-08 | Texas Instruments Incorporated | DC-DC converter having a switch on-time control loop with a switched-capacitor circuit for error-based adjustment |
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2019
- 2019-11-15 US US16/685,357 patent/US10969808B2/en active Active
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2020
- 2020-04-01 EP EP20785360.7A patent/EP3966919A4/en active Pending
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EP3966919A4 (en) | 2022-08-24 |
WO2020205918A1 (en) | 2020-10-08 |
US20200310475A1 (en) | 2020-10-01 |
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