TWI418132B - Frequency control circuit and method for a ripple regulator - Google Patents

Description

Frequency control circuit and method for chopper regulator

The present invention relates to a frequency control circuit for a ripple regulator, and more particularly to a frequency control circuit that does not change the frequency due to load changes.

1 is a conventional chopper regulator, which operates as shown in FIG. 2. When the feedback signal FB having a proportional relationship with the output voltage Vout is lower than the reference voltage Vref, the output of the comparator 24 is shown as time t1. Comp_out is switched from the high level to the low level, the control circuit 22 thus sends the signal S1, and the click circuit 12 generates the control signal S2 having the fixed time Ton according to the signal S1 and the fixed time Ton set by the fixed time generator 10, thereby The driver 16 triggers the control signal UG having a fixed time Ton to turn the upper bridge switch M1 on for a fixed time Ton, while the inverter 14 generates a control signal S3 according to the control signal S2 to the driver 18 to turn off the lower bridge switch M2 (turn) Off) Fixed time Ton. After the fixed time Ton ends, the upper bridge switch M1 is turned off and the lower bridge switch M2 is turned on until the feedback signal FB is again lower than the reference voltage Vref. Since the upper bridge switch M1 of the chopper regulator is turned on for a fixed time Ton each time, the chopper regulator is also referred to as a constant on-time switching regulator. Conversely, if the upper bridge switch M1 is turned off for a fixed time each time, the chopper regulator is referred to as a fixed off-time switching regulator.

The chopper regulator of Figure 1 has several advantages over the pulse width modulation (PWM) regulator: (1) the control architecture is simple, no error amplifier is required; and (2) fast transient response. However, the chopper regulator turns on the upper bridge switch M1 when the feedback signal FB is lower than the reference voltage Vref, unlike the PWM regulator having an internal oscillator to control when the upper bridge switch is turned on, so the chopper regulator of FIG. Not a fixed frequency architecture.

As shown in FIG. 3, in order to enable the chopper regulator to achieve a fixed frequency, the fixed time adjustment circuit 26 generally detects the input voltage Vin and the output voltage Vout and adjusts the fixed time Ton accordingly. 4 shows the fixed time adjustment circuit 26 of FIG. 3, wherein the current source 28 is connected to the capacitor C and generates a charging current I1=K×Vin according to the input voltage Vin, wherein K is a constant, and the switch SW1 is connected in parallel with the capacitor C to control the capacitor C. Charge and discharge to generate voltage V1, comparator 30 compares voltage V1 and output voltage Vout to determine fixed time

Ton=(C/K)×(Vout/Vin). Formula 1

The chopper regulator of Fig. 3 is in an ideal state, when the upper bridge switch M1 is turned on, as shown in time t2 to t3 of Fig. 5, the phase node voltage Phs on the phase node between the upper and lower bridge switches M1 and M2 is equal to Vin, when the lower bridge switch M2 is turned on, as shown in time t3 to t4 of FIG. 5, the phase node voltage Phs is equal to GND=0, and the output voltage Vout is equal to the average value of the phase node voltage Phs, so

Vout=Vin×D=Vin×(Ton/T), Equation 2

Where T is the period of the control signal UG, and D=Ton/T is the duty cycle ratio (duty). According to formula 2, it can be derived

T=Ton×(Vin/Vout), Equation 3

Substituting the formula 1 into the formula 3 can obtain the period T=C/K. Therefore, as long as the values of C and K are controlled, the operating frequency of the chopper regulator can be controlled. Similarly, as long as C and K are constant values, the chopping is performed. The operating frequency of the regulator is fixed.

However, the actual high and low voltages of the phase node voltage Phs are not Vin and 0. The high and low points of the phase node voltage Phs are affected by the load of the chopper regulator and become Vin-(IL×Ron_UG) and -IL x Ron_LG, where IL is the load current, Ron_UG is the conduction resistance of the upper bridge switch M1, and Ron_LG is the conduction resistance of the lower bridge switch M2. In other words, the operating frequency of the chopper regulator of Figure 3 will be affected by the load. Under different loads, the operating frequency will shift, especially when the load and conduction resistance values Ron_UG and Ron_LG are large. Case.

In order to improve the problem, U.S. Patent No. 6,774,611 proposes a method of using a Phase Locked Loop (PLL) to stabilize the operating frequency, which can improve the transient response, but the use of the PLL causes a significant increase in cost. Another method is proposed by U.S. Patent No. 7,508,180, which utilizes an error amplifier to stabilize the operating frequency to prevent the operating frequency from being affected by the load, but when the system enters the power saving mode, the method will produce an erroneous output signal due to a dip in the operating frequency. A fixed time Ton that produces an error will increase the abnormality of the fixed time Ton, causing the operating frequency to further decrease, and the chopping voltage may be too large, causing a problem.

One of the objects of the present invention is to provide a frequency control circuit for a chopper regulator.

One of the objects of the present invention is to provide a frequency control circuit that does not change the frequency due to a change in load.

One of the objects of the present invention is to provide a frequency control circuit that improves the performance of the power saving mode.

According to the present invention, a chopper regulator frequency control circuit and method for detecting and quantifying an operating frequency of the chopper regulator generates a frequency sensing signal, and accordingly adjusting a power output stage for driving the chopper regulator The fixed time of the control signal, which in turn stabilizes the operating frequency. When the chopper regulator enters the power saving mode, the frequency control circuit and method keep the fixed time constant or change slowly to improve the performance in the power saving mode.

6 shows an embodiment of the frequency control circuit 32 of the present invention. The chopper regulator of FIG. 6 includes, in addition to the frequency control circuit 32, a click circuit 12, an inverter 14, and drivers 16 and 18 in the circuit of FIG. The power output stage 20, the control circuit 22, and the comparator 24. The frequency control circuit 32 includes a frequency sensor 34 and a time adjustment circuit 36. The frequency sensor 34 detects the phase node voltage Phs to detect the operating frequency of the chopper regulator and quantizes the detected operating frequency. The frequency sensing signal VC, the time adjusting circuit 36 determines the magnitude of the operating frequency according to the frequency sensing signal VC. When the operating frequency is too high, the time adjusting circuit 36 will lengthen the fixed time Ton to lower the operating frequency. When the operating frequency is too low, The time adjustment circuit 36 will shorten the fixed time Ton to increase the operating frequency. Therefore, as long as the frequency sensing signal VC is locked to a certain value, the operating frequency of the chopper regulator can be adjusted to be constant. In addition, when the chopper regulator enters the power saving mode, the time adjustment circuit 36 will not adjust the fixed time Ton or slowly adjust the fixed time Ton to avoid an erroneous fixed time Ton due to the dip in the operating frequency. In other embodiments, frequency sensor 34 may also obtain information on the operating frequency from any of the chopping regulator related signals of the operating frequency. The chopper regulator shown in Figure 6 is a fixed operating time switching regulator, and the frequency control circuit 32 of the present invention can also be used in a fixed off-time switching regulator.

In the time adjustment circuit 36 of FIG. 6, the comparator 38 compares the frequency sensing signal VC and the reference value Vref1 to generate a comparison signal Sc1, and the up/down counter 40 increases or decreases the count value Dc according to the comparison signal Sc1, and the digital analog converter 42 counts the count value. Dc is converted to voltage Vdac, current source 46 is connected to capacitor C2 for providing charging current I2, switch SW2 is connected in parallel with capacitor C2, and signal Ssw2 is controlled to charge and discharge capacitor C2 to generate voltage V2, and comparator 44 determines voltage Vdac and V2. Fixed time Ton. In this embodiment, the up-down counter 40 changes the count value Dc according to the control signal UG. Whenever the upper bridge switch M1 is turned on once, the up-down counter 40 changes the count value Dc by one bit. In other embodiments, other internals may also be provided. A periodic signal is sent to the up-down counter 40 in place of the control signal UG. When the frequency sensing signal VC is greater than the reference value Vref1, indicating that the operating frequency is too high, the up-down counter 40 will cause the count value Dc to rise by one bit, so that the voltage Vdac rises, thereby increasing the fixed time Ton, lowering the operating frequency, and vice versa, When the frequency sensing signal VC is less than the reference value Vref1, indicating that the operating frequency is too low, the up-down counter 40 lowers the count value Dc by one bit, so that the voltage Vdac falls to shorten the fixed time Ton, thereby increasing the operating frequency, and thus the time adjusting circuit 36 successively adjusts the frequency sensing signal VC to the reference value Vref1 and maintains stability. When the chopper regulator enters the power saving mode, since the up/down counter 40 changes the count value Dc one bit each time the upper bridge switch M1 is turned on once, the fixed time Ton will slowly change, thereby avoiding a sudden increase in the operating frequency. The performance of the electrical mode is reduced. Preferably, when the chopper regulator enters the power saving mode, the chopper regulator provides the sleep signal PSM to the up/down counter 40 to stop the up counter 40, and the up counter 40 stores the current count value Dc, thereby saving power During the mode, the count value Dc provided by the up-down counter 40 remains unchanged, so the voltage Vdac supplied from the digital analog converter 42 remains unchanged, and the fixed time Ton thus remains unchanged.

In the time adjustment circuit 36 of FIG. 6, the maximum value and the minimum value of the voltage Vdac are limited by the positive bias voltage VH and the negative bias voltage VL of the digital analog converter 42, respectively. In order to make the chopper regulator start up, the operating frequency can quickly reach the target value, the charging current I2 can be set proportional to the input voltage Vin, and the positive bias voltage VH and the negative bias voltage VL are all proportional to the output voltage Vout. Alternatively, the charging current I2 may be set to a constant value, and the positive bias voltage VH and the negative bias voltage VL are proportional to the ratio Vout/Vin or the duty cycle ratio D of the output voltage Vout and the input voltage Vin.

The frequency sensor 34 of Figure 6 can be implemented in a variety of ways. Figure 7 is an embodiment of a frequency sensor 34 that includes a click circuit 38 and a low pass filter consisting of resistors R3 and C1 (Low Pass). Filter; LPF) 40, the click circuit 38 triggers the short pulse signal Ssp according to the phase node voltage Phs, and the short pulse signal Ssp is filtered by the LPF 40 to generate the frequency sensing signal VC. When the operating frequency is high, the frequency of the phase node voltage Phs is also high, so the pulse wave of the short pulse signal Ssp appears densely, so the frequency sensing signal VC is large, and conversely, when the operating frequency is low, the phase The frequency of the node voltage Phs is also low, so the frequency sensing signal VC is small. In the embodiment of FIG. 7, the value of the frequency sensing signal VC is proportional to the operating frequency, but in other embodiments, the value of the frequency sensing signal VC may also be inversely proportional, linear, or non-linear to the operating frequency.

In the time adjustment circuit 36 of FIG. 6, only one comparator 38 is used to detect the frequency sensing signal VC. However, in other embodiments, multiple comparators may be used to detect the frequency sensing signal VC, as shown in FIG. The comparison comparator 48 compares the frequency sensing signal VC and the reference value Vref2 to generate a comparison signal Sc2, and the up/down counter 40 further increases or decreases the count value Dc according to the comparison signals Sc1 and Sc2 output by the comparators 38 and 48.

The above description of the preferred embodiments of the present invention is intended to be illustrative, and is not intended to limit the scope of the invention to the disclosed embodiments. It is possible to make modifications or variations based on the above teachings or learning from the embodiments of the present invention. The embodiments are described and illustrated in the practical application of the present invention in various embodiments, and the technical idea of the present invention is intended to be equivalent to the scope of the following claims. Decide.

10. . . Fixed time generator

12. . . Click circuit

14. . . inverter

16. . . driver

18. . . driver

20. . . Power output stage

twenty two. . . Control circuit

twenty four. . . Comparators

26. . . Fixed time adjustment circuit

28. . . Battery

30. . . Comparators

32. . . Frequency control circuit

34. . . Frequency sensor

36. . . Time adjustment circuit

38. . . Comparators

40. . . Lift counter

42. . . Digital analog converter

44. . . Comparators

46. . . Battery

48. . . Comparators

Figure 1 is a conventional chopper regulator;

Figure 2 shows the signal waveform of Figure 1;

Figure 3 is another conventional chopper regulator;

Figure 4 shows the fixed time adjustment circuit of Figure 3;

Figure 5 shows the waveform of the phase node voltage Phs under ideal conditions;

Figure 6 shows the frequency control circuit of the present invention;

Figure 7 shows an embodiment of the frequency sensor of Figure 6;

Figure 8 shows another embodiment of the time adjustment circuit of Figure 6.

12. . . Click circuit

14. . . inverter

16. . . driver

18. . . driver

20. . . Power output stage

twenty two. . . Control circuit

twenty four. . . Comparators

32. . . Frequency control circuit

34. . . Frequency sensor

36. . . Time adjustment circuit

38. . . Comparators

40. . . Lift counter

42. . . Digital analog converter

44. . . Comparators

46. . . Battery

Claims (11)

A frequency control circuit for a chopper regulator, the chopper regulator comprising a power output stage for converting an input voltage into an output voltage according to a control signal, and a click circuit for triggering a fixed time for the control signal, the frequency control circuit comprising: a sense of frequency a detector that detects a frequency of operation of the chopper regulator to generate a frequency sensing signal; and a time adjustment circuit that is coupled to the frequency sensor, and adjusts a width of the fixed time according to the frequency sensing signal to adjust the operating frequency, The time adjustment circuit includes: at least one first comparator connected to the frequency sensor, comparing the frequency sensing signal and a reference value; and a rising counter connected to the at least one first comparator, according to the at least one first comparator The output determines the count value; the digital analog converter is connected to the up/down counter, and the count value is converted into a first voltage; a capacitor; a current source connected to the capacitor to provide a charging current; and a switch connected in parallel with the capacitor to control the Capacitor charging and discharging to generate a second voltage; and a second comparator connecting the digital analog converter and the capacitor The first voltage and the second voltage to determine the width of a fixed time. The frequency control circuit of claim 1, wherein the frequency sensor comprises: a second click circuit, triggering a short pulse according to a phase node voltage of the power output stage And a low pass filter connected to the second click circuit to filter the short pulse signal to generate the frequency sensing signal. The frequency control circuit of claim 1, wherein the up/down counter stops counting when in the power saving mode. The frequency control circuit of claim 1, wherein the up/down counter stores the count value. The frequency control circuit of claim 1, wherein the charging current is proportional to the input voltage, and the digital analog converter limits a maximum value and a minimum value of the first voltage, the maximum value and the minimum value being proportional to the output voltage. The frequency control circuit of claim 1, wherein the digital analog converter limits a maximum value and a minimum value of the first voltage, and the maximum value and the minimum value are proportional to a ratio of the output voltage to the input voltage. A frequency control method for a chopper regulator, the chopper regulator includes a power output stage for converting an input voltage into an output voltage according to a control signal, and a click circuit triggering a fixed time for the control signal, the frequency control method comprising the following steps: (A) detecting the operating frequency of the chopper regulator to generate a frequency sensing signal; (B) comparing the frequency sensing signal with a reference value to generate a comparison signal; (C) determining a count value according to the comparison signal; (D) Converting the count value to a first voltage; (E) controlling charging and discharging of a capacitor to generate a second voltage; and (F) comparing the first voltage and the second voltage to determine a width of the fixed time to adjust the operating frequency. The frequency control method of claim 7, wherein the step A comprises: triggering the short pulse signal according to the phase node voltage of the power output stage; and filtering the short pulse signal to generate the frequency sensing signal. The frequency control method of claim 7, further comprising: storing the count value; and in the power saving mode, stopping adjusting the count value, and determining the first voltage according to the stored count value. The frequency control method of claim 7, further comprising: causing a charging current to charge the capacitor to be proportional to the input voltage; and limiting a maximum value and a minimum value of the first voltage, wherein the maximum value and the minimum value are proportional to the The output voltage. The frequency control method of claim 7, further comprising limiting a maximum value and a minimum value of the first voltage, wherein the maximum value and the minimum value are proportional to a ratio of the output voltage to the input voltage.