EP3931703A4 - Quad-channel dram - Google Patents

Quad-channel dram Download PDF

Info

Publication number
EP3931703A4
EP3931703A4 EP20763110.2A EP20763110A EP3931703A4 EP 3931703 A4 EP3931703 A4 EP 3931703A4 EP 20763110 A EP20763110 A EP 20763110A EP 3931703 A4 EP3931703 A4 EP 3931703A4
Authority
EP
European Patent Office
Prior art keywords
quad
channel dram
dram
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP20763110.2A
Other languages
German (de)
French (fr)
Other versions
EP3931703A1 (en
Inventor
Steven C. Woo
Torsten Partsch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc filed Critical Rambus Inc
Publication of EP3931703A1 publication Critical patent/EP3931703A1/en
Publication of EP3931703A4 publication Critical patent/EP3931703A4/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
EP20763110.2A 2019-02-28 2020-02-18 Quad-channel dram Pending EP3931703A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201962811903P 2019-02-28 2019-02-28
PCT/US2020/018634 WO2020176291A1 (en) 2019-02-28 2020-02-18 Quad-channel dram

Publications (2)

Publication Number Publication Date
EP3931703A1 EP3931703A1 (en) 2022-01-05
EP3931703A4 true EP3931703A4 (en) 2022-05-11

Family

ID=72239798

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20763110.2A Pending EP3931703A4 (en) 2019-02-28 2020-02-18 Quad-channel dram

Country Status (4)

Country Link
US (2) US11762787B2 (en)
EP (1) EP3931703A4 (en)
CN (1) CN113490926B (en)
WO (1) WO2020176291A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10915451B2 (en) * 2019-05-10 2021-02-09 Samsung Electronics Co., Ltd. Bandwidth boosted stacked memory
CN116569151A (en) * 2020-10-20 2023-08-08 美光科技公司 Multi-channel memory system
US20240211420A1 (en) * 2021-06-22 2024-06-27 Rambus Inc. Quad-channel memory module

Citations (3)

* Cited by examiner, † Cited by third party
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US6785782B1 (en) * 2001-09-10 2004-08-31 Rambus Inc. Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules
US20130194854A1 (en) * 2012-01-30 2013-08-01 Rambus Inc. Memory device comprising programmable command-and-address and/or data interfaces
WO2018204086A1 (en) * 2017-05-05 2018-11-08 Apple Inc. Dual-sided memory module with channels aligned in opposition

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US5959933A (en) * 1996-01-25 1999-09-28 Micron Technology, Inc. System for improved memory cell access
US6378056B2 (en) * 1998-11-03 2002-04-23 Intel Corporation Method and apparatus for configuring a memory device and a memory channel using configuration space registers
US7010642B2 (en) 2000-01-05 2006-03-07 Rambus Inc. System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices
US20050195629A1 (en) 2004-03-02 2005-09-08 Leddige Michael W. Interchangeable connection arrays for double-sided memory module placement
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US7539842B2 (en) * 2006-08-15 2009-05-26 International Business Machines Corporation Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables
EP2102867B1 (en) * 2006-12-14 2013-07-31 Rambus Inc. Multi-die memory device
US7679984B2 (en) 2007-04-03 2010-03-16 Qimonda North Amercia Corp. Configurable memory data path
WO2008127698A2 (en) 2007-04-12 2008-10-23 Rambus Inc. Memory system with point-to-point request interconnect
US8332680B2 (en) 2007-08-13 2012-12-11 Rambus Inc. Methods and systems for operating memory in two modes
US8683149B2 (en) 2008-07-23 2014-03-25 Rambus Inc. Reconfigurable memory controller
WO2010017015A1 (en) 2008-08-08 2010-02-11 Rambus Inc. Request-command encoding for reduced-data-rate testing
US8914589B2 (en) * 2008-09-22 2014-12-16 Infineon Technologies Ag Multi-port DRAM architecture for accessing different memory partitions
US8275936B1 (en) 2009-09-21 2012-09-25 Inphi Corporation Load reduction system and method for DIMM-based memory systems
US9183166B2 (en) * 2009-12-14 2015-11-10 Rambus Inc. Expandable asymmetric-channel memory system
KR101854251B1 (en) * 2010-11-30 2018-05-03 삼성전자주식회사 multi channel semiconductor memory device and semiconductor device having such memory device
US10902890B2 (en) 2012-06-22 2021-01-26 Intel Corporation Method, apparatus and system for a per-DRAM addressability mode
US9009362B2 (en) 2012-12-20 2015-04-14 Intel Corporation Variable-width command/address bus
WO2015048199A1 (en) * 2013-09-24 2015-04-02 Rambus Inc. High capacity memory system
US9826638B2 (en) 2013-10-15 2017-11-21 Rambus Inc. Load reduced memory module
WO2015070245A1 (en) 2013-11-11 2015-05-14 Rambus Inc. High capacity memory system using standard controller component
US10223299B2 (en) 2013-12-18 2019-03-05 Rambus Inc. High capacity memory system with improved command-address and chip-select signaling mode
WO2016089563A1 (en) 2014-12-01 2016-06-09 Rambus Inc. High performance, high capacity memory systems and modules
US11551735B2 (en) * 2015-03-11 2023-01-10 Rambus, Inc. High performance, non-volatile memory module
US9601182B2 (en) * 2015-05-08 2017-03-21 Micron Technology, Inc. Frequency synthesis for memory input-output operations
WO2017023508A1 (en) 2015-08-06 2017-02-09 Rambus Inc. High performance, high capacity memory modules and systems
US10141935B2 (en) * 2015-09-25 2018-11-27 Intel Corporation Programmable on-die termination timing in a multi-rank system
US10339072B2 (en) * 2016-04-01 2019-07-02 Intel Corporation Read delivery for memory subsystem with narrow bandwidth repeater channel
US10140223B2 (en) * 2016-06-27 2018-11-27 Qualcomm Incorporated System and method for odd modulus memory channel interleaving
US11068161B1 (en) * 2016-07-18 2021-07-20 Rambus Inc. Memory module with emulated memory device population
US10334334B2 (en) * 2016-07-22 2019-06-25 Intel Corporation Storage sled and techniques for a data center
US10762010B2 (en) 2016-11-16 2020-09-01 Rambus Inc. Multi-mode memory module and memory component
KR20180079811A (en) 2017-01-02 2018-07-11 삼성전자주식회사 Method of reconfiguring DQ pad of memory device and DQ pad reconfigurable memory device
US11256318B2 (en) * 2019-08-09 2022-02-22 Intel Corporation Techniques for memory access in a reduced power state

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6785782B1 (en) * 2001-09-10 2004-08-31 Rambus Inc. Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules
US20130194854A1 (en) * 2012-01-30 2013-08-01 Rambus Inc. Memory device comprising programmable command-and-address and/or data interfaces
WO2018204086A1 (en) * 2017-05-05 2018-11-08 Apple Inc. Dual-sided memory module with channels aligned in opposition

Also Published As

Publication number Publication date
CN113490926B (en) 2024-06-18
WO2020176291A1 (en) 2020-09-03
US11762787B2 (en) 2023-09-19
US20220156204A1 (en) 2022-05-19
EP3931703A1 (en) 2022-01-05
US20240028527A1 (en) 2024-01-25
CN113490926A (en) 2021-10-08

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RIC1 Information provided on ipc code assigned before grant

Ipc: G06F 12/02 20060101ALI20220407BHEP

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