EP3921984A1

EP3921984A1 - Circuit for the connection of a transducer

Info

Publication number: EP3921984A1
Application number: EP20704273.0A
Authority: EP
Inventors: Dennis KREISS; André Schmidt; Stefanie HEPPEKAUSEN
Original assignee: Elmos Semiconductor SE
Current assignee: Elmos Semiconductor SE
Priority date: 2019-02-08
Filing date: 2020-02-07
Publication date: 2021-12-15
Also published as: WO2020161282A1; CN113661688A; CN113661688B

Abstract

The invention relates to a circuit (IC) for controlling one or more ultrasonic transducers and/or one or more ultrasonic transmitters and/or one or more ultrasonic receivers. The circuit (IC) comprises various means for determining the application in which the ultrasonic transducer or the ultrasonic transmitter or the ultrasonic receiver is being used. The corresponding method is also claimed. The sensor can therefore determine, for example, whether the bus addresses are determined by means of connector coding or by means of a daisy-chain-like method.

Description

Circuit for connecting a transducer

This patent application adopts the priorities of the German patent applications 10 2019 103 221.0 from February 8, 2019, 10 2019 103 222.9 from February 8, 2019, 10 2019 103 223.7 from February 8, 2019 and 10 2020 100 425.7 from January 10, 2020 Claim, the contents of which are hereby incorporated by reference into the subject matter of the present patent application.

The invention relates to a circuit for connecting a transducer and in particular special for connecting an ultrasonic transducer element of an ultrasonic measuring system which emits ultrasonic signals and / or receives ultrasonic signals to a communication data bus which can have one of several configurations. The invention also relates to variously configured data bus systems with such circuits.

Current integrated circuits for the control of ultrasonic transducers in automotive ultrasonic systems usually only have one communication interface (e.g. a LIN bus interface, but other bus systems are also conceivable) to transfer data between a higher-level control unit (e.g. ECU) and replace one or more ultrasonic sensors. In this case, the ECU functions as a bus master and is responsible for both communication and processing of the individual ultrasonic measurements at system level.

There are also ultrasonic systems in which the individual sensors communicate with each other and process the data. LIN communication or another bus protocol can also be used here. A specially selected sensor takes over (partial) tasks of the classic control unit and communicates already evaluated results or only controls a loudspeaker / buzzer or generally a (e.g. warning) display unit (optical, graphic) to show the driver the distance to you Signal obstacle.

Fig. La shows as a block diagram such an ultrasonic system as a block diagram based on a currently common LIN bus system according to the prior art.

Fig. Lb shows as a block diagram such an ultrasonic system as a block diagram on the basis of a currently common LIN bus system with a not further defined private data bus privDB between the individual sensors (bus nodes) according to the State of the art. The standard LIN bus is only used between the control unit ECU and the first sensor S1.

As a block diagram, FIG. 1c shows such an ultrasonic system as a block diagram based on a LIN bus system that is customary today with a private data bus privDB, which is not further defined, between the individual sensors (bus nodes) in accordance with the prior art. In contrast to FIGS. 1a and 1b, the system in FIG. 1c does not have its own bus master ECU. Rather, one of the sensors, preferably the first sensor S1, takes on this role. This typically includes a small computer that takes on this role and can send a warning message to the vehicle driver via a signaling device (buzzer / loudspeaker).

The applications described above according to FIGS. la, lb and lc have different requirements for a data bus interface or the control of the signaling device (buzzer / loudspeaker), so that these different applications cannot be implemented with a structurally identical circuit.

The documents US-A2019 / 0041504, US-A-2006/0273927 and DE-A10 2017 118 565 disclose alternative solutions to a circuit for controlling one or more ultrasonic transducers and / or one or more ultrasonic transmitters and / or one or more Ultrasonic receiver and method for configuring an ultrasonic transmitter for use in a circuit known. None of these documents solves the problem of how the various applications described above can be implemented with a circuit of the same construction.

DE-A-10 2014 115 000 describes a method for the functional test of an ultrasonic transmission device of a motor vehicle. In this case, during a measuring operation, that is to say for example in production or in the workshop, a functionality of the ultrasonic sensor device is checked by means of a diagnosis device based on a transmission signal and / or the measurement signal.

In particular, ultrasonic measuring systems in the automotive sector can be implemented as low-cost solutions and high-end implementations. Sometimes it is sufficient, for example, if an acoustic signal is output as a signal that the distance between the vehicle and an obstacle is below a minimum value. In such applications, it may not be necessary to assess whether the signature must be output or not, based on an ECU or the like. to carry out comparatively on agile central evaluation and control unit. Here it would be advisable, for example, to give one of the circuits on which the individual ultrasonic sensors are arranged a certain "intelligence" in order to then control a warning display by means of this circuit.

Other systems in the high-end area also have, among other things, graphic or camera representations of the vehicle's surroundings. In any case, more elaborate evaluation electronics are required here, to which a large number of ultrasonic sensors or even several ultrasonic sensor bus systems are connected if necessary. In the latter case, however, it can make sense to relieve the central evaluation and control unit of tasks or subtasks, so that one of these sensors can be switched with additional intelligence for each connected sensor bus.

In the case of the aforementioned concepts, there is also the fact that simple addressing options for the various sensors that are connected to various bus systems may be required. So this also plays a role in terms of the complexity or the reduction in complexity of such systems. As addressing options, so-called pin or plug coding or addressing options are available here, as are known, for example, in daisy chain data bus systems for the individual bus subscribers connected in series in a chain.

One object of the invention is to create a circuit for electrically operated transducer elements, and in particular for ultrasonic transducer elements, which it allows to interconnect the transducer elements and thus the entire measuring system according to different concepts for data communication and address assignment.

To solve this problem, the invention proposes a circuit which is used to connect an ultrasonic transducer element (of an ultrasonic measuring system to a communication data bus, which can have one of several configurations) to emit ultrasonic signals and / or to receive ultrasonic signals, the circuit is provided with

at least one converter element connection WEA1, WEA2, a reference potential connection GND,

a supply potential connection VCC,

a first data bus interface IF1,

a second data bus interface IF2,

a first I / O interface GPIO1 and which can be operated by programming as (e.g. digital) input or output or programming can be operated in binary with a pin coding potential

a second I / O interface GPI02 that can be operated as a (e.g. digital) input or output through programming or binary programming with a pin coding potential,

a microcomputer for processing data and / or signals (analog and / or digital) that can be received or sent via the two data bus interfaces IF1, IF2 and the two I / O interfaces GPIOl, GPI02 and the at least one converter element connection,

the first data bus interface IF1 according to a first data bus protocol or according to a second data bus protocol different from the first data bus protocol or as (e.g. digital) input or as driver for operating an optical and / or graphic and / or acoustic (e.g. warning) display unit BUZ is operable

wherein the second data bus interface IF2 can be operated according to the first data bus protocol or according to the second data bus protocol different from the first data bus protocol or as an input or as a driver for operating an optical and / or graphic and / or acoustic (e.g. warning) display unit BUZ,

wherein the first data bus interface IF1 can be connected to a first data bus which has a bus master and to which the first data bus interfaces IF1 of further circuits can be connected (see below under Application I and in Fig. 3 and under Application II and in Fig. 4),

With the first data bus interface IF1 connected to a first data bus LIN, the second data bus interface IF2 can be connected to a different second data bus privDB which is separate from the first data bus LIN and to which the first or second data bus interface IF1, IF2 of further circuits can be connected (see below under application III and in Fig. 5, under application IV and in Fig. 6, under application V and in Fig. 7 and under application VI and in Fig. 8), wherein the second I / O interface GPI02 of a circuit with the first I / O interface GPIOl of another circuit can be connected in series and through this serial connection the one further circuit or several further circuits connected in series with one another and with one another are adres is or are (see below under application II and in FIG. 4, under application IV and in FIG. 6 and under application VI and in FIG. 8), with one of the two I / O interfaces GPIO1, GPI02 or both I / O interfaces GPIOl, GPI02 and possibly one of the two data bus interfaces IF1, IF2 in their operation as (e.g. digital) input for addressing the circuit can be or are connected to a reference potential by connection coding (see below under Application I. as well as in Fig. 3, under application III and in Fig. 5 and under application V and in Fig. 7) and

where one of the two data bus interfaces IF1, IF2, i.e. e.g. the first data bus interface IF1, for operating the (e.g. warning) display unit BUZ, can be connected to it and the other of the two data bus interfaces, i.e. e.g. the second data bus interface IF2 can be connected to a data bus privDB to which the first data bus interfaces IF1 of further circuits or the second data bus interfaces IF2 of further circuits can be connected (see below under application V as well as in FIG. 7 and under application VI and FIG. 8) .

The circuit according to the invention can be connected to the reference and supply potential of the on-board network and to various data communication concepts using a six-pin connector. The circuit according to the invention likewise has at least one connection towards the converter element.

As described above, the two data communication interfaces of the circuit and the two I / O interfaces can be configured. The individual configuration options are mentioned above and will be explained in greater detail below.

With the circuit according to the invention, a connecting link that can be configured in several respects between the sensor system (sensor hardware) and the electrical supply and data communication in the vehicle is specified. This significantly reduces the assembly effort and logistics for the vehicle supplier and also the vehicle manufacturer; because one of these two companies or both companies can now run the microcomputer by installing the appropriate software Program in such a way that the circuits ultimately installed correspond to the desired configuration.

According to a first possible application, which corresponds to the concept according to FIG. 1 a and will be described further below in connection with FIG. 3, the invention can be used to implement a data bus system which is provided with

several circuits IC according to the invention,

a bus master ECU and

a data bus line LIN to which the bus master ECU and the several IC circuits are connected,

wherein the multiple circuits IC for the purpose of data communication with the bus master and / or with each other either with their respective first data bus interfaces IF1 or their respective second data bus interfaces IF2 are connected to the data bus line LIN,

the two I / O interfaces GPIOl, GPI02 and the data bus interfaces IF1, IF2, which are not used for data communication, of a first circuit IC according to the invention are not connected to the data bus line LIN (and if necessary by means of control by the microcomputer with a representative Potential are connected) and

the two I / O interfaces GPIOl, GPI02 of all other circuits IC according to the invention or the two I / O interfaces GPIOl, GPI02 and the data bus interfaces IF1, IF2 not used for data communication of all other inventive circuits IC in each different combinations are connected to the reference potential for addressing using pin coding.

According to a second possible application, which corresponds to the concept according to FIG. 1 a and will be described further below in connection with FIG. 4, the invention can be used to implement a data bus system which is provided with

several circuits IC according to the invention,

a bus master ECU and

the data bus interfaces IF1, IF2 of all circuits IC not required for data communication are not connected (and possibly connected to a potential representing this by means of control by the microcomputer),

wherein the first I / O interface GPIOl of a first circuit IC according to the invention and the second I / O interface GPI02 of a second circuit IC according to the invention are not connected to the data bus line LIN (and if necessary by means of control by the microcomputer with a representing the Potential are connected) and

where further circuits IC according to the invention for the purpose of automatic addressing at least these further circuits IC and possibly also the second circuit IC and / or possibly also the first circuit IC are connected in series with the first circuit IC and the second circuit IC such that the second I. / O interface GPI02 of the first circuit IC and each further circuit IC is connected to the first I / O interface GPIOl of one of the further circuits IC or the next further circuit IC and the second I / O interface GPI02 of the last further circuit IC is connected to the first I / O interface GPIOl of the second circuit IC.

According to a third possible application, which corresponds to the concept according to FIG. 1b and will be described further below in connection with FIG. 5, the invention can be used to implement a data bus system which is provided with

several circuits IC according to the invention,

a bus master ECU,

a first data bus line LIN and

a second data bus line privDB,

the bus master ECU and the first data bus interface IF1 being connected to at least one first circuit IC according to the invention for the purpose of data communication on the data bus line LIN,

the second data bus interface IF2 at least one of the first circuits IC and the second data bus interfaces IF2 or the first data bus interfaces IF1 of further circuits IC according to the invention are connected to the second data bus line privDB, wherein the data bus interfaces IF1, IF2 not used for data communication of each further circuit IC are not connected to any of the data bus lines LIN, privDB (and are possibly connected to a potential representing this by means of control by the microcomputer) and

the two I / O interfaces GPIOl, GPI02 of all other circuits IC according to the invention or the two I / O interfaces GPIOl, GPI02 and the data bus interfaces IF1, IF2 not used for data communication for all other circuits IC according to the invention in different combinations Pin coding taking place addressing are connected to the reference potential.

According to a fourth possible application, which corresponds to the concept according to FIG. 1b and will be described further below in connection with FIG. 6, the invention can be used to implement a data bus system which is provided with

several circuits IC according to the invention,

a bus master ECU,

a first data bus line LIN and

a second data bus line privDB,

wherein the second data bus interface IF2 at least one of the first circuits IC and the second data bus interfaces IF2 or the first data bus interfaces IF1 of further inventive circuits IC are connected to the second data bus line privDB,

wherein the first I / O interface GPIOl of a first further circuit IC according to the invention and the second I / O interface GPI02 of a second further circuit IC according to the invention are not connected to the second data bus line privDB (and possibly by means of control by the microcomputer are connected to a potential representing this) and

wherein the other further circuits IC according to the invention for the purpose of automatic addressing at least these further circuits IC and possibly also the first further circuit IC and / or optionally also the second further circuit IC serially connected to the first further circuit IC and the second further circuit IC are that the second I / O interface GPI02 of the first further circuit IC and each further circuit device IC is connected to the first I / O interface GPIOl of one of the further circuits IC or the next further circuit IC and the second I / O interface - place GPI02 of the last further circuit IC with the first I / O interface GPIOl the second further circuit IC is connected.

According to a fifth possible application, which corresponds to the concept according to FIG. 1c and will be described further below in connection with FIG. 7, the invention can be used to implement a data bus system which is provided with

several circuits IC according to the invention,

a (e.g. warning) display unit BUZ and

a data bus line privDB,

the first data bus interface IF1 of a first circuit IC according to the invention for operating the (e.g. warning) display unit BUZ is connected to it,

the second data bus interface IF2 of the first circuit IC being connected to the data bus line privDB,

wherein the first data bus interface IF1 or the second data bus interface IF2 of further inventive circuits IC are connected to the data bus line privDB,

The two I / O interfaces GPIOl, GPI02 and the data bus interfaces IF1, IF2 of the other inventive circuits IC, which are not used for data communication, are not connected to the data bus line privDB (and possibly connected to a potential representing this by means of control by the microcomputer ) and

the two I / O interfaces GPIOl, GPI02 of all other further circuits IC according to the invention or the two I / O interfaces GPIOl, GPI02 and the data bus interfaces IF1, IF2 not used for data communication of all other further circuits IC according to the invention in different combinations each are connected to the reference potential by means of addressing carried out through pin coding.

According to a sixth possible application, which corresponds to the concept according to FIG. 1c and will be described further below in connection with FIG. 8, the invention can be used to implement a data bus system which is provided with

several circuits IC according to the invention,

a (e.g. warning) display unit BUZ and a data bus line privDB,

wherein the first I / O interface GPIOl of a first further circuit IC according to the invention and the second I / O interface GPI02 of a second further circuit IC according to the invention are not connected to the data bus line privDB (and possibly by means of control by the microcomputer with a representative Potential are connected) and

the other further circuits IC according to the invention for the purpose of automatic addressing at least these further circuits IC and optionally also the first further circuit IC and / or optionally also the second further circuit IC connected in series with the first further circuit IC and the second further circuit IC are that the second I / O interface GPI02 of the first further circuit IC and each further circuit IC is connected to the first I / O interface GPIOl of one of the further circuits IC or the next further circuit IC and the second I / O interface - GPI02 of the last further circuit IC is connected to the first I / O interface GPIOl of the second further circuit IC.

Using a second communication interface and addressing options via a freely programmable digital combined input and output connection, hereinafter referred to as GPIO or GPIO pin, in an integrated sensor circuit, hereinafter referred to as circuit, the above-mentioned applications and tasks realize with one circuit only one construction. This simplifies the logistics for the users of such a circuit and lowers the manufacturing costs through economies of scale. The individual applications are only implemented using different cable harnesses for the electrical connection of the sensors.

In the circuit itself, the various applications are controlled by software and / or logic of the microcomputer, whereby the recognition in which application fertilize and where the sensor is located in the cable harness, by querying the interfaces and the GPIOs after switching on and / or resetting and / or following a special request by a signal or a higher-level system and / or by a timer. This relates to the individual sensor and / or the system.

The query of the interfaces and GPIOs is characterized in that they can each measure the current voltage level at the respective connection of the circuit with respect to a reference potential, typically ground GND, and detect a change in the voltage value and / or recognize a transmitted protocol.

With the inventive approach of a configurable circuit, with which in particular transducer elements in different configurations can be connected with each other, an extremely efficient way is shown to solve the problem mentioned above, namely to be able to cover several concepts with one and the same circuit. In the context of the invention, it was recognized that it is sufficient to provide two data bus interfaces in the circuit according to the invention, namely to implement a division of converter elements into two groups, of which the circuits of the converter elements of one group are via a standard data bus, For example, a standard LIN bus to be connected to a bus master, while the other group of transducer elements are connected via another local data bus (also referred to as a private data bus), the circuit of one of the transducer elements of the first group coupling the two data buses realized. The circuit of said converter element then serves in a certain way as a kind of bus master for the circuits of the second group of converter elements and relieves the burden on the bus master, which is coupled to the circuits of the first group of converter elements via the standard data bus (i.e. the one circuit if the first group has only one transducer element,) is. Said circuit, to which both data buses are connected, requires two data bus interfaces, while the other circuits would in principle not need such a second data bus interface.

In addition, it has been found that it is advantageous to have two so-called General Purpose I / O interfaces that can be programmed as inputs or outputs. The two aforementioned data bus interfaces can also be operated differently, namely as data bus interfaces according to one specified protocol or as a driver or as a digital input or output. The data bus interfaces and the two other I / O interfaces are configured, for example, by means of the microcomputer.

With the aid of the two programmable I / O interfaces, addresses can be assigned by pin or connector coding, which are assigned to the circuits and thus to the converter elements connected to them. The number of circuits that can be pin-coded in this way is limited and can advantageously be expanded according to the invention in that one of the two data bus interfaces is also used for pin coding. If a greater number of circuits are to be connected to a data bus than can be addressed by the three interfaces in a pin-coded manner, the two I / O interfaces can be used for the chained coupling of a large number of circuits according to the invention by creating a daisy chain -Connection to be interconnected. This additional connection of neighboring circuits, which exists in addition to the communication data bus, enables convenient addressing of the individual circuits, which can run automatically.

Finally, with the circuit according to the invention, it is also possible to connect several converter elements to one another via one or more communication buses (without a bus master in the actual sense), one of the circuits being used to drive a particular (warning) display unit. For this purpose, one of the two data bus interfaces is used as a driver, while the other data bus interface of this circuit is used for data communication with the other circuits. These additional circuits can either be addressed in a pin-coded manner or can be automatically addressed via the daisy chain-like connection already described above.

The multifunctionality of the circuit according to the invention is the real advantage of the invention.

The invention is explained in more detail below with reference to an exemplary embodiment using the drawing. In detail, show:

Figs. la, lb and lc

State-of-the-art data bus systems, Fig. 2 shows a sensor according to the invention with circuit IC, which is shown in simplified form as a block diagram.

3 shows a data bus system as a block diagram according to application I with sensors according to FIG. 2,

4 shows a data bus system as a block diagram according to application II with sensors according to FIG. 2,

FIG. 5 shows a data bus system as a block diagram according to application III with sensors according to FIG. 2,

6 shows a data bus system as a block diagram according to application IV with sensors according to FIG. 2,

7 shows a data bus system as a block diagram according to application V with sensors according to FIG. 2,

8 shows a data bus system as a block diagram according to application VI with sensors according to FIG. 2,

9 shows an exemplary process flow for a data bus system and

10 shows an exemplary embodiment for method steps which take place within a circuit.

A device according to the invention is shown in FIG. When a sensor is mentioned in the following, this basically means the circuit via which the sensor is connected to the bus of the respective data bus system.

A suitable ultrasonic circuit IC is provided with two standard-compliant interfaces IF1, IF2 and one or more GPIOs. For example, one of the interfaces can be a LIN bus interface. Fig. 2 shows a corresponding sensor schematically in the form of function blocks. Such a sensor can comprise further blocks which are of subordinate importance to the invention and which are not shown for the sake of simplicity. The circuit IC preferably contains the following blocks:

Supply Su

This is a function block that typically has a voltage regulator or the like. comprises the energy supply providing electrical energy.

Logic

This is preferably a digital circuit block for the function of the IC, the processing of the protocols, the signal processing, the evaluation of the ultrasonic measurements etc.

Transmitter Tx

This is a transmitter for controlling an exemplary ultrasonic transducer TR or ultrasonic transmitter TR.

Receiver Rx

This is a receiver for receiving the signals from the exemplary ultrasonic transducer TR or an ultrasonic receiver TR.

Interface 1 IF1

This is preferably a data interface that is preferably used primarily for communication with a higher-level control device.

Interface 2 IF2

This is preferably a data interface that is preferably used primarily for communication with the other sensors.

General Purpose I / O GPIOl, GPI02

These are connections that can be freely programmed as input and output connections and that are preferably used primarily to address the sensors.

Transducer element TR It is a transducer element, for example, electro-acoustic, electro-optical, electro-mechanical, electro-magnetic or other type. The invention is described for example for ultrasonic transducer elements in particular in the form of transducers.

Measuring transducer element connections WEA1, WEA2

These are connections to which the respective transducer element is connected. Microcomputer pC

The microcomputer determines the function of the circuit within the various circuit concepts through its programming.

The circuit IC exchanges signals with the one or more ultrasonic transducers TR, TRI, TR2... TR8 and / or with the one or more ultrasonic transmitters and / or with the one or more ultrasonic receivers directly or indirectly. "Directly" means that the circuit IC_ is directly electrically connected to one or more ultrasonic transducers TR, TRI, TR2 ... TR8 and / or to one or more ultrasonic transmitters and / or to one or more ultrasonic receivers. "Indirectly" means that the circuit IC only indirectly via other electrical and / or electronic components electrically with one or more ultrasonic transducers TR, TRI, TR2 ... TR8 and / or with one or more ultrasonic transmitters and / or with one or multiple ultrasonic receivers is connected.

The first interface IF1 is the primary data interface to the standard communication data bus of the vehicle. A standard automotive-qualified data interface type is typically used here. For example, it is particularly preferred to use a LIN interface here. Furthermore, in the case of a LIN interface, this first interface IF1 can be used as a low-side driver in order to control a loudspeaker / buzzer or generally a (warning) display unit BUZ that may operate optically or graphically.

The second interface IF2 connects the other sensors with one another when a selected sensor is already communicating with the vehicle's standard communication data bus via its first interface IF1. Compared to the first interface IF1, the second interface IF2 is a "private", local interface so that a standard interface (eg a LIN interface) or an interface type with reduced requirements can be used here.

If the second interface IF2 is not used for communication, it can also be used as an additional GPIO pin and / or for address assignment.

In this arrangement, the GPIO pins are primarily used to address the sensors, regardless of whether only the first interface IF1 or both interfaces IF1, IF2 are used. Addressing is preferably done either by connecting the individual GPIOs to GND in the connector (if necessary using a pull-up resistor and / or a power source in the sensor) or by e.g. a daisy chain-like connection from the GPIO-out of the current sensor to the GPIO-in of the next sensor.

According to the invention, it was recognized that with these sensors according to FIG. 2 (IC, PCB and a 6-pin connector for VCC, GND, IF1, IF2, GPIO1, GPI02) the following applications, among others, can be implemented:

1) Application with ECU as control unit or higher-level computer system:

a) Application I (see Fig. 3, corresponds to the concept of Fig. la)

Standard LIN data bus with pin coding of the bus node address of the sensor via connection pattern from three pins to the reference potential GND b) Application II (see Fig. 4, corresponds to the concept according to Fig. La)

Standard LIN data bus with a determination of the bus node address of the sensor as in a daisy chain process

2) Application with a sensor that uses the ECU as a control unit or as a higher-level

Computer system partially replaced:

c) Application III (see Fig. 5, corresponds to the concept of Fig. lb)

In order to relieve the ECU, one of the sensors (e.g. Sl) coupled to the ECU via the standard communication data bus transfers already processed data to the ECU and replaces the ECU with the following sensors, with a pin coding of the bus node address of the sensor via connection patterns from three pins to the reference potential GND.

d) Application IV (see Fig. 6, corresponds to the concept of Fig. lb) In order to relieve the ECU, one of the sensors coupled to the ECU via the standard communication data bus (e.g. S1) transmits already processed data to the ECU and "replaces" the ECU with respect to the following sensors, with the determination of the bus node address of the sensors as with one Daisy-chain procedure takes place.

3) Application without ECU as control unit or higher-level computer system, but with a display unit that can be operated by one of the sensors

e) Application V (see Fig. 7, corresponds to the concept of Fig. lc)

The first sensor controls a loudspeaker / buzzer or generally an optical and / or graphical and / or acoustic display unit and replaces the ECU with respect to the following sensors, whereby the bus node address of the sensor is pin-coded via connection patterns from three pins to the reference potential GND.

f) Application VI (see Fig. 8, corresponds to the concept of Fig. lc)

The first sensor controls a loudspeaker / buzzer or generally an optical and / or graphic and / or acoustic display unit and replaces the ECU with respect to the following sensors, the bus node address of the sensors being determined as in a daisy chain process.

However, the invention is not restricted to this. Instead of auto-addressing via daisy-chain similar methods, other auto-addressing methods can also be used. The invention is therefore not limited to the auto-addressing manner.

Application I: Standard LIN data bus, addressing via pin coding (Fig. 3)

In the example of FIG. 3, the sensors are supplied with electrical energy via the VCC line VCC and the GND line GND. The electrical energy of the VCC line and the GND line is provided by the bus master, the ECU, for example. The ECU represents the bus master of the communication bus, which can be a LIN data bus LIN, for example. A BCM (Body Control Module) can also be used instead of the ECU. These three lines VCC, GND, LIN are connected to each sensor in the application example of FIG. 3. The structure of each sensor corresponds to that of FIG. 2. The circuits of the circuits IC of FIG. 3 for the pin coding are shown again in the following table.

As can be easily seen, the address in the example of FIG. 3 is coded by means of the cable harness and the second interface IF2 of the sensors, the first GPIO pin GPIO1 and the second GPIO pin GPI02 of the respective circuits IC.

For the address assignment on the LIN bus, 3 input pins of the circuits IC are required. In this application, the second interface IF2 and two additional GPIOs of the respective circuit IC are used for this address assignment. All 3 pins IF2, GPIO1, GPI02 use an internal pull-up resistor and are therefore at a high level when they are not connected. The coding is carried out by wiring with a low level by means of a connection to the reference potential GND. The input circuits of these three connection pins IF2, GPIOl, GPI02 determine a respective voltage measurement after switching on and / or resetting and / or on request, e.g. by software command or by wired signaling and / or cyclically e.g. controlled by a timer and / or causes the voltage value of the respective connection by a watchdog timer. Depending on the external wiring, different bus node addresses are assigned for the sensors. Application II: Standard LIN, addressing as in a daisy chain process (Fig. 4)

As an alternative to assigning addresses via the connector coding (GPIOs with or without IF2), the GPIOs can also be connected in a daisy chain-like configuration according to FIG. 4.

The supply voltage VCC, the data bus (e.g. LIN) and the reference potential line GND are provided by the bus master ECU or BCMs and are connected to each sensor (see Fig. 4).

For the bus node address assignment on the data bus (e.g. LIN), the GPIOs of the sensors of the network are connected in series in a daisy chain-like configuration. With regard to processes for assigning addresses that can be used by way of example, reference is made to DE-U-20 2018 006 079 and US-A-2017/0083468. Orientation on the data bus is important for the discussion of address assignment. Sensors that are located closer to the bus master ECU in the data bus are "in front of" those sensors that are placed further from the bus master ECU in the data bus than the aforementioned sensors. The latter, second-mentioned sensors are in this sense placed "after" or "following" the first-mentioned sensors in the data bus. In this sense, the first-mentioned sensors are placed “before” or “preceding” the second-mentioned sensors in the data bus. The fully automatic assignment of the bus node addresses then follows e.g. as follows:

1. All GPIO inputs use an internal pull-up resistor. If no other level is impressed, all GPIO connections GPIOl, GPI02 of all sensors are on a logical 1.

2. The first GPIO connection GPIO1 of a subsequent sensor is always connected to the second GPIO connection GPI02 of a preceding sensor.

3. The first sensor S1 has no preceding sensor. Its first GPIO connection is therefore not connected and is therefore always on a logical 1.

4. Each sensor without a valid bus node address drives its second GPIO connection GPI02 to a logical 0. 5. The first GPIO connections GPIOl of all subsequent sensors then detect this logical 0.

6. Only the first sensor S1 detects a logical 1 at its first GPIO connection, since it is not preceded by a sensor that forces its first GPIO connection GPIO1 to the logical value 0.

7. This first sensor S1 recognizes that it is the sensor furthest forward in the chain of sensors without a valid bus node address. If the bus master ECU now offers a bus node address for assignment by means of a special bus command, the first sensor S1 accepts this offered bus node address as a valid bus node address and sets its second GPIO connection GPI02 to a logical 1.

8. Of the sensors without a valid bus node address, only the second sensor S2 detects a logical 1 at its first GPIO connection, since it is not preceded by a sensor without an invalid bus node address that forces its first GPIO connection GPIOl to logical 0.

9. This second sensor S2 thereby recognizes that it is the sensor furthest forward in the chain of sensors without a valid bus node address. If the bus master ECU now offers a bus node address for assignment by means of a special bus command, the second sensor S2 accepts this offered bus node address as a valid bus node address and sets its second GPIO connection GPI02 to a logical 1.

10. This and the following sensors repeat steps 8 and 9 in an analogous manner until all sensors have been addressed.

As a person skilled in the art will surely recognize, the addressing sequence can also be reversed from the last sensor (S8 in FIG. 4) to the first sensor S1. In this case, the bus master ECU can receive a signal via the first GPIO connection GPIO1 of the first sensor that the first sensor S1 has received a valid bus node address and thus the chain of sensors is fully addressed. This configuration of FIG. 4 or the reverse configuration described made light, in contrast to the application described above, the assignment of any number of sensors. The number of these can well exceed the number described under Application I.

Application III: The first sensor (or one of the first sensors) is the bus master of a private data bus and is connected to the ECU via a standard interface, addressing via GPIO (pin) address coding (Fig. 5)

In this application outlined in FIG. 5, the "intelligence" of the ultrasonic sensor system lies in the first sensor S1 (illustrated by hatching in the block pC) or generally in one of those sensors that communicates with the bus master via the standard bus. This means that the sensor in question takes on the role of bus master for the following sensors in the private data bus privDB.

In the example of FIG. 5, the positions and thus the respective bus node address to be used by the respective sensor of the second sensor S2, the third sensor S3, and the fourth sensor S4 are again about the presence or absence of a connection between the first GPIO Connection GPIOl and the reference potential line GND and the presence or absence of a connection between the second GPIO connection GPI02 and the reference potential line GND. In the example in FIG. 5, the GPIO connections of the first sensor S1 are not wired, as a result of which it can recognize its role as bus master of the private data bus privDB. This sensor can, however, also receive its task as bus master of the private data bus privDB via a data word via its first data bus interface IF1 of the first sensor S1.

The first sensor S1 uses its first data bus interface IF1 as a data bus interface for a standard data interface in order to communicate with a higher-level control unit ECU. The standard data interface is preferably a LIN bus interface for a LIN data bus LIN.

The first sensor S1 uses its second data bus interface IF2 as a bus master interface for the subsequent private data bus privDB. The private data bus privDB can correspond to a different data bus standard if the second data bus interface of the first sensor S1 is configured according to this standard.

The sensors following the first sensor S1 are connected with their first data bus interface IF1 to the private data bus privDB. The private data bus privDB can correspond to a different data bus standard if the first data bus interface IF1 of the sensor following the first sensor S1 is also configured in accordance with this standard.

The first interface of the first sensor S1 acts as e.g. LIN interface to the BCM or the ECU.

The second interface of the first sensor S1 serves as a local bus interface to the fol lowing sensors and acts as a bus master for the following sensors.

The identification of the bus node addresses of the sensors of the private data bus privDB following the first sensor S1 takes place again with the aid of the pin coding as described above for application I via the GPIO connections GPIO1, GPI02 of the sensors. In the example of FIG. 5, the second data interface IF2 of the sensors following the first sensor S1 is not used. In principle, however, as in the example of application I, it can also be used for the address assignment of the bus addresses for the sensors of the private data bus privDB following the first sensor S1. In addition to the GPIO connections GPIO1, GPI02, the second data bus interfaces IF2 of the sensors connected to the private data bus privDB with their first data bus interfaces IF1 can also be used for pin coding.

Application IV: The first sensor (or one of the first sensors) is the bus master of a private data bus and is connected to the ECU via a standard interface, addressing via daisy-chain-like address coding (Fig. 6)

In this application outlined in FIG. 6, the "intelligence" of the ultrasonic sensor system is again in the first sensor S1 (illustrated by hatching the block pC) or generally in one of those sensors which communicates with the bus master via the standard bus. This means that the first sensor takes on the role of bus master for the subsequent sensors in the data bus. In the example of FIG. 6, the positions and thus the bus node address to be used in each case of the second sensor S2, the third sensor S3, and the fourth sensor S4 are determined again via the daisy chain-like connection chain of the sensors following the first sensor S1 . The daisy-chain-like chain between the sensors following the first sensor S1 is again established, as in application II, by respective connections between the first GPIO connection GPIOl of a subsequent sensor and the second GPIO connection GPI02 of the preceding sensor. In the example of FIG. 6, the second GPIO connection GPI02 of the first sensor S1 is connected to the first GPIO connection GPIO1 of the second sensor S2. The addressing of the private data bus privDB takes place here, as already mentioned in the description of application II, preferably from the last sensor in the chain of sensors placed farthest "back" and thus behind all other sensors, to the first sensor S1. This enables the first sensor in its role as bus master of the private data bus privDB to recognize that all sensors on the private data bus privDB have successfully received a valid bus node address. What is described above in connection with application II for the address assignment process applies here in an analogous manner and is therefore not repeated here. In the example in FIG. 6, the first GPIO connection GPIO1 of the first sensor S1 is not wired, so that it can recognize its role as bus master of the private data bus privDB.

The sensors following the first sensor S1 are connected to the private data bus privDB with their first data bus interface IF1. The private data bus privDB can correspond to another data bus standard if the first data bus interface IF1 of the sensor following the first sensor S1 can also be configured accordingly to this standard. The second data bus interface IF2 of the sensors following the first sensor S1 are IF2 not connected.

Application V: The first sensor is the bus master of a private data bus and controls a loudspeaker / buzzer, addressing via GPIO address coding (Fig. 7)

This application V is outlined in FIG. 7 and is very similar to the previous application IV.

In this application, the "intelligence" of the ultrasonic sensor system lies in the first sensor S1 or, in other words, in one of the sensors which is connected to a display unit and controls it. This means that the first sensor takes on the role of the bus master for the subsequent sensors of the private data bus privDB.

However, the first sensor S1 does not report the system result to a higher-level control unit ECU, but uses its first data interface IF1 as a low-side driver to control a loudspeaker / buzzer or generally a visual, graphic or acoustic warning display unit.

The sensors of the private data bus privDB following the first sensor S1 are again provided with a bus node address for the private data bus privDB analogous to the applications I and III using the pin coding method and a suitable cable harness by using their first GPIO connection GPIOl and yours evaluate second GPIO connection GPI02.

The identification of the bus node addresses of the sensors of the private data bus privDB following the first sensor S1 takes place again with the help of the coding as described under application I and under application III via the GPIO connections GPIO1, GPI02 of the sensors. In the example in FIG. 7, the second data interface IF2 of the sensors following the first sensor S1 is not used, but in principle, as in the example of application I and in the example of application III, it can also be used to assign the bus addresses for the first sensor S1 subsequent sensors of the private data bus privDB are used. But it can also be used for other applications. Application VI: The first sensor is the bus master of a private data bus and controls a loudspeaker / buzzer, addressing via daisy-chain-like address coding (Fig. 8)

This application is shown in FIG. 8 and is very similar to the previous application V.

In this application, the "intelligence" of the ultrasonic sensor system lies in the first sensor S1 or, in other words, in one of the sensors which is connected to a display unit and controls it. This means that the first sensor takes on the role of bus master for the subsequent sensors in the data bus.

The first sensor S1, however, does not report the system result to a higher-level control unit ECU, but uses its first data interface IF1 as a low-side driver for controlling a loudspeaker / buzzer.

The bus node addresses of the sensors of the private data bus privDB following the first sensor S1 are again determined by means of the daisy chain-like connection chain, analogously to applications II and IV.

In the example of FIG. 8, the second data interface IF2 of the sensors following the first sensor S1 is not used, but it can of course be used for other applications.

Method for recognizing the present application according to which the sensors are connected

A method with which it can be determined according to which of the applications I to VI the circuit IC of a sensor is configured or wired runs e.g. as follows (Fig. 9):

Step 1

In a first step (1), the circuit IC is reset to an initial state. This can, for example, after switching on and / or after receiving a reset command via an additional, shown in FIGS. 1 to 8 not shown reverse set line or as a data bus command. Resetting by a safety logic, for example a watchdog timer, is also conceivable.

After resetting (1), the first data interface IF1 of the circuit IC does not drive its first connection, but can examine this first connection of the circuit IC for logic levels in its function as a data input.

After resetting (1), the second data interface IF2 of the circuit IC does not drive its second connection, but can examine this second connection of the circuit IC preferably for logic levels in its function as a data input.

After resetting (1), the first GPIO connection GPIO1 of the circuit IC does not drive its third connection, but can examine this third connection of the circuit IC for logic levels in the function as a data input.

After the reset (1), the second GPIO connection GPI02 of the circuit IC does not drive its fourth connection, but can examine this fourth connection of the circuit IC preferably for logic levels in its function as a data input.

The first connection of the circuit IC, if it is not overwritten from the outside by a low, raw logic 0, is pulled to a high resistance to a logic 1 by an internal first pull-up circuit.

The second connection of the circuit IC, if it is not overwritten from the outside by a never-ohmic logical 0, is pulled to a high-impedance logic 1 by an internal second pull-up circuit.

The third connection of the circuit IC, if it is not overwritten from the outside by a never-ohmic logic 0, is pulled to a logic 1 by an internal third pull-up circuit.

The fourth connection of the circuit IC, if it is not overwritten from the outside by a never-ohmic logical 0, is pulled high-impedance to a logical 1 by an internal fourth pull-up circuit. step 2

The circuit IC drives a logic 0 with its second interface IF2 and waits for a predetermined time At after resetting. During this time, the circuit IC configures its first data interface IF1 as a data interface of a first data bus standard, for example as a LIN interface.

Case 2a): If the circuit IC observes the transmission of a first predetermined data word or a first predetermined sequence of predetermined data words at its first data interface IF1 during this time At, the circuit IC recognizes that it is in a configuration of the application I or is located as a circuit IC of the first sensor S1 in application III or IV. The circuit IC can recognize from this that it is connected by its first data interface IF1 to a superordinate computer system ECU, BCM. In this case, the circuit IC waits for a command from the computer system ECU by means of a second predetermined data word and / or a second predetermined sequence of predetermined data words which inform the circuit IC which of the applications I to IV is present.

Case 2b): If the circuit IC observes no transmission of the first given data word or the first given sequence of given data at its first data interface IF1 and a permanent logic 0 in the time At, then it knows the circuit IC that it is subsequent circuit IC located in a private data bus privDB following the first sensor S1 in application V or VI.

Case 2c): If the circuit IC observes no transmission of the first given data word or the first given sequence of given data at its first data interface IF1 and a permanent logical 1 in the time At, then it knows the circuit IC that it is Circuit IC of the first sensor S1 is in the application V or VI.

Step 3 (only for applications I to IV)

In case 2a, the computer system ECU uses a second predetermined data word and / or a second predetermined sequence of predetermined data words, preferably as a third step, to indicate which of the applications I to IV is present. In cases 2b and 2c, the circuit IC of the first sensor S1 informs the circuits IC of the subsequent sensors that they are in application V or VI.

Step 4 (only for application I)

In the case of application I, the circuits IC of all sensors have the information that application I is present. Each circuit IC of the overall system then checks the logic level at its second data interface IF2 and at its first GPIO connection GPIO1 and at its second GPIO connection GPI02. On the basis of the three data bit values determined, each circuit IC then calculates its individual bus node address on the basis of a predetermined algorithm. An exemplary algorithm can be: 4 * bit value on the second data interface IF2 + 2 * bit value on the first GPIO connection GPIO1 + bit value on the second GPIO connection GPI02.

Step 5 (only for application II)

In the case of application II, the circuits IC of all sensors have the information that application II is present. Addressing can take place from the last sensor to the first sensor or vice versa. The method described above in connection with application II for assigning the bus node addresses is carried out in this step 5 so that at the end of this step 5 all the circuits IC of the sensors have a valid bus node address.

Step 6 (only for application III)

In the case of application III, only the first sensor S1 has the information that application III is present. Step 6 therefore serves to send a message to the other sensors that their first data interface should be reconfigured from a configuration corresponding to the first data bus standard to a new configuration corresponding to the protocol of the private data bus privDB.

For this purpose, the circuit IC of the first sensor S1 sends a predetermined data message in the protocol of the first data bus standard, that is, for example, in accordance with the LIN protocol. This data message preferably includes information about which of the applications III to IV is present and that the circuits IC receiving this data message are those that belong to sensors following the first sensor S1.

After receiving this predetermined data message, the circuits IC of the sensors following the first sensor S1 configure their first data interface IF1 in accordance with the protocol of the private data bus privDB and determine their bus node address within the private data bus privDB using the GPIO method, as described above in connection with the Application III described.

In the case of application IV, only the first sensor S1 has the information that application IV is present. Step 7 therefore serves to send a message to the other sensors that their first data interface should be reconfigured from a configuration corresponding to the first data bus standard to a new configuration corresponding to the protocol of the private data bus privDB.

For this purpose, the circuit IC of the first sensor S1 sends a predetermined data message in the protocol of the first data bus standard, that is, for example, in accordance with the LIN protocol. This data message preferably includes information about which of the applications III to IV is present and that the circuits IC receiving this data message are those belonging to sensors following the first sensor S1.

After receiving this predetermined data message, the circuits IC of the sensors following the first sensor S1 configure their first data interface IF1 according to the protocol of the private data bus privDB and determine their bus node address within the private data bus privDB using a daisy chain-like method, such as described above in connection with Application IV.

In case 2c of step 2, only the first sensor S1 has the information that the application V or the application VI is present. The step 8 is therefore used to to send a message to other sensors that their first data interface should be reconfigured from a configuration according to the first data bus standard to a new configuration according to the protocol of the private data bus privDB.

Step 9

For this purpose, in a step 9, the circuit IC of the first sensor S1 sends a predetermined fourth data message in the protocol of the first data bus standard, so for example in accordance with the LIN protocol. This fourth data message includes information that one of the applications V or VI is present and that the circuits IC receiving this data message are those belonging to the sensors following the first sensor S1.

Step 10

A first possibility in the form of a step 10 is for the circuits IC of the sensors following the first sensor S1 to configure their first data interface IF1 according to the protocol of the private data bus privDB as soon as this predetermined fourth data message has been received.

After receiving this predetermined fourth data message, the circuits IC of the sensors following the first sensor S1 in any case initiate an address determination in accordance with a daisy chain-like method.

Step 11

If, in a step 11, the circuit IC of the first sensor S1 does not detect a change from a logical 0 to a logical 1 at its second GPIO connection GPI02 after a second period At ₂ , then there is no daisy chain connection.

Step 12

In a step 12, the circuit IC of the first sensor S1 then uses a predetermined fifth data message to signal the circuits IC of the sensors following the first sensor S1 that an application V is involved. Then it will The method described above in connection with the application V for assigning the bus node addresses is carried out.

Step 13

However, if in a step 13 the circuit IC of the first sensor S1 detects a change from a logical 0 to a logical 1 at its second GPIO connection GPI02 after a second period At ₂ , a daisy chain-like connection is present.

By means of a predetermined sixth data message, the circuit IC of the first sensor S1 then signals in this step 13 to the circuits IC of the sensors following the first sensor S1 that it is an application VI. The method for assigning the bus node addresses described above in connection with application VI is then carried out.

Emergency signaling

If the first sensor S1 still has a signaling option not detailed here, it can send an error message if, for example, the initialization of the bus system fails. For example, in the event of such an error, it can transmit a predefined pattern of ultrasonic signals.

The circuit IC can also be used to control one or more ultrasonic transducers TRI, TR2,... TR8 and / or one or more ultrasonic transmitters and / or one or more ultrasonic receivers, the circuit then typically being provided with the one or more ultrasonic transducers TRI, TR2, ... TR8 and / or the one or more ultrasonic transmitters and / or the one or more ultrasonic receivers to form a sensor within the meaning of this disclosure. The reference symbol TR and its numbered variants TRI, TR2, ... TR8 stand in accordance with the terminology used here for one or more ultrasonic transducers TR, TRI, TR2 .... TR8 and / or for one or more ultrasonic transmitters and / or for one or more ultrasound receivers. The sensor and / or the circuit IC can have several, but at least two, states. The circuit IC typically has means to, as a function of the at least two states, signals and / or error signals via the one or more Ultrasonic transducers TRI, TR2, ... TR8 and / or to emit via the one or more ultrasonic transmitters and / or to receive commands via the one or more ultrasonic receivers. Such a circuit IC preferably has means, for example the first data interface IF1, for data transmission of measurement results to a higher-level device ECU, BCM by means of a data connection, for example a LIN bus. The circuit IC then preferably sends an error message as a signal and / or error signal via the one ultrasonic transducer or several ultrasonic transducers TRI, TR2, ... TR8 and / or via the one ultrasonic transmitter or several ultrasonic transmitters if the data connection is faulty and / or is interrupted.

The invention thus relates to a circuit IC for controlling an ultrasonic transducer TRI, TR2, ... TR8 and / or an ultrasonic transmitter and / or an ultrasonic receiver. It is typically i.a. provided with a first connection and with a second connection and with a third connection and with a fourth connection and with a first interface IF1 and with a second interface IF2 and with a first GPIO interface GPIO1 and with a second GPIO interface GPI02. According to the invention, the circuit is intended to be used in a first application I and a second application II and a third application III and a fourth application IV and a fifth application V and a sixth application VI in order to be able to represent the necessary production flexibility. The first interface IF1 is connected to the first connection of the circuit IC. The first interface IF1 can be operated according to a first data bus protocol and / or as a digi tal input and / or as a low-side driver. The first interface IF1 is e.g. operated as a digital input after resetting the circuit IC. The reset can be done, for example, after switching on, by a signal or by software command or by a circuit part. Circuit IC is set up and provided to carry out a method that includes at least the following steps, possibly also in a different order, a preferred order being described here. It should also be pointed out that here, if necessary, for a better overview, several steps are combined in FIG. 10 to form an overall step with the same reference number. The same reference symbols are used for the different designations of the sub-steps.

A first step (20) is to reset the circuit IC and the resulting high-resistance pulling of the input potential of the first interface IF1 to a logical 1. This first step (20) also includes the configuration of the first interface IF1 according to the first data bus protocol and the configuration of the second interface IF2 according to the first data bus protocol.

As a second step (21), the circuit IC waits for a first time At for it to receive a first predetermined data message via the first interface IF1 by overwriting the high-resistance 1 at the input of its first interface IF1.

If the circuit IC receives the first predetermined data message in this first time At via its first interface IF1 in a step (22), it carries out the following steps:

In the event (23) that the circuit IC has received a first predetermined data message via its first interface IF1, which a first application (application

I), the following step (23) is the implementation of an auto addressing method by means of a GPIO method by the circuit IC to determine a valid bus node address for the circuit IC.

In the event (24) that the circuit IC has received a first predetermined data message via its first interface IF1, which a second application (application

II) signals, the implementation of an Autoadressierungsverfah rens by means of a daisy-chain-like method by the circuit IC in cooperation with the other circuits IC of the data bus system follows as step (24) to determine a valid bus node address for the circuit.

In the event (25) that the circuit IC has received a first predetermined data message via its first interface IF1, which a third application (application

III) signaled by signaling a positioning as the first sensor S1, step (25) is followed by the further signaling of an application III to the subsequent circuits IC of the sensors following in the data bus chain by means of the second interface IF2 and the signaling (25) to the subsequent circuits IC of the sensors following in the data bus chain by means of the second interface IF2 that they are positioned as the following sensor S1. In addition, in this case the configuration (25) of the second interface IF2 takes place in accordance with a second data bus protocol, if this is not the same as the first data bus protocol. In the event (26) that the circuit IC has received a first predetermined data message via its first interface IF1, which a fourth application (application

IV) is signaled with signaling (26) of a positioning as a subsequent sensor, the implementation of an auto-addressing method by means of a GPIO method by the circuit IC follows as step (26) to determine a valid bus node address for the circuit IC. In addition, in this case (26) the first interface IF1 is preferably configured according to a second data bus protocol if this is not the same as the first data bus protocol.

In the event (27) that the circuit IC has received a first predetermined data message via its first interface IF1, which is a fifth application (application

V) is signaled with signaling (27) of a positioning as the first sensor S1, followed by step (27) is the signaling of an application IV to the subsequent circuits IC of the sensors following in the data bus chain by means of the second interface IF2 and the signaling (27) to the subsequent circuits IC of the sensors following in the data bus chain by means of the second interface IF2 that they have a positioning as the following sensor S1. In this case (27, the second interface IF2 is preferably also configured according to a second data bus protocol, if this is not the same as the first data bus protocol.

In the event (28) that the circuit IC has received a first predetermined data message via its first interface IF1, which a sixth application (application

VI) is signaled with signaling (28) of a positioning as a subsequent sensor, the implementation of an auto-addressing method by means of a daisy-chain-like method follows as step (28) to determine a valid bus node address for the subsequent circuits IC of the subsequent sensors and, if necessary, the configuration ( 28) of the first interface IF1 according to a second data bus protocol, if this is not the same as the first data bus protocol.

If (29) no first predetermined data message is received via the first interface IF1 of the circuit IC in this first period At and the logic level at the input of the first interface IF1 in this first time At was a logic 1, which is a step (8) of the 9, but instead the implementation of a signaling (29) of a message "Application V or VI" in a step (29) to the subsequent circuits IC of the sensors following in the data bus chain with means of the second interface IF2 and signaling (29) to the following Circuits IC of the sensors following in the data bus chain by means of the second interface IF2 that they have a positioning as the following sensor S1. As a result, the circuits IC of the subsequent sensors start an attempt to carry out auto-addressing via an existing or non-existing daisy-chain-like chain (30). If the daisy-chain-like chain does not exist, this procedure must naturally fail (31), which can be used to differentiate between application V and application VI.

If (31) after a second period At ₂ within the scope of an auto addressing process by means of a daisy chain-like process there is no signaling to the circuit IC that this auto-addressing process has been successfully carried out using a daisy chain-like process, it must be an application V act. Therefore, the signaling (31) of an application V is then carried out to the circuits IC of the sensors following this circuit IC. In addition, the configuration (31) of the second interface IF2 takes place according to a second data bus protocol, if this is not the same as the first data bus protocol.

If (31) within the second time period At ₂ in the context of this auto-addressing process by means of a daisy-chain-like process, a signaling to the circuit IC about the successful implementation of this auto-addressing process by means of a daisy-chain-like process has taken place, it must be a Application VI act. Therefore, the signaling (31) of an application VI to the circuits IC of the sensors following this circuit IC is then preferably carried out. In addition, the configuration (31) of the second interface IF2 takes place in accordance with a second data bus protocol if this is not the same as the first data bus protocol.

If (32) no first predetermined data message is received via the first interface IF1 of the circuit IC in that first time At and the logic level at the input of the first interface IF1 was a logic 0 in the first time At, the data bus system does not have a bus master ECU . In that case it must be an application V or VI and the circuit IC is not at the bus position of the first sensor S1. Preferably, but not necessarily, the first sensor waits for the signaling “Application V or VI”. It follows at the latest after the signaling "Application V or VI" by the first sensor S1, the step of attempting the through Execution (33) of an auto-addressing method by means of a daisy chain-like method for determining a valid bus node address. If (34) then after a second period At ₂ the signaling of an application V is received via the first interface IF1 from the first sensor S1, an auto-addressing process is carried out (34) using a GPIO process to determine a valid bus node address. In addition, the first interface IF1 is configured (34) in accordance with a second data bus protocol if this is not the same as the first data bus protocol.

In general, the invention thus relates to a circuit IC for controlling one or more ultrasonic transducers TRI, TR2, ... TR8 and / or one or more ultrasonic transmitters and / or one or more ultrasonic receivers, the circuit IC having means, e.g. a small computer system with a memory and an internal data bus, to which, for example, the first data interface IF1 and the second data interface IF2 and the first GPIO connection GPIOl and the second GPIO connection GPI02 are connected in order to be able to carry out a method to recognize whether it is either in one of the applications from a first set of applications. The first set of applications comprises at least two applications and / or three applications and / or four applications of application I and application II and application III and application IV. By means of said method, the circuit IC can then also recognize whether it is instead located in one of the applications from a second set of applications, the second set of applications comprising at least one application and / or two applications of application V and application VI.

The corresponding method for execution in this circuit IC is characterized in that the method has steps to identify whether the circuit IC is either in one of the applications from a first set of applications, the first set of applications at least two applications and / or three applications and / or four applications of application I and application II and application III and application IV, or whether it is instead in one of the applications from a second set of applications, the second set the application comprises at least one application and / or two applications of application V and application VI. Such a circuit and the associated method make it possible, at least in some implementations, to use the circuit IC with the same sensor PCB flexibly in different applications where it configures itself independently. This enables the number of different structures and the associated production logistics to be reduced, which leads to cost savings.

The advantages are not limited to this.

The invention has been described above using the example of circuits for transducer elements operating on the basis of ultrasound. However, the invention can also be applied to circuits to which other types of measuring converter elements, in particular, can be connected.

Individual features and groups of features that characterize various exemplary embodiments of the invention are listed below. It applies here that these individual exemplary embodiments can include individual features of the respective feature groups, individual features from several of the feature groups and several feature groups.

1. Circuit IC for controlling one or more ultrasonic transducers and / or one or more ultrasonic transmitters and / or one or more ultrasonic receivers

with a first connection and

with a second connector and

with a third connector and

with a fourth port and

with a first interface IF1 and

with a second interface IF2 and

with a first GPIO interface GPIOl and

with a second GPIO interface GPI02,

wherein the circuit is intended to be used in a first application I and a second application II and a third application III and a fourth application IV and a fifth application V and a sixth application VI and

wherein the first interface IF1 is connected to the first connection and wherein the first interface IF1 can be operated according to a first data bus protocol and wherein the first interface IF1 can be operated as a digital input and

wherein the first interface IF1 can be operated as a low-side driver and

wherein the first interface IF1 is operated as a digital input after a reset and

the circuit IC being set up and provided to carry out a method comprising the following steps:

Reset (20) the circuit IC and

High-resistance pulling (20) of the input of the first interface IF1 to a logical 1 and

Low-resistance driving (20) of the output of the second interface IF2 to a logical 0 and

Configuring (20) the first interface IF1 according to the first data bus protocol;

Configuring (20) the second interface IF2 in accordance with the first data bus protocol;

Waiting (21) for a first time At for a first predetermined data message to be received via the first interface IF1 by overwriting the high-resistance 0 at the input of the first interface IF1; If (22) the first predetermined data message is received via the first interface IF1 in this first time At, carry out the following steps:

in the event (23) that the first predetermined data message signals a first application I:

- Carrying out (23) an auto-addressing method by means of a GPIO method to determine a valid bus node address for the circuit;

in the event (24) that the first predetermined data message signals a second application II:

- Carrying out (24) an auto addressing method by means of a daisy chain method to determine a valid bus node address for the circuit;

in the event (25) that the first predetermined data message signals a third application III with signaling of a positioning as the first sensor S1: - Signaling (25) an application III to the subsequent circuits IC of the subsequent sensors in the data bus chain by means of the second interface IF2 and

- Signaling (25) to the subsequent circuits IC of the subsequent sensors in the data bus chain by means of the second interface IF2 that they are positioned as the subsequent sensor S1;

Configuration (25) of the second interface IF2 in accordance with a second data bus protocol, if this is not the same as the first data bus protocol;

for the case (26) that the first predetermined data message signals a third application III with signaling of a positioning as according to the following sensor:

- Implementation (26) of an auto-addressing method using a GPIO method to determine a valid bus node address for the subsequent circuits IC of the subsequent sensors;

Configuration (26) of the first interface IF1 in accordance with a second data bus protocol, if this is not the same as the first data bus protocol;

in the event (27) that the first predetermined data message signals a fourth application IV with signaling of a positioning as the first sensor S1:

- Signaling (27) of an application IV to the subsequent circuits IC of the subsequent sensors in the data bus chain by means of the second interface IF2 and

- Signaling (27) to the subsequent circuits IC of the subsequent sensors in the data bus chain by means of the second interface IF2 that they are positioned as the subsequent sensor S1;

- Configuration (27) of the second interface IF2 according to a second data bus protocol, if this is not the same as the first data bus protocol;

in the event (28) that the first predetermined data message signals a fourth application IV with signaling of a positioning as according to the following sensor: - Implementation (28) of an auto addressing method by means of a daisy chain method to determine a valid bus node address for the subsequent circuits IC of the subsequent sensors;

Configuration (28) of the first interface IF1 according to a second data bus protocol, if this is not the same as the first data bus protocol;

If (29) no first predetermined data message is received via the first interface IF1 in this first time period At and the logic level at the input of the first interface IF1 was a logic 1 in this first time At, carry out the following steps:

- Signaling (30) an "application V or VI" to the subsequent circuits IC of the subsequent sensors in the data bus chain by means of the second interface IF2 and

- Signaling (30) to the following circuits IC of the sensors following in the data bus chain by means of the second interface IF2 that they are positioned as the following sensor S1;

If (31) after a second period At ₂ in the context of an auto addressing process by means of a daisy chain process there is no signaling to the circuit IC about the successful implementation of this auto addressing process by means of a daisy chain process, signaling of an "application V" to the circuit IC of the subsequent sensors;

- Configuration (31) of the second interface IF2 according to a second data bus protocol, if this is not the same as the first data bus protocol.

If (32) no first predetermined data message is received via the first interface IF1 in this first time At and the logical level at the input of the first interface IF1 was a logical 0 in this first time At, carry out the following steps:

- Carrying out (33) an auto addressing method by means of a daisy chain method to determine a valid bus node address;

If (34) after a second time period At ₂ the signaling of an application V is received via the first interface IF1, through Carrying out an auto addressing process using a GPIO process to determine a valid bus node address;

- Configuration (34) of the first interface IF1 according to a second data bus protocol, if this is not the same as the first data bus protocol. Method for configuring an ultrasonic sensor for use in a circuit IC

with a first connection and

with a second connector and

with a third connector and

with a fourth port and

with a first interface IF1 and

with a second interface IF2 and

with a first GPIO interface GPIOl and

with a second GPIO interface GPI02,

wherein the circuit is part of the ultrasonic sensor and

wherein the first interface IF1 is connected to the first connection and wherein the first interface IF1 can be operated according to a first data bus protocol and

wherein the first interface IF1 can be operated as a digital input and

wherein the first interface IF1 can be operated as a low-side driver and

w ith th e c h r i t t e n

Reset (20) the circuit IC and

Low-resistance driving (20) of the output of the second interface IF2 to a logical 0 and Configuring (20) the first interface IF1 according to the first data bus protocol;

Waiting (21) for a first time At for a first predetermined data message to be received via the first interface IF1 by overwriting the high-resistance 1 at the input of the first interface IF1; If (22) the first predetermined data message is received via the first interface IF1 in this first time At, carry out the following steps:

in the event (25) that the first predetermined data message signals a third application III with signaling of a positioning as the first sensor S1:

- Signaling (25) an application III to the subsequent circuits IC of the subsequent sensors in the data bus chain by means of the second interface IF2 and

- Configuration (25) of the second interface IF2 according to a second data bus protocol, if this is not the same as the first data bus protocol.

for the case (26) that the first predetermined data message signals a third application III with signaling of a positioning as according to the following sensor: - Implementation (26) of an auto-addressing method using a GPIO method to determine a valid bus node address for the subsequent circuits IC of the subsequent sensors;

- Configuration (26) of the first interface IF1 according to a second data bus protocol, if this is not the same as the first data bus protocol.

- Configuration (27) of the second interface IF2 according to a second data bus protocol, if this is not the same as the first data bus protocol.

in the event (28) that the first predetermined data message signals a fourth application IV with signaling of a positioning as according to the following sensor:

- Implementation (28) of an auto addressing method by means of a daisy chain method to determine a valid bus node address for the subsequent circuits IC of the subsequent sensors;

- Configuration (28) of the first interface IF1 according to a second data bus protocol, if this is not the same as the first data bus protocol.

If (29) no first predetermined data message is received via the first interface IF1 in this first time period At and the logic level at the input of the first interface IF1 was a logic 1 in this first time At, carry out the following steps: - Signaling (30) an "application V or VI" to the subsequent circuits IC of the subsequent sensors in the data bus chain by means of the second interface IF2 and

If (31) after a second period At ₂ in the context of an auto addressing process by means of a daisy chain process no signaling to the circuit IC about the successful implementation of this auto addressing process by means of a daisy chain process takes place, signaling of an application V to the Circuits IC of the following sensors;

If (34) after a second period At ₂ the signaling of an application V is received via the first interface IF1, implementation of an auto-addressing method using a GPIO method to determine a valid bus node address;

- Configuration (34) of the first interface IF1 according to a second data bus protocol, if this is not the same as the first data bus protocol. Circuit IC for controlling one or more ultrasonic transducers and / or one or more ultrasonic transmitters and / or one or more ultrasonic receivers,

the circuit IC having means to be able to carry out a method in order to recognize whether it is either in one of the applications from a first set of applications,

wherein the first set of applications comprises at least two applications and / or three applications and / or four applications of application I and application II and application III and application IV, or whether he is instead in one of the applications from a second set of Applications is located

wherein the second set of applications comprises at least one application and / or two applications of application V and application IV, method for execution in a circuit IC for controlling one or more ultrasonic transducers and / or one or more ultrasonic transmitters and / or one or more ultrasound receivers,

the method comprising steps of recognizing

whether it is either in one of the applications from a first set of applications,

wherein the first set of applications comprises at least two applications and / or three applications and / or four applications of application I and application II and application III and application IV,

or whether it is instead in one of the applications from a second set of applications,

wherein the second set of applications comprises at least one application and / or two applications of application V and application IV, circuit IC for controlling one or more ultrasonic transducers and / or one or more ultrasonic transmitters and / or one or more ultrasonic receivers,

wherein the circuit is provided to form a sensor with the one or more ultrasonic transducers and / or the one or more ultrasonic transmitters and / or the one or more ultrasonic receivers for the purposes of this claim, and

wherein the sensor and / or the circuit IC can have several, but at least two, states and The circuit IC has means to emit signals and / or error signals via the one or more ultrasonic transducers and / or via the one or more ultrasonic transmitters and / or commands via the one or more ultrasonic receivers as a function of the at least two states Receive ultrasonic receivers. circuit according to point 5,

wherein the circuit has means for data transmission of measurement results to a superordinate device ECU by means of a data connection and

the circuit IC emits an error message as a signal and / or error signal via the one or more ultrasonic transducers and / or via the one or more ultrasonic transmitters when the data connection is faulty and / or interrupted. Method for a circuit IC for controlling one or more ultrasonic transducers and / or one or more ultrasonic transmitters and / or one or more ultrasonic receivers,

wherein the sensor and / or the circuit IC several, but at least two,

Can have states and

the method comprising the steps of:

Emission of a signal or signals and / or emission of an error signal or error signals via the one or more ultrasonic transducers of the sensor and / or via the one or more ultrasonic transmitters of the sensor, the emission taking place as a function of the at least two states , and or

Receipt of a command or of commands via an ultrasonic receiver or several ultrasonic receivers of the sensor. Method according to point 7, wherein a radiated signal is an error message and / or an error signal. Method according to item 8, wherein the error signal is emitted when a certain data connection between the sensor and a superordinate device is faulty and / or interrupted.

REFERENCE LIST

At, At ₂ period

GPIOl first I / O interface

GPI02 second I / O interface

IF1 first data bus interface

IF2 second data bus interface

S1 to S8 sensors

WEA1 transducer element connection

WEA2 transducer element connection

BUZ display unit

pC microcomputer

ECU bus master

GND reference potential connection

IC circuit

LIN first data bus line

VCC supply potential connection

d data bus interfaces

privDB second data bus line

TR transducer element

TRI to TR8 Ultrasonic TransducerSu power supply

Rx receiver

Tx transmitter

List of the cited writings

DE-A-10 2017 118 565

DE-A-10 2014 115 000

DE-U-20 2018 006 079

US-A-2006/0273927

US-A-2017/0083468

US-A-2019/0041504

Claims

EXPECTATIONS

1. A circuit for the connection of an ultrasonic transducer element which emits ultrasonic signals and / or which receives ultrasonic signals to a communication data bus which can have one of several configurations, the circuit being provided with

at least one converter element connection (WEA1, WEA2),

a reference potential connection (GND),

a supply potential connection (VCC),

a first data bus interface (IF1),

a second data bus interface (IF2),

a first I / O interface (GPIO1) that can be operated by programming as an input or output or programming binary with a pin coding potential and

a second I / O interface (GPI02) that can be operated as an input or output by programming or can be operated in binary with a pin coding potential,

a microcomputer for processing data and / or signals that can be received or sent via the two data bus interfaces (IF1, IF2) and the two I / O interfaces (GPIOl, GPI02) and the at least one converter element connection,

wherein the first data bus interface (IF1) can be operated according to a first data bus protocol or according to a second data bus protocol different from the first data bus protocol, or as an input or as a driver for operating an optical and / or graphic and / or acoustic display unit (BUZ),

wherein the second data bus interface (IF2) can be operated according to the first data bus protocol or according to the second data bus protocol different from the first data bus protocol or as an input or as a driver for operating an optical and / or graphic and / or acoustic display unit (BUZ),

wherein the first data bus interface (IF1) can be connected to a first data bus which has a bus master and to which the first data bus interfaces (IF1) of further circuits can be connected,

wherein the second data bus interface (IF2) with the first data bus interface (IF1) connected to a first data bus (LIN) to one of the first data bus (LIN) separate, different second data bus (privDB) can be connected to which the first or the second data bus interface (IF1, IF2) of further circuits can be connected,

The second I / O interface (GPI02) of a circuit can be serially connected to the first I / O interface (GPIO1) of a further circuit and through this serial connection the one further circuit or several are serially connected to the one further circuit and to one another further circuits can be addressed,

where either one of the two I / O interfaces (GPIOl, GPI02) or both I / O interfaces (GPIOl, GPI02) and possibly one of the two data bus interfaces (IF1, IF2) in their operation as an input for addressing the circuit through connection coding is ver bindable with a reference potential or are and

whereby one of the two data bus interfaces (IF1, IF2), i.e. e.g. the first data bus interface (IF1) for operating the display unit (BUZ) can be connected to it and the other of the two data bus interfaces, i.e. e.g. the second data bus interface (IF2) can be connected to a data bus (privDB) to which the first data bus interfaces (IF1) of further circuits or the second data bus interfaces (IF2) of further circuits can be connected.

2. Data bus system with

several circuits (IC) according to claim 1,

a bus master (ECU) and

a data bus line (LIN) to which the bus master (ECU) and the multiple circuits (IC) are connected,

the multiple circuits (IC) being connected to the data bus line (LIN) either with their respective first data bus interfaces (IF1) or their respective second data bus interfaces (IF2) for the purpose of data communication with the bus master and / or with one another,

wherein the two I / O interfaces (GPIOl, GPI02) and the data bus interfaces (IF1, IF2) not used for data communication of a first circuit (IC) according to claim 1 are not connected to the data bus line (LIN) and

whereby the two I / O interfaces (GPIOl, GPI02) of all other circuits (IC) according to claim 1 or the two I / O interfaces (GPIOl, GPI02) and the data bus interfaces (IF1, IF2) not used for data communication of all other circuits (IC) according to claim 1 are connected to the reference potential in different combinations for addressing by means of pin coding.

3. Data bus system with

several circuits (IC) according to claim 1,

a bus master (ECU) and

whereby the data bus interfaces (IF1, IF2) of all circuits (IC) not required for data communication are not connected, the first I / O interface (GPIOl) of a first circuit (IC) according to claim 1 and the second I / O Interface (GPI02) of a second circuit (IC) according to Claim 1 are not connected to the data bus line (LIN) and

wherein further circuits (IC) according to claim 1 for the purpose of automatic addressing of at least these further circuits (IC) and optionally also the second circuit (IC) and / or optionally also the first circuit (IC) in series with the first circuit (IC) and the second circuit (IC) are connected, that the second I / O interface (GPI02) of the first circuit (IC) and each further circuit (IC) with the first I / O interface (GPIOl) of one of the further circuits (IC) or the next further circuit (IC) is connected and the second I / O interface (GPI02) of the last further circuit (IC) is connected to the first I / O interface (GPIO1) of the second circuit (IC).

4. Data bus system with

several circuits (IC) according to claim 1,

a bus master (ECU),

a first data bus line (LIN) and

a second data bus line (privDB), wherein the bus master (ECU) and the first data bus interface (IF1) are at least one first circuit (IC) according to claim 1 connected to the data bus line (LIN) for the purpose of data communication,

wherein the second data bus interface (IF2) at least one of the first circuits (IC) and the second data bus interfaces (IF2) or the first data bus interfaces (IF1) of further circuits (IC) according to claim 1 are connected to the second data bus line (privDB),

wherein the data bus interfaces (IF1, IF2) not used for data communication of any further circuit (IC) are not connected to any of the data bus lines (LIN, privDB) and

whereby the two I / O interfaces (GPIOl, GPI02) of all other circuits (IC) according to claim 1 or the two I / O interfaces (GPIOl, GPI02) and the data bus interfaces not used for data communication (IF1, IF2) of all others Circuits (IC) according to Claim 1, each in different combinations, are connected to the reference potential for addressing by means of pin coding.

5. Data bus system with

several circuits (IC) according to claim 1,

a bus master (ECU),

a first data bus line (LIN) and

a second data bus line (privDB),

wherein the bus master (ECU) and the first data bus interface (IF1) are at least one first circuit (IC) according to claim 1 connected to the data bus line (LIN) for the purpose of data communication,

wherein the first I / O interface (GPIOl) of a first further circuit (IC) according to claim 1 and the second I / O interface (GPI02) of a second white direct circuit (IC) according to claim 1 not to the second data bus line (privDB ) are connected and

wherein the other further circuits (IC) according to claim 1 for the purpose of automatic addressing at least these further circuits (IC) and optionally also the first further circuit (IC) and / or optionally if also the second further circuit (IC) are serially connected to the first further circuit (IC) and the second further circuit (IC) in such a way that the second I / O interface (GPI02) of the first further circuit (IC) and each further circuit (IC) is connected to the first I / O interface (GPIOl) of one of the further circuits (IC) or the next further circuit (IC) and the second I / O interface (GPI02) of the last further circuit ( IC) is connected to the first I / O interface (GPIOl) of the second further circuit (IC).

6. Data bus system with

several circuits (IC) according to claim 1,

a display unit (BUZ) and

a data bus line (privDB),

wherein the first data bus interface (IF1) of a first circuit (IC) according to claim 1 for operating the display unit (BUZ) is connected to this, the second data bus interface (IF2) of the first circuit (IC) being connected to the data bus line (privDB),

wherein the first data bus interface (IF1) or the second data bus interface (IF2) of further circuits (IC) according to claim 1 are connected to the data bus line (privDB),

wherein the two I / O interfaces (GPIOl, GPI02) and the data bus interfaces (IF1, IF2) not used for data communication of the further circuits (IC) according to claim 1 are not connected to the data bus line (privDB) and

whereby the two I / O interfaces (GPIOl, GPI02) of all other white direct circuits (IC) according to claim 1 or the two I / O interfaces (GPIOl, GPI02) and the data bus not used for data communication (IF1, IF2) All other further circuits (IC) according to claim 1 are connected to the reference potential in different combinations for addressing carried out by pin coding.

7. Data bus system with

several circuits (IC) according to claim 1,

a display unit (BUZ) and

a data bus line (privDB), wherein the first data bus interface (IF1) of the first circuit (IC) according to claim 1 for operating the display unit (BUZ) is connected to it, the second data bus interface (IF2) of a first circuit (IC) being connected to the data bus line (privDB),

wherein the first I / O interface (GPIOl) of a first further circuit (IC) according to claim 1 and the second I / O interface (GPI02) of a second white direct circuit (IC) according to claim 1 not to the data bus line (privDB) are connected and

wherein the other further circuits (IC) according to claim 1 for the purpose of automatic addressing at least these further circuits (IC) and optionally also the first further circuit (IC) and / or optionally also the second further circuit (IC) in series with the first further circuit (IC) and the second further circuit (IC) are connected that the second I / O interface (GPI02) of the first further circuit (IC) and each further circuit (IC with the first I / O interface ( GPIOl) one of the further circuits (IC) or the next further circuit (IC) is connected and the second I / O interface (GPI02) of the last further circuit (IC) with the first I / O interface (GPIOl) the second white direct circuit (IC) is connected.