CN113661688B - Circuit for connecting a measuring transducer - Google Patents

Circuit for connecting a measuring transducer Download PDF

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Publication number
CN113661688B
CN113661688B CN202080027422.1A CN202080027422A CN113661688B CN 113661688 B CN113661688 B CN 113661688B CN 202080027422 A CN202080027422 A CN 202080027422A CN 113661688 B CN113661688 B CN 113661688B
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China
Prior art keywords
data bus
circuit
interface
gpio
sensor
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CN202080027422.1A
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CN113661688A (en
Inventor
丹尼斯·克里斯
安德列·施密特
斯蒂芬妮·霍佩考森
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Elmers Semiconductor Europe
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Elmers Semiconductor Europe
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Priority claimed from DE102019103223.7A external-priority patent/DE102019103223B4/en
Priority claimed from DE102019103222.9A external-priority patent/DE102019103222B3/en
Priority claimed from DE102020100425.7A external-priority patent/DE102020100425B3/en
Application filed by Elmers Semiconductor Europe filed Critical Elmers Semiconductor Europe
Publication of CN113661688A publication Critical patent/CN113661688A/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/003—Transmission of data between radar, sonar or lidar systems and remote stations
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
    • G01S15/87—Combinations of sonar systems
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
    • G01S15/88—Sonar systems specially adapted for specific applications
    • G01S15/93—Sonar systems specially adapted for specific applications for anti-collision purposes
    • G01S15/931—Sonar systems specially adapted for specific applications for anti-collision purposes of land vehicles
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming
    • H04L61/50—Address allocation
    • H04L61/5038—Address allocation for local use, e.g. in LAN or USB networks, or in a controller area network [CAN]

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  • Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • Acoustics & Sound (AREA)
  • Small-Scale Networks (AREA)

Abstract

The present invention relates to a circuit (IC) for operating one or more ultrasonic transducers and/or one or more ultrasonic transmitters and/or one or more ultrasonic receivers. The circuit (IC) comprises means for determining in which application the ultrasonic transducer or ultrasonic transmitter or ultrasonic receiver is used. The corresponding method is to claim a part of the content. Thus, the sensor may, for example, determine: whether the bus address is determined by means of plug coding or by means of a daisy chain method.

Description

Circuit for connecting a measuring transducer
Technical Field
The present patent application claims priority from german patent application 10 2019 103 221.0, 2019, 2, 8, 10 2019 103 222.9, 2019, 2, 8, 10 2019 103 223.7, 2019, 2, 8, and 1020220, 100, 425.7, 10, 2020, the contents of which are hereby incorporated by reference into the subject matter of the present patent application.
The present invention relates to a circuit for connecting a measuring transducer and in particular an ultrasonic measuring transducer element of an ultrasonic measuring system for transmitting ultrasonic signals and/or receiving ultrasonic signals to a communication data bus, which may have one of a plurality of configurations. The invention further relates to a differently configured data bus system having such a circuit.
Background
Current integrated circuit systems for manipulating ultrasonic transducers in automotive ultrasonic systems typically have only one communication interface (e.g., a LIN bus interface, although other bus systems are also contemplated) in order to exchange data between a superordinate control unit (e.g., ECU) and one or more ultrasonic sensors. In this case, the ECU acts as a bus master and is responsible not only for communication but also for processing individual ultrasound measurements at the system level.
In addition, there are ultrasound systems in which individual sensors communicate with each other and process data. LIN communication or other bus protocols may likewise be used herein. The specifically selected sensor takes over the (partial) task of the classical control unit and conveys the result that has been evaluated or merely manipulates a loudspeaker/buzzer or, in general, (for example, a warning) display unit (optical, graphic form) in order to signal the distance of the driver from the obstacle.
Fig. 1a shows such an ultrasound system as a block diagram based on the LIN bus system common today according to the prior art.
Fig. 1b shows such an ultrasound system as a block diagram based on a common LIN bus system of today with a private data bus privDB between the individual sensors (bus nodes) according to the prior art, which is not further defined. In this case, a standard LIN bus is used only between the control device ECU and the first sensor S1.
Fig. 1c shows such an ultrasound system as a block diagram based on a common LIN bus system of today with a private data bus privDB between the individual sensors (bus nodes) according to the prior art, which is not further defined. Unlike fig. 1a and 1b, the system in fig. 1c does not possess its own bus master ECU. Instead, one of the sensors, preferably the first sensor S1 takes over the role. The sensor typically comprises a small computer which takes over the character and can give an alarm to the vehicle driver via a signaling device (buzzer/loudspeaker).
The aforementioned applications according to fig. 1a, 1b and 1c have different requirements for the manipulation of the data bus interface or the signaling device (buzzer/loudspeaker), so that these different applications cannot be implemented with structurally identical circuits.
Alternative solutions to circuitry for steering one or more ultrasonic transducers and/or one or more ultrasonic transmitters and/or one or more ultrasonic receivers and methods for configuring an ultrasonic transmitter for use in the circuitry are known from documents US-se:Sup>A 2019/0041504, US-se:Sup>A-2006/0273927 and DE-se:Sup>A 10 2017 118 565. None of these documents solves the problem of how the different applications mentioned above can be implemented with circuits of the same structure.
DE-A-10 2014 115 000 describes a method for functional testing of an ultrasonic transmission device for a motor vehicle. During the measurement operation, i.e. for example in production or in a workshop, the functional capacity of the ultrasonic sensor device is checked by means of a diagnostic device on the basis of the emission signal and/or the measurement signal.
In particular, ultrasonic measuring systems in the automotive field can be implemented as low-cost solutions and high-end implementations. Sometimes, for example, it is sufficient when an acoustic signal is output as a signal for the distance of the vehicle from the obstacle not exceeding a minimum value. In such applications, it may not be necessary to evaluate whether a signal has to be output based on an ECU or similar relatively complex central evaluation and control unit. For example, it is proposed here to give one of the circuits in which the individual ultrasonic sensors are arranged a certain "intelligence" in order to be able to control the warning display by means of this circuit.
Other systems again in the high-end sector have, in particular, also graphic or camera representations of the surroundings of the vehicle. In any case, more complex evaluation electronics are required, to which a large number of ultrasonic sensors or also a plurality of ultrasonic sensor bus systems are connected if necessary. However, in the last-mentioned case, it may be expedient to reduce the tasks or subtasks of the central evaluation and control unit, so that the circuit of one of these sensors is equipped with additional intelligence for each connected sensor bus.
In the above concept, further add: a simple addressing possibility of different sensors connected to different bus systems may be required. This also works, therefore, which involves a complexity or reduction in complexity of such a system. As addressing options, what is known as pin or plug coding is provided here or also addressing options which are known, for example, in daisy-chained data bus systems for individual bus users which are chained in series.
Disclosure of Invention
The object of the present invention is to provide a circuit for electrically operating a transducer element and in particular for an ultrasonic transducer element, which allows the transducer element and thus the entire measuring system to be wired according to different concepts for data communication and address assignment.
In order to solve this problem, a circuit for connecting an ultrasonic measuring transducer element (connecting an ultrasonic measuring transducer element of an ultrasonic measuring system to a communication data bus, which may have one of a plurality of configurations) for transmitting an ultrasonic signal and/or receiving an ultrasonic signal is proposed with the present invention, wherein the circuit is provided with
At least one converter element terminal WEA1, WEA2,
a reference potential terminal GND,
a supply potential terminal VCC,
a first data bus interface IF1,
a second data bus interface IF2,
a first I/O interface GPIO1, which can be programmed to operate as a (e.g. digital) input or output or can be programmed to operate binary with pin-coded potentials, and
a second I/O interface GPIO2, which can be programmed to operate as a (e.g. digital) input or output or can be programmed to operate binary with pin-coded potentials, and
a microcomputer for processing (analog and/or digital) data and/or signals receivable or to be transmitted via two data bus interfaces IF1, IF2 and two I/O interfaces GPIO1, GPIO2 and at least one converter element terminal,
wherein the first data bus interface IF1 can be operated according to a first data bus protocol or according to a second data bus protocol different from the first data bus protocol or as (e.g. digital) input or as a driver for operating the optical and/or graphic and/or acoustic (e.g. warning) display unit BUZ,
wherein the second data bus interface IF2 can be operated according to a first data bus protocol or according to a second data bus protocol different from the first data bus protocol or as an input or as a driver for operating the optical and/or graphic and/or acoustic (e.g. warning) display unit BUZ,
Wherein the first data bus interface IF1 can be connected to a first data bus having a bus master and to which the first data bus interface IF1 of the other circuits can be connected (see further below under application I and under application II and in fig. 4),
wherein the second data bus interface IF2 can be connected to a different second data bus privDB, separate from the first data bus LIN, when the first data bus interface IF1 is connected to the first data bus LIN, to which the first or first data bus interface IF1, IF2 of the other circuit can be connected (see further below under application III and in fig. 5, under application IV and in fig. 6, under application V and in fig. 7 and under application VI and in fig. 8),
wherein the second I/O interface GPIO2 of the circuit can be connected in series with the first I/O interface GPIO1 of one other circuit and via this series connection the one other circuit or a plurality of other circuits connected in series with the one other circuit and with each other can be addressed (see further below under application II and in figure 4, under application IV and in figure 6 and under application VI and in figure 8),
In which optionally one of the two I/O interfaces GPIO1, GPIO2 or one of the two I/O interfaces GPIO1, GPIO2 and, IF appropriate, one of the two data bus interfaces IF1, IF2 can be connected as (for example digital) input to a reference potential for addressing the circuit by means of terminal coding (see further below under application I and in fig. 3, under application III and in fig. 5 and under application V and in fig. 7) and
one of the two data bus interfaces IF1, IF2, i.e. for example the first data bus interface IF1, can be connected to the display unit BUZ for operation (e.g. warning), and the other of the two data bus interfaces, i.e. for example the second data bus interface IF2, can be connected to the data bus privDB, the first data bus interface IF1 of the other circuit or the second data bus interface IF2 of the other circuit can be connected to the data bus (see further below under application V and under application VI and in fig. 8).
The circuit according to the invention can be connected to a reference potential and a supply potential of the on-board electrical system by means of a hexapole plug, and can be connected to different data communication schemes. The circuit according to the invention likewise has at least one terminal towards the converter element.
As described above, two data communication interfaces and two I/O interfaces of the circuit may be configured. The individual configuration possibilities are mentioned above and will be elucidated further and described in detail below.
With the circuit according to the invention, a connection element configurable in multiple aspects between the sensor system (sensor hardware) and the power supply and data communication in the vehicle is described. This completely decisively reduces the assembly effort and logistics for the vehicle suppliers and vehicle manufacturers; because one of the two companies, or both, can now program the microcomputer by installing the corresponding software so that the final installed circuit corresponds to the respectively desired configuration.
According to a first possible application corresponding to the concept according to fig. 1a and which will be described further below in connection with fig. 3, a data bus system can be realized with the invention, said data bus system being provided with:
a plurality of circuit ICs according to the invention,
-a bus master ECU, and
the bus master ECU and the data bus line LIN to which the plurality of circuit ICs are connected,
wherein for data communication with the bus master and/or with each other a plurality of circuit ICs are connected to the data bus line LIN either with their respective first data bus interface IF1 or with their respective second data bus interface IF2,
In which the data bus interface IF1, IF2 and the two I/O interfaces GPIO1, GPIO2 of the first circuit IC according to the invention, which are not used for data communication, are not connected to the data bus line LIN (and are connected to a potential representing this by means of control by a microcomputer IF necessary) and
wherein the two I/O interfaces GPIO1, GPIO2 of all other circuit ICs according to the invention or the data bus interfaces IF1, IF2 of all other circuit ICs according to the invention not used for data communication and the two I/O interfaces GPIO1, GPIO2 are connected in respectively different combinations with reference potentials for addressing by pin coding.
According to a second possible application corresponding to the concept according to fig. 1a and which will be described further below in connection with fig. 4, a data bus system can be realized with the invention, said data bus system being provided with:
a plurality of circuit ICs according to the invention,
-a bus master ECU, and
a data bus line LIN to which the bus master ECU and the plurality of circuit ICs are connected,
wherein for data communication with the bus master and/or with each other a plurality of circuit ICs are connected to the data bus line LIN either with their respective first data bus interface IF1 or with their respective second data bus interface IF2,
The data bus interfaces IF1, IF2 of all the circuit ICs which are not required for the data communication are not connected (and IF necessary by means of a potential connection to a potential representative of this by microcomputer control),
wherein the first I/O interface GPIO1 of the first circuit IC according to the invention and the second I/O interface GPIO2 of the second circuit IC according to the invention are not connected to the data bus line LIN (and are connected to a potential representing this by means of control by a microcomputer, if necessary), and
wherein the further circuit ICs according to the invention are connected in series with the first circuit IC and the second circuit IC for the purpose of automatically addressing at least these further circuit ICs and optionally also the second circuit IC and/or optionally also the first circuit IC, such that the second I/O interface GPIO2 of the first circuit IC and each further circuit IC is connected with the first I/O interface GPIO1 of one or the next further circuit IC and the second I/O interface GPIO2 of the last further circuit IC is connected with the first I/O interface GPIO1 of the second circuit IC.
According to a third possible application corresponding to the concept according to fig. 1b and further described below in connection with fig. 5, a data bus system can be realized with the invention, said data bus system being provided with:
A plurality of circuit ICs according to the invention,
the bus master ECU is configured to,
-first data bus line LIN and
a second data bus line privDB,
wherein the first data bus interface IF1 of the at least one first circuit IC and the bus master ECU according to the invention are connected to the data bus line LIN for data communication purposes,
wherein the second data bus interface IF2 of at least one of the first circuit ICs and the first data bus interface IF1 or the second data bus interface IF2 of the other circuit ICs according to the invention are connected to the second data bus line privDB, wherein the data bus interfaces IF1, IF2 of each other circuit IC which are not used for data communication are not connected to one of the data bus lines LIN, privDB (and IF necessary by means of a potential connection to a potential representative of this by means of a microcomputer control) and
wherein all other two I/O interfaces GPIO1, GPIO2 of the circuit IC according to the invention or all other data bus interfaces IF1, IF2 of the circuit IC according to the invention not used for data communication and the two I/O interfaces GPIO1, GPIO2 are connected in respectively different combinations with reference potentials for addressing by pin coding.
According to a fourth possible application corresponding to the concept according to fig. 1b and which will be described further below in connection with fig. 6, a data bus system can be realized with the invention, which data bus system is provided with
A plurality of circuit ICs according to the invention,
the bus master ECU is configured to,
-first data bus line LIN and
a second data bus line privDB,
wherein the first data bus interface IF1 of the at least one first circuit IC and the bus master ECU according to the invention are connected to the data bus line LIN for data communication purposes,
wherein the second data bus interface IF2 of at least one of the first circuit ICs and the first data bus interface IF1 or the second data bus interface IF2 of the further circuit ICs according to the invention are connected to the second data bus line privDB, -wherein the first I/O interface GPIO1 of the first further circuit IC according to the invention and the second I/O interface GPIO2 of the second further circuit IC according to the invention are not connected to the second data bus line privDB (and are connected to a potential representative of this by means of a microcomputer control, IF necessary) and
wherein a further circuit IC according to the invention is connected in series with the first further circuit and the second further circuit IC for the purpose of automatically addressing at least these further circuit ICs and, if necessary, the first further circuit IC and/or, if necessary, the second further circuit IC, such that the first further circuit IC and the second I/O interface GPIO2 of each further circuit IC are connected with the first I/O interface GPIO1 of one or the next further circuit IC and the second I/O interface GPIO2 of the last further circuit IC is connected with the first I/O interface GPIO1 of the second further circuit IC.
According to a fifth possible application corresponding to the concept according to fig. 1c and which will be described further below in connection with fig. 7, a data bus system can be realized with the invention, which data bus system is provided with
A plurality of circuit ICs according to the invention,
BUZ and (e.g. warning) display unit
The data bus line privDB,
wherein the first data bus interface IF1 of the first circuit IC according to the invention is connected to the (e.g. warning) display unit BUZ for operating said (e.g. warning) display unit BUZ,
wherein the second data bus interface IF2 of the first circuit IC is connected to the data bus line privDB,
wherein the second data bus interface IF2 or the first data bus interface IF1 of the further circuit IC according to the invention is connected to a data bus line privDB,
wherein the two I/O interfaces GPIO1, GPIO2 of the further circuit IC according to the invention and the data bus interfaces IF1, IF2 not used for data communication are not connected to the data bus line privDB (and are connected to a potential representing this by means of a microcomputer control IF necessary) and
wherein the two I/O interfaces GPIO1, GPIO2 of all further other circuit ICs according to the invention or the two I/O interfaces GPIO1, GPIO2 of all further other circuit ICs according to the invention and the data bus interfaces IF1, IF2 not used for data communication are connected in respectively different combinations with reference potentials for addressing by pin coding.
According to a sixth possible application corresponding to the concept according to fig. 1c and further described below in connection with fig. 8, a data bus system can be realized with the invention, which data bus system is provided with
A plurality of circuit ICs according to the invention,
BUZ and (e.g. warning) display unit
The data bus line privDB,
wherein the first data bus interface IF1 of the first circuit IC according to the invention is connected to the (e.g. warning) display unit BUZ for operating said (e.g. warning) display unit BUZ,
wherein the second data bus interface IF2 of the first circuit IC is connected to the data bus line privDB,
wherein the first data bus interface IF1 or the second data bus interface IF2 of the further circuit IC according to the invention is connected to a data bus line privDB,
wherein the first I/O interface GPIO1 of the first further circuit IC according to the invention and the second I/O interface GPIO2 of the second further circuit IC according to the invention are not connected to the data bus line privDB (and if necessary by means of a potential connection to a potential representative of this by microcomputer control) and
-wherein a further circuit IC according to the invention is connected in series with the first further circuit IC and the second further circuit IC for the purpose of automatically addressing at least these further circuit ICs and, if necessary, the first further circuit IC and/or, if necessary, the second further circuit IC, such that the first further circuit IC and the second I/O interface GPIO2 of each further circuit IC are connected with the first I/O interface GPIO1 of one or the next further circuit IC and the second I/O interface GPIO2 of the last further circuit IC is connected with the first I/O interface GPIO1 of the second further circuit IC.
By means of the addressing possibility via the combined input and output terminals of the freely programmable numbers (hereinafter GPIO or GPIO pins) in the integrated sensor circuitry (hereinafter referred to as circuitry) and the second communication interface the above mentioned applications and tasks can be achieved with a circuit of only one configuration. This simplifies the logistics for the user of such circuits and reduces manufacturing costs by scaling effects. Here, the respective applications are realized only by different cable harnesses for electrically connecting the sensors.
In the circuit itself, the different applications are controlled by the logic and/or software of the microcomputer, wherein it is identified which application and which location the sensor is in the cable harness is by querying the interface and GPIO after switching on and/or resetting and/or according to specific requests by signals or by a superordinate system and/or by a timer. This involves a single sensor and/or system.
The inquiry of the interface and the GPIO is characterized in that they can measure the current voltage level at the respective terminals of the circuit with respect to a reference potential (typically ground GND), respectively, and can detect the transformation of the voltage values and/or identify the transmitted protocol.
The manner according to the invention of using configurable circuits, with which in particular the measuring transducer elements can be wired to each other in different configurations, shows an extremely efficient way of solving the problems mentioned at the outset, i.e. several solutions can be covered with the same circuit. Within the scope of the invention it is recognized that it is sufficient in this connection to seek two data bus interfaces in the circuit according to the invention in order to thereby achieve a division of the converter elements into two groups, the circuits of the converter elements of one group being connected to the bus master via a standard data bus, for example a standard LIN bus, and the other group of converter elements being connected via another local data bus (also referred to as a private data bus), wherein the circuits of one of the converter elements of the first group achieve a coupling of the two data buses. The circuit of the converter element then acts in a certain way as a kind of bus master for the circuit of the second set of converter elements and in this connection relieves the bus master of the load, which is coupled via a standard bus system with the circuit of the first set of converter elements (i.e. a circuit if the first set has only one converter element). The circuit to which the two data buses are connected requires two data bus interfaces, while the further circuit does not substantially require such a second data bus interface.
Furthermore, it has proven advantageous to have two so-called general purpose I/O interfaces, which can be programmed as inputs or outputs. The two data bus interfaces can also be operated differently and as data bus interfaces according to a predefined protocol or as drivers or as digital inputs or outputs. For example, the data bus interface and the other two I/O interfaces are configured by means of a microcomputer.
By means of two programmable I/O interfaces, addresses can be assigned via pin or plug codes, which addresses are assigned to the circuit and thus to the converter elements connected to the circuit. In this regard, the number of circuits that can be pin-coded is thereby limited and can advantageously be extended according to the invention in that one of the two data bus interfaces is likewise used for pin coding. As long as a larger number of circuits can be connected to the data bus than is addressable in pin-coded manner by means of three interfaces, two I/O interfaces can be used for coupling a large number of circuits according to the invention in a chained manner in that they are connected to each other in accordance with a daisy-chained manner. This existing additional connection of adjacent circuits in this respect in addition to the communication data bus enables an easy addressing of the individual circuits that can be operated automatically.
Finally, it is also possible with the circuit according to the invention to connect a plurality of converter elements to one another via one or more communication buses (in the sense of no bus master), wherein one of the circuits is used to drive, in particular (warn)), a display unit. For this purpose, one of the two data bus interfaces is used as a driver, while the other data bus interface of the circuit is used for data communication with the other circuit. These other circuits may be addressed either in a pin-coded manner or automatically via the daisy-chain connection already described above.
The versatility of the circuit according to the invention is a practical advantage of the invention.
Drawings
The invention is described in more detail below with reference to an embodiment according to the accompanying drawings. Here, in detail:
1a, 1b and 1c show data bus systems from the prior art,
fig. 2 shows a sensor according to the invention with a circuit IC, which is shown simplified as a block diagram.
Figure 3 shows as a block diagram a data bus system according to application I with a sensor according to figure 2,
figure 4 shows as a block diagram a data bus system according to application II with a sensor according to figure 2,
Figure 5 shows as a block diagram a data bus system according to application III with a sensor according to figure 2,
figure 6 shows as a block diagram a data bus system according to an application IV with a sensor according to figure 2,
figure 7 shows as a block diagram a data bus system according to application V with a sensor according to figure 2,
figure 8 shows as a block diagram a data bus system according to application VI with a sensor according to figure 2,
FIG. 9 illustrates an exemplary process flow for a data bus system, and
fig. 10 shows an embodiment of method steps running within a circuit.
Detailed Description
The device according to the invention is shown in fig. 2. When referring to a sensor in the following, this basically means the circuit via which the sensor is connected to the bus of the respective data bus system.
For this purpose, a suitable ultrasound circuit IC is provided with two standard-compliant interfaces IF1, IF2 and one or more GPIOs. For example, one of the interfaces may be a LIN bus interface.
Fig. 2 shows schematically the corresponding sensor in the form of a functional block. Such a sensor may comprise other blocks which are secondary to the invention and which are not shown for simplicity. Here, the circuit IC preferably contains the following modules:
Power supply Su
In this case functional blocks typically comprising voltage regulators or similar energy supply devices providing electrical energy.
Logic for logic control
In this case digital circuit blocks for the function of the IC, executing protocols, signal processing, evaluating ultrasound measurements, etc. are preferred.
Transmitter Tx
In this case a transmitter for operating an exemplary ultrasound transducer TR or ultrasound transmitter TR.
Receiver Rx
In this case a receiver for receiving signals of an exemplary ultrasound transducer TR or ultrasound receiver TR.
Interface 1IF1
In this case preferably a data interface which is preferably used mainly for communication with the superordinate control device.
Interface 2IF2
In this case preferably a data interface preferably mainly used for communication with other sensors.
General purpose I/O GPIO1, GPIO2
In this case terminals, which are freely programmable to be defined as input and output terminals, and which are preferably used mainly for addressing the sensor.
Measuring transducer element TR
Which is for example an electroacoustic, electro-optical, electromechanical, electromagnetic or other type of measuring transducer element. The invention is described exemplarily for an ultrasonic transducer element, in particular in the form of a transducer.
Measuring transducer element terminal WEA1, WEA2
These are the terminals to which the respective measuring transducer elements are connected.
Microcomputer muC
The microcomputer determines the function of the circuits within the different circuit concepts by its programming.
The circuit IC exchanges signals directly or indirectly with one or more ultrasonic transducers TR, TR1, TR2. By "directly" is meant that the circuit IC is electrically connected directly to one or more ultrasonic transducers TR, TR1, TR 2..tr 8 and/or to one or more ultrasonic transmitters and/or to one or more ultrasonic receivers. By "indirect" is meant that the circuit IC is connected with the one or more ultrasonic transducers TR, TR1, TR 2..tr 8 and/or with the one or more ultrasonic transmitters and/or with the one or more ultrasonic receivers only indirectly via other electrical and/or electronic devices.
The first interface IF1 is the primary data interface to the standard communication data bus of the vehicle. A standard automotive acceptable data interface type is typically used herein. For example, it is particularly preferred to use a LIN interface here. Furthermore, in the case of the LIN interface, this first interface IF1 can be used as a low-side driver in order to operate a loudspeaker/buzzer or a (warning) display unit BUZ which is usually operated optically or graphically IF necessary.
IF the selected sensor has communicated via its first interface IF1 with the standard communication data bus of the vehicle, the second interface IF2 connects the other sensors to each other. The second interface IF2 is a "private" local interface compared to the first interface IF1, so that here standard interfaces (for example LIN interfaces) or interface types reduced in terms of their requirements can be used.
The second interface IF2 may also be used as an additional GPIO pin and/or for address assignment IF it is not used for communication.
In this device the GPIO pins are mainly used for addressing the sensor, irrespective of whether only the first interface IF1 or both interfaces IF1, IF2 are used. The addressing is preferably performed either by connecting the individual GPIOs to GND in the plug (if necessary using current sources and/or pull-up resistors in the sensor) or by, for example, a daisy-chain connection from the GPIO output of the current sensor to the GIPO input of the next sensor.
It has been realized according to the invention that with these sensors according to fig. 2 (IC, PCB and 6-pole plug for VCC, GND, IF, IF2, GPIO1, GPIO 2) the following applications are realized in particular:
1) An application having an ECU as a control device or a superior computer system:
a) Application I (see FIG. 3, corresponding to the concept according to FIG. 1 a)
Standard LIN data bus, in which the bus node address of the sensor is pin-coded via a connection pattern of three pins to a reference potential GND
b) Application II (see FIG. 4, corresponding to the concept according to FIG. 1 a)
Standard LIN data bus, in which the bus node address of a sensor is determined as in the daisy chain method
2) Application with sensors that partly replace ECU as control device or upper computer system:
c) Application III (see FIG. 5, corresponding to the concept according to FIG. 1 b)
To relieve the load of the ECU, the processed data is transmitted to the ECU via one of the sensors (e.g. S1) coupled to the ECU via a standard communication data bus, and the ECU is replaced with respect to the subsequent sensor, wherein the bus node address of the sensor is pin coded via a three pin to reference potential GND connection pattern.
d) Application IV (see FIG. 6, corresponding to the concept according to FIG. 1 b)
In order to relieve the load of the ECU, the processed data is transmitted to the ECU via one of the sensors (e.g. S1) coupled to the ECU via a standard communication data bus, and the ECU is "replaced" with respect to the subsequent sensor, wherein the bus node address of the sensor is determined as in the daisy-chain method.
3) Application without ECU as control device or upper computer system, with display unit operable with one of the sensors therefor
e) Application V (see FIG. 7, corresponding to the concept according to FIG. 1 c)
The first sensor controls a speaker/buzzer or a usual optical and/or graphic and/or acoustic display unit and replaces the ECU with respect to the subsequent sensor, wherein the bus node address of the sensor is pin coded via a connection pattern of three pins to the reference potential GND.
f) Application VI (see FIG. 8, corresponding to the concept according to FIG. 1 c)
The first sensor controls a speaker/buzzer or a typical optical and/or graphic and/or acoustic display unit and replaces the ECU with respect to the subsequent sensor, wherein the bus node address of the sensor is determined as in the daisy chain method.
However, the present invention is not limited thereto. Instead of automatic addressing via the daisy chain method, other automatic addressing methods may also be applied. Thus, the present invention is not limited to the manner in which automatic addressing occurs.
Application I: standard LIN data bus addressed via pin coding (fig. 3)
In the example of fig. 3, the sensor is supplied with electrical energy via VCC line VCC and GND line GND. The power of the VCC line and the GND line is supplied by, for example, a bus master, ECU. The ECU is a bus master of a communication bus, which may be, for example, a LIN data bus LIN. Instead of the ECU, BCM (body control module (Body Control Module)) may be used. These three lines VCC, GND, LIN are connected to each sensor in the application example in fig. 3. The structure of each sensor corresponds to the structure according to fig. 2.
The wiring of the circuit IC of fig. 3 for pin encoding is shown again in the following table.
Sensor for detecting a position of a body IF2 GPIO1 GPIO2
1 - - -
2 - - GND
3 - GND -
4 - GND GND
5 GND - -
6 GND - GND
7 GND GND -
8 GND GND GND
As can be readily seen, the addresses are encoded in the example of fig. 3 by means of the first GPIO pin GPIO1 and the second GPIO pin GPIO2 of the respective circuit ICs, the second interface IF2 of the sensor and the cable harness.
For address assignment on the LIN bus, 3 input pins of the circuit IC are therefore required. In this application, the second interface IF2 and two additional GPIOs of the respective circuit ICs are used for this address assignment. All three pins IF2, GPIO1, GPIO2 use internal pull-up resistors and are therefore high in the unconnected state. By connection to the reference potential GND with a low-level connection. The input circuits of the three terminal pins IF2, GPIO1, GPIO2 determine the voltage value of the respective terminal via the respective voltage measurement after switching on and/or resetting and/or upon request, for example by a software command or by a wired signal transmission and/or periodically, for example controlled by a timer and/or prompted by a watchdog timer. The sensors are therefore assigned different bus node addresses depending on the external wiring.
Application II: standard LIN addressing as in the daisy chain method (fig. 4)
Alternatively to encoding the assignment address via the plug (GPIO with or without IF 2), the GPIOs may also be connected in a daisy-chain configuration according to fig. 4.
The supply voltage VCC, the data bus (for example LIN) and the reference potential line GND are provided by the bus master ECU or BCM and are connected to each sensor (see fig. 4).
For bus node address assignment at a data bus (e.g., LIN), the GPIOs of the sensors of the network are connected in series with each other in a daisy chain configuration. For exemplary usable procedures for assigning addresses, reference is made to DE-U-20 2018006 079 and US-A-2017/0083468. Orientation on the data bus is important to discuss address assignment. The sensor located closer to the bus master ECU in the data bus is located "in front" of such a sensor located farther from the bus master ECU in the data bus than the above-mentioned sensor. The second sensor mentioned later is placed "behind" or "after" the first mentioned sensor in the data bus in this sense. In this sense, the first-mentioned sensor is placed "in front of" or "in front of" the second-mentioned sensor in the data bus. The fully automatic assignment of bus node addresses is then performed, for example, as follows:
1. All GPIO inputs use internal pull-up resistors. As long as no other level is applied, all GPIO terminals GPIO1, GPIO2 of all sensors are thus at logic 1.
2. The first GPIO terminal GPIO1 of the subsequent sensor is always connected to the second GPIO terminal GPIO2 of the previous sensor.
3. The first sensor S1 has no preceding sensor. Thus, its first GPIO terminal is not connected and is therefore always at logic 1.
4. Each sensor without an active bus node address drives its second GPIO terminal GPIO2 to logic 0.
5. The first GPIO terminal GPIO1 of all subsequent sensors then detects this logic 0.
6. Only the first sensor S1 detects a logic 1 at its first GPIO terminal, since there is no sensor before said first sensor forcing its first GPIO terminal GPIO1 to a logic value 0.
7. The first sensor S1, which is the first sensor in the chain of sensors, without a valid bus node address, is thus identified. If the bus master ECU now provides a bus node address for dispatch by means of a dedicated bus instruction, the first sensor S1 accepts this provided bus node address as a valid bus node address and sets its second GPIO terminal GPIO2 to logic 1.
8. Of the sensors without an active bus node address, only the second sensor S2 now detects a logic 1 at its first GPIO terminal, since there is no sensor without an inactive bus node address before this second sensor, which forces its first GPIO terminal GPIO1 to a logic 0.
9. The second sensor S2, which is the first sensor in the chain of sensors without a valid bus node address, is thus identified. If the bus master ECU now provides a bus node address for dispatch by means of a dedicated bus instruction, the second sensor S2 accepts this provided bus node address as a valid bus node address and sets its second GPIO terminal GPIO2 to logic 1.
10. The sensor and the following sensor repeat steps 8 and 9 in a similar manner until all sensors are addressed.
As is well recognized by those skilled in the art, the addressing sequence may also be reversed from the last sensor (S8 in fig. 4) to the first sensor S1 and to some extent. In this case, the bus master ECU may obtain a signal via the first GPIO terminal GPIO1 of the first sensor: the first sensor S1 has obtained a valid bus node address and thus the chain of sensors is fully addressed.
Unlike the above application, this configuration of fig. 4 or the reverse configuration described enables any number of sensors to be allocated. The number thereof may significantly exceed the number described in application I.
Application III: the first sensor (or one of the first sensors) is the bus master of the private data bus and is connected to the ECU via a standard interface, addressed via GPIO (pin) address coding (fig. 5)
In this application outlined in fig. 5, the "intelligence" of the ultrasonic sensor system is located in the first sensor S1 (illustrated by the hatching of the block μc) or typically in that sensor which communicates with the bus master via a standard bus. This means that the sensor takes over the role of a bus master for the subsequent sensor in the private data bus privDB.
In the example of fig. 5, the positions of the second sensor S2, the third sensor S3 and the fourth sensor S4 and thus the respective bus node addresses to be used by the relevant sensors are again encoded by the presence or absence of a connection between the first GPIO terminal GPIO1 and the reference potential line GND and by the presence or absence of a connection between the second GPIO terminal GPIO2 and the reference potential line GND, respectively. In the example of fig. 5, the GPIO terminal of the first sensor S1 is not wired, whereby the first sensor can recognize its role as a bus master of the private data bus privDB. However, this sensor can also acquire its role as a bus master of the private data bus privDB by means of a data word via its first data bus interface IF1 of the first sensor S1.
The first sensor S1 uses its first data bus interface IF1 as a data bus interface for a standard data interface to communicate with the upper control unit ECU. The standard data interface is preferably a LIN bus interface for a LIN data bus LIN.
The first sensor S1 uses its second data bus interface IF2 as a bus master interface for the subsequent private data bus privDB. The private data bus privDB may correspond to other data bus standards if the second data bus interface of the first sensor S1 is configured according to the standard.
The sensor following the first sensor S1 is connected with its first data bus interface IF1 to the private data bus privDB. The private data bus privDB may correspond to other data bus standards IF the first data bus interface IF1 of the sensor following the first sensor S1 is also configured according to this standard.
The first interface of the first sensor S1 here functions as a LIN interface, for example, to the BCM or ECU.
The second interface of the first sensor S1 serves as a local bus interface for the subsequent sensor and as a bus master for the subsequent sensor.
The identification of the bus node address of the sensor following the first sensor S1 of the private data bus privDB is again carried out by means of the pin coding via the GPIO terminals GPIO1, GPIO2 of the sensor as described above for application I. In the example of fig. 5, the second data interface IF2 of the sensor following the first sensor S1 is not used. In principle, however, as in the example of application I, it is also possible to use the second data interface for the address assignment of the bus address of the sensor following the first sensor S1 of the private data bus privDB. In addition to GPIO terminals GPIO1, GPIO2, a second data bus interface IF2 of the sensor, with its first data bus interface IF1 connected to the private data bus privDB, can also be used for pin coding.
Application IV: the first sensor (or one of the first sensors) is the bus master of the private data bus and is connected to the ECU via a standard interface, addressed via a daisy chain like address code (fig. 6)
In this application outlined in fig. 6, the "intelligence" of the ultrasonic sensor system is relocated in the first sensor S1 (illustrated by the hatching of the block μc) or typically in that sensor which communicates with the bus master via a standard bus. This means that the first sensor takes over the role of the bus master for the subsequent sensor in the data bus.
In the example of fig. 6, the positions of the second sensor S2, the third sensor S3 and the fourth sensor S4, and thus the bus node addresses to be used respectively, are determined again via the daisy-chain connection chain of the sensors following the first sensor S1. The daisy chain between the sensors following the first sensor S1 is again established as in application II by the respective connection between the first GPIO terminal GPIO1 of the subsequent sensor and the second GPIO terminal GPIO2 of the preceding sensor. In the example of fig. 6, the second GPIO terminal GPIO2 of the first sensor S1 is connected to the first GPIO terminal GPIO1 of the second sensor S2. The addressing of the private data bus privDB is here preferably carried out from the last sensor of the chain of sensors, which is located "behind" the most and thus is placed after all other sensors, to the first sensor S1, as already mentioned in the description for application II. Thus, the first sensor can recognize in terms of its role as a bus master of the private data bus privDB: all sensors at the private data bus privDB have successfully obtained a valid bus node address. The description above in connection with the flow of application II regarding address assignment applies here in a similar manner and is therefore not repeated here. In the example of fig. 6, the first GPIO terminal GPIO1 of the first sensor S1 is not wired, whereby the first sensor can recognize its role as a bus master of the private data bus privDB.
The first sensor S1 uses its first data bus interface IF1 as a data bus interface for a standard data interface to communicate with the upper control unit ECU. The standard data interface is preferably a LIN bus interface for a LIN data bus LIN.
The first sensor S1 uses its second data bus interface IF2 as a bus master interface for the subsequent private data bus privDB. The private data bus privDB may correspond to other data bus standards if the second data bus interface of the first sensor S1 is configured according to the standard.
The sensor following the first sensor S1 is connected with its first data bus interface IF1 to the private data bus privDB. The private data bus privDB may correspond to other data bus standards IF the first data bus interface IF1 of the sensor following the first sensor S1 may likewise be configured according to the standard.
The second data bus interface IF2 of the sensor following the first sensor S1 is not connected.
Application V: the first sensor is the bus master of the private data bus and controls the speaker/buzzer, addressed via GPIO address encoding (fig. 7)
This application V is outlined in fig. 7 and is very similar to the previous application IV.
In this application, the "intelligence" of the ultrasonic sensor system is in the first sensor S1, or in other words in one of the sensors connected to the display unit and operating the display unit. This means that the first sensor takes over the role of the bus master for the subsequent sensor of the private data bus privDB.
However, the first sensor S1 does not report the system result to the upper control device ECU, but uses its first data interface IF1 as a low-side driver to operate a speaker/buzzer or a usual optical, graphic or acoustic warning display unit.
The sensor following the first sensor S1 of the private data bus privDB is again equipped with a bus node address for the private data bus privDB by means of a pin coding method and a suitable cable harness, similarly to the applications I and III, in that said sensor evaluates its first GPIO terminal GPIO1 and its second GPIO terminal GPIO2.
The identification of the bus node address of the sensor following the first sensor S1 of the private data bus privDB is again carried out by means of the GPIO terminals GPIO1, GPIO2 coding via the sensor as described under application I and under application III. In the example of fig. 7, although the second data interface IF2 of the sensor following the first sensor S1 is not used, it is in principle also possible to use said second data interface for the address assignment of the bus address of the sensor following the first sensor S1 of the private data bus privDB, as in the example of application I and in the example of application III. But the second data interface may also be used for other applications.
Application VI: the first sensor is the bus master of the private data bus and controls the speaker/buzzer, addressed via daisy chain address coding (fig. 8)
This application is shown in fig. 8 and is very similar to the previous application V.
In this application, the "intelligence" of the ultrasonic sensor system is in the first sensor S1, or in other words in one of the sensors connected to the display unit and operating the display unit. This means that the first sensor takes over the role of the bus master for the subsequent sensor in the data bus.
However, the first sensor S1 does not report the system result to the upper control device ECU, but uses its first data interface IF1 as a low-side driver to operate the speaker/buzzer.
The bus node addresses of the sensors following the first sensor S1 of the private data bus privDB are determined again similarly to the applications II and IV by means of the daisy-chain connection chain.
In the example of fig. 8, the second data interface IF2 of the sensor following the first sensor S1 is not used, but may of course be used for other applications.
Method for identifying a current application, according to which sensor is wired
One method by which the circuit ICs of the sensor can be configured or wired according to which of the applications I to VI is determined is for example operated as follows (fig. 9):
step 1
In the first step (1), the circuit IC is reset to an initial state. This may be done, for example, after switching on and/or after a reset instruction is obtained via an additional reset line not depicted in fig. 1 to 8 or as a data bus instruction. Resetting by security logic (e.g., watchdog timer) is also contemplated.
After the reset (1), the first data interface IF1 of the circuit IC does not drive its first terminal, but it can be checked, preferably in terms of logic level, as a function of the data input.
After the reset (1), the second data interface IF2 of the circuit IC does not drive its second terminal, but it can be checked, preferably in terms of logic level, as a function of the data input.
After reset (1), the first GPIO terminal GPIO1 of the circuit IC does not drive its third terminal, but it can be checked, preferably in terms of functionality as a data input, according to a logic level.
After reset (1), the second GPIO terminal GPIO2 of the circuit IC does not drive its fourth terminal, but it can be checked, preferably in terms of functionality as a data input, according to a logic level.
If the first terminal of the circuit IC is not externally rewritten by a low impedance logic 0, the first terminal is pulled to logic 1 with high impedance by an internal first pull-up circuit.
If the second terminal of the circuit IC is not externally rewritten by a low impedance logic 0, the second terminal is pulled to logic 1 with high impedance by an internal second pull-up circuit.
If the third terminal of the circuit IC is not externally overwritten by a low impedance logic 0, the third terminal is pulled to logic 1 with high impedance through an internal third pull-up circuit.
If the fourth terminal of the circuit IC is not externally rewritten by a low impedance logic 0, it is pulled to logic 1 with high impedance by an internal fourth pull-up circuit.
Step 2
The circuit IC drives a logic 0 with its second interface IF2 and waits a predetermined time Δt after reset. During this time, the circuit IC configures its first data interface IF1 as a data interface of the first data bus standard, for example as a LIN interface.
Case 2 a): IF the circuit IC observes a first predefined data word or a transmission of a first predefined sequence of predefined data words at its first data interface IF1 during this time Δt, the circuit IC recognizes that the circuit is in the configuration of application I or that the circuit IC as first sensor S1 is in application III or IV. The circuit IC can thus recognize that the circuit is connected with its first data interface IF1 to the upper computer system ECU, BCM. In this case, the circuit IC waits for an instruction of the computer system ECU by means of the second predetermined data word and/or the second predetermined sequence of predetermined data words, which informs the circuit IC which of the applications I to IV is present.
Case 2 b): IF the circuit IC does not observe a first predefined data word or a transmission of a first predefined sequence of predefined data words at its first data interface IF1 and observes a continuous logic 0 during this time Δt, the circuit IC recognizes that it is in application V or VI as a subsequent circuit IC following the first sensor S1 in the private data bus privDB.
Case 2 c): IF the circuit IC does not observe the transmission of the first predefined data word or the first predefined sequence of predefined data words at its first data interface IF1 and a continuous logic 1 is observed during this time Δt, the circuit IC recognizes that the circuit is in application V or VI as the circuit IC of the first sensor S1.
Step 3(for applications I to IV only)
In case 2a, the computer system ECU preferably informs as a third step by means of a second predetermined data word and/or a second predetermined sequence of predetermined data words: there is which of applications I to IV.
In cases 2b and 2c, the circuit IC of the first sensor S1 informs the circuit IC of the following sensor: they are in application V or VI.
Step 4 (for application I only)
In the case of application I, the circuit ICs of all sensors have information that application I is present. Each circuit IC of the overall system then checks the logic level at its second data interface IF2 and at its first GPIO terminal GPIO1 and at its second GPIO terminal GPIO 2. Based on the determined three data bit values, each circuit IC then calculates its individual bus node address according to a predefined algorithm. An exemplary algorithm may be: the bit value at the second data interface IF2 + the bit value at the first GPIO terminal GPIO1 + the bit value at the second GPIO terminal GPIO 2.
Step 5(for application II only)
In the case of application II, the circuit ICs of all sensors have information that application II is present. The first sensor may be addressed from the last sensor or vice versa. The method for assigning bus node addresses described above in connection with application II is performed in this step 5 such that at the end of this step 5 all the circuit ICs of the sensor have valid bus node addresses.
Step 6(for application III only)
In the case of application III, only the first sensor S1 has information that application III is present. Thus, step 6 is used to get the remaining sensors a message: its first data interface should be reconfigured from a configuration according to the first data bus standard to a new configuration according to the protocol of the private data bus privDB.
For this purpose, the circuit IC of the first sensor S1 transmits predetermined data messages in the protocol of the first data bus standard, i.e. for example according to the LIN protocol. The data message preferably comprises information about which of the applications III to IV is present and the circuit IC receiving the data message is such a circuit belonging to the sensor following the first sensor S1.
The circuit IC of the sensor following the first sensor S1 after receiving the predetermined data message configures its first data interface IF1 according to the protocol of the private data bus privDB and determines its bus node address within the private data bus privDB by the GPIO method as described above in connection with application III.
Step 7 (for application IV only)
In the case of application IV, only the first sensor S1 has information that application IV is present. Thus, step 7 is for the remaining sensors to get a message: its first data interface should be reconfigured from a configuration according to the first data bus standard to a new configuration according to the protocol of the private data bus privDB.
For this purpose, the circuit IC of the first sensor S1 transmits predetermined data messages in the protocol of the first data bus standard, i.e. for example according to the LIN protocol. The data message preferably comprises information about which of the applications III to IV is present and the circuit IC receiving the data message is such a circuit belonging to the sensor following the first sensor S1.
The circuit IC of the sensor following the first sensor S1 after receiving the predetermined data message configures its first data interface IF1 according to the protocol of the private data bus privDB and determines its bus node address within the private data bus privDB by means of a daisy chain method as described above in connection with application IV.
Step 8(for applications V and VI only)
In case 2c of step 2, only the first sensor S1 has information that there is an application V or an application VI. Thus, step 8 is used to get the remaining sensors a message: its first data interface should be reconfigured from a configuration according to the first data bus standard to a new configuration according to the protocol of the private data bus privDB.
Step 9
For this purpose, in step 9, the circuit IC of the first sensor S1 transmits a predetermined fourth data message in the protocol of the first data bus standard, i.e. for example according to the LIN protocol. The fourth data message comprises information about the presence of one of the applications V or VI and that the circuit IC receiving the data message is such a circuit belonging to the sensor following the first sensor S1.
Step 10
A first possibility in the form of step 10 is that, already after receiving the predetermined third data message, the circuit IC of the sensor following the first sensor S1 configures its first data interface IF1 according to the protocol of the private data bus privDB.
However, after receiving this predetermined fourth data message, the circuit IC of the sensor following the first sensor S1 initiates an address determination in any case according to the daisy chain method.
Step 11
If the circuit IC of the first sensor S1 is in step 11 at the second time interval Deltat 2 Then no daisy-chain connection exists if no transition from logic 0 to logic 1 is detected at its second GPIO terminal GPIO 2.
Step 12
The circuit IC of the first sensor S1 then signals the circuit IC of the sensor following the first sensor S1 in step 12 by means of a predetermined fifth data message: to application V. The method for dispatching the bus node address described above in connection with application V is then performed.
Step 13
However, if in step 13 the circuit IC of the first sensor S1 is at the second time interval Δt 2 Then a transition from logic 0 to logic 1 is detected at its second GPIO terminal GPIO2, a daisy-chain connection exists.
The circuit IC of the first sensor S1 then signals the circuit IC of the sensor following the first sensor S1 in step 13 by means of a predetermined sixth data message: to application VI. The method for assigning bus node addresses described above in connection with application VI is then performed.
Emergency signalling as long as the first sensor S1 still has signalling possibilities not further stated here, said first sensor issues an error report if, for example, the initialization of the bus system fails. For example, the first sensor may emit a predefined pattern of ultrasonic signals in such error situations.
The circuit IC may also be used here for actuating one or more ultrasonic transducers TR1, TR2,..tr8 and/or one or more ultrasonic transmitters and/or one or more ultrasonic receivers, wherein the circuit is then typically provided for constructing a sensor using the one or more ultrasonic transducers TR1, TR2,..tr8 and/or one or more ultrasonic transmitters and/or one or more ultrasonic receivers in the sense of the present disclosure. The reference numerals TR and numbered variants TR1, TR2, TR8 therefore represent one or more ultrasonic transducers TR, TR1, TR2, TR8 and/or one or more ultrasonic transmitters and/or one or more ultrasonic receivers, according to the terminology used herein. The sensor and/or the circuit IC may have multiple states, but at least two states. The circuit IC typically has means to emit signals and/or error signals via one or more ultrasonic transducers TR1, TR2, TR8 and/or via one or more ultrasonic transmitters and/or to receive instructions via one or more ultrasonic receivers depending on at least two states. Such a circuit IC preferably has means, for example a first data interface IF1, for data transmission of measurement results to the higher-level device ECU, BCM by means of a data connection, for example a LIN bus. If the data connection is faulty and/or interrupted, the circuit IC preferably emits an error notification as a signal and/or an error signal via the one or more ultrasonic transducers TR1, TR2, TR8 and/or via an ultrasonic transmitter or transmitters.
The invention thus relates to a circuit IC for operating an ultrasonic transducer TR1, TR2, TR8 and/or an ultrasonic transmitter and/or an ultrasonic receiver. The ultrasound transducer or ultrasound transmitter or ultrasound receiver is typically provided with, inter alia, a first and a second terminal and a third and a fourth terminal and a first and a second interface IF1 and IF2 and a first and a second GPIO interface GPIO1 and GPIO2. According to the invention, the circuit is defined for being used in a first application I and a second application II and a third application III and a fourth application IV and a fifth application V and a sixth application VI in order to be able to represent the necessary production flexibility. The first interface IF1 is connected to a first terminal of the circuit IC. The first interface IF1 may operate according to a first data bus protocol and/or as a digital input and/or as a low-side driver. The first interface IF1 is operated as a digital input, for example after resetting the circuit IC. The reset may occur, for example, after switching on by a signal or by a software instruction or by a circuit component. The circuit IC is designed and provided for carrying out a method which, at least if necessary, also comprises the following steps in a different sequence, wherein a preferred sequence is described here. It should also be noted that in fig. 10, several steps are combined into a total step with the same reference numerals for a better overview if necessary. Thus, the same reference numerals are given to the sub-steps at different names.
The first step (20) is to reset the circuit IC and thereby draw the input potential of the first interface IF1 to logic 1 in a high impedance manner. The first step (20) further comprises configuring the first interface IF1 according to a first data bus protocol and configuring the second interface IF2 according to the first data bus protocol.
As a second step (21) the circuit IC then waits a first time Δt, which receives the first predetermined data message via the first interface IF1 by overwriting the high impedance 1 at the input of its first interface IF 1.
IF the circuit IC receives a first predetermined data message via its first interface IF1 in step (22) in the first time Δt, the circuit performs the following steps:
for the case (23) that the circuit IC has received a first predetermined data message via its first interface IF1, which data message signals (application I) the first application (application I), step (23) is followed by determining the effective bus node address for the circuit IC by performing an automatic addressing method by means of the GPIO method by the circuit IC.
For the case (24) that the circuit IC has received a first predetermined data message via its first interface IF1, which data message signals the second application (application II), step (24) is followed by determining the effective bus node address for the circuit by performing an automatic addressing method by means of a daisy chain method by the circuit IC in co-operation with the other circuit ICs of the data bus system.
For the case (25) that the circuit IC has received a first predetermined data message via its first interface IF1, wherein said first predetermined data message signals the third application (application III) with signaling as a positioning of the first sensor S1, step (25) is followed by further signaling the application III to the subsequent circuit IC of the subsequent sensor in the data bus chain by means of the second interface IF2 and signaling (25) to the subsequent circuit IC of the subsequent sensor in the data bus chain by means of the second interface IF 2: they have a position as a subsequent sensor S1. Also in this case, IF the second data bus protocol is not identical to the first data bus protocol, the second interface IF2 is configured (25) according to the second data bus protocol.
For the case (26) that the circuit IC has received a first predetermined data message via its first interface IF1, wherein said first predetermined data message signals the fourth application (application IV) with signaling (26) as a location of a subsequent sensor, step (26) is followed by determining the effective bus node address for the circuit IC by performing an automatic addressing method by means of a GPIO method. Furthermore, in this case (26), IF the second data bus protocol is not identical to the first data bus protocol, the first interface IF1 is preferably configured according to said second data bus protocol.
For the case (27) that the circuit IC has received a first predetermined data message via its first interface IF1, wherein the data message signals the fifth application (application V) with signaling (27) as a positioning of the first sensor S1, step (27) is followed by signaling the application IV to the subsequent circuit IC of the subsequent sensor in the data bus chain by means of the second interface IF2 and signaling the subsequent circuit IC of the subsequent sensor in the data bus chain by means of the second interface IF 2: they have a position as a subsequent sensor S1. In this case (27), IF the second data bus protocol is not identical to the first data bus protocol, then the second interface IF2 is preferably also configured according to said second data bus protocol.
For the case (28) that the circuit IC has received a first predetermined data message via its first interface IF1, wherein the data message signals the sixth application (application VI) with the signaling (28) as a localization of the subsequent sensor, step (28) is followed by performing an automatic addressing method by means of a daisy chain method to determine the effective bus node address of the subsequent circuit IC for the subsequent sensor, and IF the second data bus protocol is not identical to the first data bus protocol, the first data interface IF1 is configured (28) according to the second bus protocol IF necessary.
IF (29) no first predetermined data message is received via the first interface IF1 of the circuit IC during this first time interval Δt and the logic level at the input of the first interface IF1 is a logic 1 during this first time Δt, which corresponds to step (8) of fig. 9, however instead of this then follows the execution of signaling (29) in step (29) the subsequent circuit IC of the subsequent sensor in the data bus with the aid of the second interface IF2 of an "application V or VI" and signaling (29) in the data bus chain with the aid of the second interface IF2 of the subsequent circuit IC of the subsequent sensor: they have a position as a subsequent sensor S1. Thus, the circuit ICs of the subsequent sensor begin to attempt to perform (30) automatic addressing via the daisy chain, either present or absent. If a daisy chain does not exist, the method naturally has to fail (31), whereby a distinction can be made between application V and application VI.
If (31) in the range of the automatic addressing method by means of the daisy chain method at a second time interval Deltat 2 The successful execution of the automatic addressing method by means of the daisy chain method, which is not then signalled to the circuit IC, has to be related to the application V. Thus, V is then signaled (31) to the circuit IC of the sensor following this circuit IC. Furthermore, IF the second data bus protocol is not identical to the first data bus protocol, the second interface IF2 is still configured (31) according to the second data bus protocol IF necessary.
If (31) in the range of the automatic addressing method by means of the daisy chain method is at a second time interval Deltat 2 The inward circuit IC signals the successful execution of the automatic addressing method by means of the daisy chain method and has to be related to application VI. Thus, the application VI is then preferably signaled (31) to the circuit IC of the sensor following this circuit IC. Furthermore, IF the second data bus protocol is not identical to the first data bus protocol, the second interface IF2 is still configured (31) according to the second data bus protocol IF necessary.
IF (32) the first predetermined data message is not received via the first interface IF1 of the circuit IC for that first time Δt and the logic level at the input of the first interface IF1 is a logic 0 for the first time Δt, the data bus system has no bus master ECU. In this case, it must be referred to the application V or VI, and the circuit IC is not in the bus position of the first sensor S1. Preferably, but not necessarily, by a first sensorWaiting for a signal to signal "application V or VI". At the latest after signaling "application V or VI" by the first sensor S1, a step is then attempted to be performed (33) by means of an automatic addressing method of the daisy chain method to determine the effective bus node address. If (34) then at a second time interval Deltat 2 After which a signaling of the application V is received by the first sensor S1 via the first interface IF1, an automatic addressing method is performed (34) by means of the GPIO method to determine the effective bus node address. Furthermore, IF the second data bus protocol is not identical to the first data bus protocol, the first interface IF1 is configured (34) according to said second data bus protocol.
The invention thus relates in general to a circuit IC for operating one or more ultrasound transducers TR1, TR2, … TR8 and/or one or more ultrasound transmitters and/or one or more ultrasound receivers, wherein the circuit IC has means, i.e. for example a small computer system with a memory and an internal data bus, to which for example a first data interface IF1 and a second data interface IF2 and a first GPIO interface GPIO1 and a second GPIO interface GPIO2 are connected, in order to be able to execute a method to identify whether it is in one of the applications from the first application set. Here, the first application set comprises at least two applications and/or three applications and/or four applications of application I and application II and application III and application IV. By means of the method, the circuit IC can then also recognize whether the circuit is instead in one of the applications from a second set of applications, wherein the second set of applications comprises at least one application and/or both applications of application V and application VI.
A corresponding method for execution in the circuit IC is characterized in that the method has a step for identifying whether the circuit IC is in one of the applications in a first set of applications, wherein the first set of applications comprises at least two applications and/or three applications and/or four applications in application I and application II and application III and application IV, or whether it is instead in one of the applications from a second set of applications, wherein the second set of applications comprises at least one application and/or two applications in application V and application VI.
Such a circuit and associated method enable the following possibilities to be achieved, at least in some implementations: the circuit ICs with the same sensor PCB are flexibly used in different applications, where the applications are automatically configured. Thereby, the number of different structures and the production streams associated therewith can be reduced, which results in cost savings.
But the advantage is not limited thereto.
The invention has been described above in terms of an example of a circuit for an ultrasound-based working transducer element. However, the invention is also applicable to other types of circuits to which, in particular, measuring transducer elements can be connected.
Individual features and feature groups characterizing different embodiments of the invention are listed next. Where applicable, these individual embodiments may include individual features of respective feature groups, individual features from multiple feature groups, and multiple feature groups.
1. A circuit IC for operating one or more ultrasonic transducers and/or one or more ultrasonic transmitters and/or one or more ultrasonic receivers,
-having a first terminal, and
-having a second terminal, and
-having a third terminal, and
-having a fourth terminal, and
-having a first interface IF1, and
having a second interface IF2, and
-having a first GPIO interface GPIO1, and
having a second GPIO interface GPIO2,
-wherein the circuit is determined to be used in a first application I and a second application II and a third application III and a fourth application IV and a fifth application V and a sixth application VI, and
-wherein said first interface IF1 is connected to said first terminal, and
-wherein said first interface IF1 can be operated according to a first data bus protocol, and
-wherein said first interface IF1 can be operated as a digital input, and
-wherein said first interface IF1 can be operated as a low-side driver, and
-wherein said first interface IF1 is operated as a digital input after reset, and
-wherein the circuit IC is set up and arranged for performing a method comprising the steps of:
-resetting the circuit IC, and
-pulling the input of said first interface IF1 to logic 1 in a high impedance manner, and
-driving the output of the second interface IF2 to logic 0 in a low impedance manner, and
-configuring said first interface IF1 according to said first data bus protocol;
-configuring the second interface IF2 according to the first data bus protocol;
-waiting for a first time Δt: receiving a first predetermined data message via said first interface IF1 by overwriting a high impedance 0 at an input of said first interface IF1;
-IF said first predetermined data message is received via said first interface IF1 in a first time Δt, performing the steps of:
-signaling a first application I for said first predetermined data message:
-performing an automatic addressing method by means of a GPIO method to determine an effective bus node address for the circuit;
-signaling the second application II for the first predetermined data message:
-performing an automatic addressing method by means of a daisy chain method to determine an effective bus node address for the circuit;
-signaling a third application III with signaling as a positioning of the first sensor S1 for said first predetermined data message:
signaling application III to a subsequent circuit IC of a subsequent sensor in the data bus chain by means of said second interface IF2, and
-signaling a subsequent circuit IC of a subsequent sensor in the data bus chain by means of said second interface IF 2: they have a position as a subsequent sensor S1;
-IF the second data bus protocol is not identical to the first data bus protocol, configuring the second interface IF2 according to the second data bus protocol;
-signaling a third application III with signaling of the location as a subsequent sensor for said first predetermined data message:
-performing an automatic addressing method by means of a GPIO method to determine an effective bus node address for a subsequent circuit IC of the subsequent sensor;
-IF a second data bus protocol is not identical to the first data bus protocol, configuring the first interface IF1 according to the second data bus protocol;
-signaling the fourth application IV with signaling as the positioning of the first sensor S1 for said first predetermined data message:
-signaling an application IV to a subsequent circuit IC of a subsequent sensor in the data bus chain by means of said second interface IF2, and
-signaling a subsequent circuit IC of a subsequent sensor in the data bus chain by means of said second interface IF 2: with a positioning as a subsequent sensor S1;
-IF a second data bus protocol is not identical to the first data bus protocol, configuring the second interface IF2 according to the second data bus protocol;
-signaling a fourth application IV with signaling of a location as a subsequent sensor for said first predetermined data message:
-performing an automatic addressing method by means of a daisy chain method to determine an effective bus node address of a subsequent circuit IC for a subsequent sensor;
-IF a second data bus protocol is not identical to the first data bus protocol, configuring the first interface IF1 according to the second data bus protocol;
-IF no first predetermined data message is received via said first interface IF1 in the first time interval Δt and the logic level at the input of said first interface IF1 is a logic 1 in the first time Δt, performing the steps of:
Signaling "application V or VI" to a subsequent circuit IC of a subsequent sensor in the data bus chain by means of said second interface IF2, and
-signaling a subsequent circuit IC of a subsequent sensor in the data bus chain by means of said second interface IF 2: they have a position as a subsequent sensor S1;
-if in the range of the automatic addressing method by means of the daisy chain method at a second time interval Δt 2 After that, no successful execution of the automatic addressing method by means of the daisy chain method is signalled to the circuit IC, the circuit IC of the subsequent sensor is signalled "application V";
-IF a second data bus protocol is not identical to the first data bus protocol, configuring the second interface IF2 according to the second data bus protocol.
-IF no first predetermined data message is received via said first interface IF1 in the first time interval Δt and the logic level at the input of said first interface IF1 is a logic 0 in the first time Δt, performing the steps of:
-determining an effective bus node address by means of a daisy chain method performing an automatic addressing method;
-if at a second time interval Δt 2 Then receiving a signaling of an application V via said first interface IF1, then performing an automatic addressing method by means of a GPIO method to determine an effective bus node address;
-IF the second data bus protocol is not identical to the first data bus protocol, configuring the first interface IF1 according to the second data bus protocol.
2. A method for configuring an ultrasonic sensor for use in a circuit IC, the circuit IC
-having a first terminal, and
-having a second terminal, and
-having a third terminal, and
-having a fourth terminal, and
-having a first interface IF1, and
having a second interface IF2, and
-having a first GPIO interface GPIO1, and
having a second GPIO interface GPIO2,
-wherein the circuit is part of the ultrasonic sensor, and
-wherein the circuit is determined to be used in a first application I and a second application II and a third application III and a fourth application IV and a fifth application V and a sixth application VI, and
-wherein said first interface IF1 is connected to said first terminal, and
-wherein said first interface IF1 can be operated according to a first data bus protocol, and
-wherein said first interface IF1 can be operated as a digital input, and
-wherein said first interface IF1 can be operated as a low-side driver, and
-wherein said first interface IF1 is operated as a digital input after reset, and
the method comprises the following steps:
-resetting the circuit IC, and
-pulling the input of said first interface IF1 to logic 1 in a high impedance manner, and
-driving the output of the second interface IF2 to logic 0 in a low impedance manner, and
-configuring said first interface IF1 according to said first data bus protocol;
-configuring the second interface IF2 according to the first data bus protocol;
-waiting for a first time Δt: receiving a first predetermined data message via said first interface IF1 by overwriting a high impedance 1 at an input of said first interface IF1;
-IF said first predetermined data message is received via said first interface IF1 in a first time Δt, performing the steps of:
-signaling a first application I for said first predetermined data message:
-performing an automatic addressing method by means of a GPIO method to determine an effective bus node address for the circuit;
-signaling the second application II for the first predetermined data message:
-performing an automatic addressing method by means of a daisy chain method to determine an effective bus node address for the circuit;
-signaling a third application III with signaling as a positioning of the first sensor S1 for said first predetermined data message:
signaling application III to a subsequent circuit IC of a subsequent sensor in the data bus chain by means of said second interface IF2, and
-signaling a subsequent circuit IC of a subsequent sensor in the data bus chain by means of said second interface IF 2: they have a position as a subsequent sensor S1;
-IF the second data bus protocol is not identical to the first data bus protocol, configuring the second interface IF2 according to the second data bus protocol;
-signaling a third application III with signaling of the location as a subsequent sensor for said first predetermined data message:
-performing an automatic addressing method by means of a GPIO method to determine an effective bus node address for a subsequent circuit IC of the subsequent sensor;
-IF a second data bus protocol is not identical to the first data bus protocol, configuring the first interface IF1 according to the second data bus protocol;
-signaling the fourth application IV with signaling as the positioning of the first sensor S1 for said first predetermined data message:
-signaling an application IV to a subsequent circuit IC of a subsequent sensor in the data bus chain by means of said second interface IF2, and
-signaling a subsequent circuit IC of a subsequent sensor in the data bus chain by means of said second interface IF 2: they have a position as a subsequent sensor S1;
-IF a second data bus protocol is not identical to the first data bus protocol, configuring the second interface IF2 according to the second data bus protocol;
-signaling a fourth application IV with signaling of a location as a subsequent sensor for said first predetermined data message:
-performing an automatic addressing method by means of a daisy chain method to determine an effective bus node address of a subsequent circuit IC for a subsequent sensor;
-IF a second data bus protocol is not identical to the first data bus protocol, configuring the first interface IF1 according to the second data bus protocol;
-IF no first predetermined data message is received via said first interface IF1 in the first time interval Δt and the logic level at the input of said first interface IF1 is a logic 1 in the first time Δt, performing the steps of:
Signaling "application V or VI" to a subsequent circuit IC of a subsequent sensor in the data bus chain by means of said second interface IF2, and
-signaling a subsequent circuit IC of a subsequent sensor in the data bus chain by means of said second interface IF 2: they have a position as a subsequent sensor S1;
-if in the range of the automatic addressing method by means of the daisy chain method at a second time interval Δt 2 After that, no successful execution of the automatic addressing method by means of the daisy chain method is signalled to the circuit IC, the application V is signalled to the circuit IC of the subsequent sensor;
-IF a second data bus protocol is not identical to the first data bus protocol, configuring the second interface IF2 according to the second data bus protocol.
-IF no first predetermined data message is received via said first interface IF1 in the first time interval Δt and the logic level at the input of said first interface IF1 is a logic 0 in the first time Δt, performing the steps of:
-determining an effective bus node address by means of a daisy chain method performing an automatic addressing method;
-if at a second time interval Δt 2 Then receiving a signaling of an application V via said first interface IF1, then performing an automatic addressing method by means of a GPIO method to determine an effective bus node address;
-IF the second data bus protocol is not identical to the first data bus protocol, configuring the first interface IF1 according to the second data bus protocol.
3. A circuit IC for operating one or more ultrasonic transducers and/or one or more ultrasonic transmitters and/or one or more ultrasonic receivers,
-wherein the circuit IC has means for enabling execution of a method for identifying
Whether it is in one of the applications from the first set of applications,
wherein the first set of applications comprises at least two applications and/or three applications and/or four applications of application I and application II and application III and application IV,
or if it is instead in one of the applications from the second set of applications,
wherein the second set of applications comprises at least one application and/or two applications of application V and application IV,
4. a method performed in a circuit IC for operating one or more ultrasound transducers and/or one or more ultrasound transmitters and/or one or more ultrasound receivers,
-wherein the method comprises the steps of identifying
Whether it is in one of the applications from the first set of applications,
Wherein the first set of applications comprises at least two applications and/or three applications and/or four applications of application I and application II and application III and application IV,
or if it is instead in one of the applications from the second set of applications,
wherein the second set of applications comprises at least one application and/or two applications of application V and application IV,
5. a circuit IC for operating one or more ultrasonic transducers and/or one or more ultrasonic transmitters and/or one or more ultrasonic receivers,
wherein the circuit is arranged for constituting a sensor in the sense of the present embodiment with one or more ultrasonic transducers and/or one or more ultrasonic transmitters and/or one or more ultrasonic receivers, and
-wherein the sensor and/or the circuit IC may have a plurality of, but at least two, states, and
-wherein the circuit IC is provided with means for transmitting signals and/or error signals via one or more ultrasonic transducers and/or via one or more ultrasonic transmitters and/or receiving instructions via an ultrasonic receiver or receivers in dependence on at least two states.
6. According to the circuit of point 5,
wherein the circuit has means for data transmission of measurement results to the higher-level device ECU by means of a data connection, and
-if the data connection is erroneous and/or interrupted, the circuit IC emits an error notification and/or error signal as a signal via one or more ultrasonic transducers.
7. A method for operating a circuit IC of one or more ultrasonic transducers and/or one or more ultrasonic transmitters and/or one or more ultrasonic receivers,
wherein the circuit is arranged for constituting a sensor in the sense of the present embodiment with one or more ultrasonic transducers and/or one or more ultrasonic transmitters and/or one or more ultrasonic receivers, and
-wherein the sensor and/or the circuit IC may have a plurality of, but at least two, states, and
-wherein the method comprises the steps of:
-transmitting a signal or signals and/or an error signal or error signals via one or more ultrasonic transducers of the sensor and/or via one or more ultrasonic transmitters of the sensor, wherein the transmission is made in accordance with the at least two states, and/or
-receiving an instruction or instructions via an ultrasonic receiver or ultrasonic receivers of the sensor.
8. The method of point 7, wherein the transmitted signal is an error notification and/or error signal.
9. The method of point 8, wherein an error signal is transmitted if a predetermined data connection between the sensor and the superior device is faulty and/or interrupted.
List of reference numerals
Δt,Δt 2 Time interval
GPIO1 first I/O interface
GPIO2 second I/O interface
IF1 first data bus interface
IF2 second data bus interface
S1 to S8 sensor
WEA1 measuring transducer element terminal
WEA2 measuring transducer element terminal
BUZ display unit
Microcomputer with a microcomputer
ECU bus master
GND reference potential terminal
IC circuit
LIN first data bus line
VCC power supply potential terminal
d data bus interface
privDB second data bus line
TR measuring transducer element
TR1 to TR8 ultrasonic transducer Su energy supply device
Rx receiver
Tx transmitter
List of cited documents
DE-A-10 2017 118 565
DE-A-10 2014 115 000
DE-U-20 2018 006 079
US-A-2006/0273927
US-A-2017/0083468
US-A-2019/0041504

Claims (11)

1. A circuit for connecting an ultrasonic measurement transducer element that transmits ultrasonic signals and/or receives ultrasonic signals to a communication data bus, wherein the circuit comprises:
At least one converter element terminal (WEA 1, WEA 2),
a reference potential terminal (GND),
a supply potential terminal (VCC),
a first data bus interface (IF 1),
a second data bus interface (IF 2),
-a first I/O interface (GPIO 1) which can be operated by programming as an input or output or by programming in binary fashion using pin-coded potentials, and
a second I/O interface (GPIO 2) which can be operated by programming as an input or output or by programming in a binary manner with pin-coded potentials,
a microcomputer for processing data and/or signals which can be received or transmitted via two data bus interfaces (IF 1, IF 2) and two I/O interfaces (GPIO 1, GPIO 2) and at least one converter element terminal,
wherein the first data bus interface (IF 1) can be operated according to a first data bus protocol or according to a second data bus protocol different from the first data bus protocol, either as input or as driver for operating an optical and/or graphic and/or acoustic display unit (BUZ),
wherein the second data bus interface (IF 2) is capable of being operated according to the first data bus protocol or according to a second data bus protocol different from the first data bus protocol or as input or as driver for operating an optical and/or graphic and/or acoustic display unit (BUZ),
Wherein the first data bus interface (IF 1) is connectable to a first data bus line, the first data bus line having a bus master and a first data bus interface (IF 1) of the other circuit being connectable to the first data bus line,
wherein when the first data bus interface (IF 1) is connected to a first data bus line, the second data bus interface (IF 2) is connectable to a second, different data bus line than the first data bus line, a first or a second data bus interface (IF 1, IF 2) of the other circuit is connectable to the second data bus line,
wherein the second I/O interface (GPIO 2) of the circuit can be connected in series with the first I/O interface (GPIO 1) of one other circuit and by means of this series connection the one other circuit or the one other circuit and a plurality of other circuits connected in series with each other can be addressed,
-wherein one or both of the two I/O interfaces (GPIO 1, GPIO 2) is/are connected in operation as input to a reference potential for addressing the circuit by terminal coding, and
-wherein one of the two data bus interfaces (IF 1, IF 2) is connectable to a display unit (BUZ) for operating the display unit (BUZ), and the other of the two data bus interfaces is connectable to the second data bus, to which the first data bus interface (IF 1) of the other circuit or the second data bus interface (IF 2) of the other circuit is connectable.
2. A circuit according to claim 1, wherein one of the two I/O interfaces (GPIO 1, GPIO 2) or one of the two I/O interfaces (GPIO 1, GPIO 2) and one of the two data bus interfaces (IF 1, IF 2) is connected in operation as an input thereof with a reference potential for addressing the circuit by terminal coding.
3. A data bus system has
A plurality of circuits (ICs) according to claim 1,
-a bus master (ECU), and
a data bus line to which the bus master (ECU) and the plurality of circuits (ICs) are connected,
wherein for the purpose of data communication with the bus master and/or with each other the plurality of circuits (ICs) are connected to the data bus lines either with their respective first data bus interface (IF 1) or with their respective second data bus interface (IF 2),
-wherein the two I/O interfaces (GPIO 1, GPIO 2) of the first circuit (IC) according to claim 1 and the data bus interface (IF 1, IF 2) not used for data communication are not connected to said data bus line, and
-wherein all other two I/O interfaces (GPIO 1, GPIO 2) of the circuit (IC) according to claim 1 or all other data bus interfaces (IF 1, IF 2) of the circuit (IC) according to claim 1 not used for data communication are connected in respectively different combinations with reference potentials for addressing by pin coding.
4. A data bus system has
A plurality of circuits (ICs) according to claim 1,
-a bus master (ECU), and
a data bus line to which the bus master (ECU) and the plurality of circuits (ICs) are connected,
wherein for the purpose of data communication with the bus master and/or with each other the plurality of circuits (ICs) are connected to the data bus lines either with their respective first data bus interface (IF 1) or with their respective second data bus interface (IF 2),
wherein the data bus interfaces (IF 1, IF 2) of all circuits (ICs) which are not required for said data communication are not connected,
-wherein a first I/O interface (GPIO 1) of a first circuit (IC) according to claim 1 and a second I/O interface (GPIO 2) of a second circuit (IC) according to claim 1 are not connected to the data bus line, and
-wherein the further circuits (ICs) according to claim 1 are connected in series with the first circuit (IC) and the second circuit (IC) for automatically addressing at least these further circuits (ICs) such that the second I/O interface (GPIO 2) of the first circuit (IC) and each further circuit (IC) is connected with the first I/O interface (GPIO 1) of one of the further circuits (ICs) or the next further circuit (IC) and the second I/O interface (GPIO 2) of the last further circuit (IC) is connected with the first I/O interface (GPIO 1) of the second circuit (IC).
5. Data bus system according to claim 4, wherein further circuits (ICs) according to claim 1 are connected in series with the first circuit (IC) and the second circuit (IC) for automatically addressing at least these further circuits (ICs) and also the second circuit (IC) and/or also the first circuit (IC), such that the second I/O interface (GPIO 2) of the first circuit (IC) and each further circuit (IC) is connected with the first I/O interface (GPIO 1) of one or the next further circuit (IC) and the second I/O interface (GPIO 2) of the last further circuit (IC) is connected with the first I/O interface (GPIO 1) of the second circuit (IC).
6. A data bus system has
A plurality of circuits (ICs) according to claim 1,
a bus master (ECU),
-a first data bus line
A second data bus line which is connected to the first data bus line,
-wherein for data communication purposes a first data bus interface (IF 1) of said bus master (ECU) and at least one first circuit (IC) according to claim 1 is connected to said first data bus line,
-wherein a second data bus interface (IF 2) of at least one of the first circuits (IC) and a first data bus interface (IF 1) or a second data bus interface (IF 2) of the other circuits (IC) according to claim 1 are connected to said second data bus line,
-wherein a data bus interface (IF 1, IF 2) of each other circuit (IC) not used for data communication is not connected to either of said first and second data bus lines, and
-wherein all other two I/O interfaces (GPIO 1, GPIO 2) of the circuit (IC) according to claim 1 or all other two I/O interfaces (GPIO 1, GPIO 2) of the circuit (IC) according to claim 1 and a data bus interface (IF 1, IF 2) not used for data communication) are connected in respectively different combinations with reference potentials for addressing by pin coding.
7. A data bus system has
A plurality of circuits (ICs) according to claim 1,
a bus master (ECU),
-a first data bus line
A second data bus line which is connected to the first data bus line,
-wherein for data communication purposes a first data bus interface (IF 1) of said bus master (ECU) and at least one first circuit (IC) according to claim 1 is connected to said first data bus line,
-wherein a second data bus interface (IF 2) of at least one of the first circuits (IC) and a first data bus interface (IF 1) or a second data bus interface (IF 2) of the other circuits (IC) according to claim 1 are connected to said second data bus line,
-wherein a first I/O interface (GPIO 1) of a first other circuit (IC) according to claim 1 and a second I/O interface (GPIO 2) of a second other circuit (IC) according to claim 1 are not connected to the second data bus line, and
-wherein the further circuit (IC) according to claim 1 is connected in series with the first further circuit (IC) and the second further circuit (IC) for automatically addressing at least these further circuits (ICs), such that the first further circuit (IC) and the second I/O interface (GPIO 2) of each further circuit (IC) are connected with the first I/O interface (GPIO 1) of one of the further circuits (ICs) or of the next further circuit (IC), and the second I/O interface (GPIO 2) of the last further circuit (IC) is connected with the first I/O interface (GPIO 1) of the second further circuit (IC).
8. Data bus system according to claim 7, wherein a further circuit (IC) according to claim 1 is connected in series with the first further circuit (IC) and the second further circuit (IC) for automatically addressing at least these further circuits (ICs) and also the first further circuit (IC) and/or also the second further circuit (IC), such that the second I/O interface (GPIO 2) of the first further circuit (IC) and each further circuit (IC) is connected with the first I/O interface (GPIO 1) of one of the further circuits (ICs) or of the next further circuit (IC) and the second I/O interface (GPIO 2) of the last further circuit (IC) is connected with the first I/O interface (GPIO 1) of the second further circuit (IC).
9. A data bus system has
A plurality of circuits (ICs) according to claim 1,
-a display unit (BUZ) and
a data bus line which is connected to the data bus line,
-wherein a first data bus interface (IF 1) of the first circuit (IC) according to claim 1 is connected with a display unit (BUZ) for operating said display unit (BUZ),
wherein a second data bus interface (IF 2) of the first circuit (IC) is connected to said data bus line,
-wherein a first data bus interface (IF 1) or a second data bus interface (IF 2) of a further circuit (IC) according to claim 1 is connected to said data bus line,
-wherein the two I/O interfaces (GPIO 1, GPIO 2) of the other circuit (IC) according to claim 1 and the data bus interface (IF 1, IF 2) not used for data communication are not connected to said data bus line and
-wherein all further two I/O interfaces (GPIO 1, GPIO 2) of the circuit (IC) according to claim 1 or all further two I/O interfaces (GPIO 1, GPIO 2) of the circuit (IC) according to claim 1 and the data bus interface (IF 1, IF 2) not used for data communication are connected in respectively different combinations with reference potentials for addressing by pin coding.
10. A data bus system has
A plurality of circuits (ICs) according to claim 1,
-a display unit (BUZ) and
a data bus line which is connected to the data bus line,
-wherein a first data bus interface (IF 1) of the first circuit (IC) according to claim 1 is connected with a display unit (BUZ) for operating said display unit (BUZ),
wherein a second data bus interface (IF 2) of the first circuit (IC) is connected to said data bus line,
-wherein a first data bus interface (IF 1) or a second data bus interface (IF 2) of a further circuit (IC) according to claim 1 is connected to said data bus line,
-wherein a first I/O interface (GPIO 1) of a first other circuit (IC) according to claim 1 and a second I/O interface (GPIO 2) of a second other circuit (IC) according to claim 1 are not connected to the data bus line and
-wherein the further circuit (IC) according to claim 1 is connected in series with the first further circuit (IC) and the second further circuit (IC) for automatically addressing at least these further circuits (ICs), such that the first further circuit (IC) and the second I/O interface (GPIO 2) of each further circuit (IC) are connected with the first I/O interface (GPIO 1) of one of the further circuits (ICs) or of the next further circuit (IC), and the second I/O interface (GPIO 2) of the last further circuit (IC) is connected with the first I/O interface (GPIO 1) of the second further circuit (IC).
11. Data bus system according to claim 10, wherein a further circuit (IC) according to claim 1 is connected in series with the first further circuit (IC) and the second further circuit (IC) for automatically addressing at least these further circuits (ICs) and also the first further circuit (IC) and/or also the second further circuit (IC), such that the second I/O interface (GPIO 2) of the first further circuit (IC) and each further circuit (IC) is connected with the first I/O interface (GPIO 1) of one of the further circuits (ICs) or of the next further circuit (IC) and the second I/O interface (GPIO 2) of the last further circuit (IC) is connected with the first I/O interface (GPIO 1) of the second further circuit (IC).
CN202080027422.1A 2019-02-08 2020-02-07 Circuit for connecting a measuring transducer Active CN113661688B (en)

Applications Claiming Priority (9)

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DE102019103221 2019-02-08
DE102019103223.7A DE102019103223B4 (en) 2019-02-08 2019-02-08 Device and method for signaling a data bus failure by an ultrasonic measuring device
DE102019103223.7 2019-02-08
DE102019103221.0 2019-02-08
DE102019103222.9A DE102019103222B3 (en) 2019-02-08 2019-02-08 Device for auto-configuration of automotive ultrasonic sensors on different data buses in different applications and corresponding method
DE102019103222.9 2019-02-08
DE102020100425.7A DE102020100425B3 (en) 2019-02-08 2020-01-10 Device for auto-configuration of automotive ultrasonic sensors on various data buses and corresponding method
DE102020100425.7 2020-01-10
PCT/EP2020/053090 WO2020161282A1 (en) 2019-02-08 2020-02-07 Circuit for the connection of a transducer

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