EP3918799A1 - Signalisation explicite de rétention prolongée d'image de référence à long terme - Google Patents

Signalisation explicite de rétention prolongée d'image de référence à long terme

Info

Publication number
EP3918799A1
EP3918799A1 EP20748672.1A EP20748672A EP3918799A1 EP 3918799 A1 EP3918799 A1 EP 3918799A1 EP 20748672 A EP20748672 A EP 20748672A EP 3918799 A1 EP3918799 A1 EP 3918799A1
Authority
EP
European Patent Office
Prior art keywords
long term
decoder
term reference
reference frame
bitstream
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP20748672.1A
Other languages
German (de)
English (en)
Other versions
EP3918799A4 (fr
Inventor
Borivoje Furht
Hari Kalva
Velibor Adzic
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
OP Solutions LLC
Original Assignee
OP Solutions LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by OP Solutions LLC filed Critical OP Solutions LLC
Publication of EP3918799A1 publication Critical patent/EP3918799A1/fr
Publication of EP3918799A4 publication Critical patent/EP3918799A4/fr
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/103—Selection of coding mode or of prediction mode
    • H04N19/105—Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/103—Selection of coding mode or of prediction mode
    • H04N19/109—Selection of coding mode or of prediction mode among a plurality of temporal predictive coding modes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/124—Quantisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/157—Assigned coding mode, i.e. the coding mode being predefined or preselected to be further used for selection of another element or parameter
    • H04N19/159—Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/58—Motion compensation with long-term prediction, i.e. the reference frame for a current frame not being the temporally closest one
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/593—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/85—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
    • H04N19/86—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving reduction of coding artifacts, e.g. of blockiness
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/96—Tree coding, e.g. quad-tree coding

Definitions

  • the present invention generally relates to the field of video compression.
  • the present invention is directed to explicit signaling of extended long term reference picture retention.
  • a video codec can include an electronic circuit or software that compresses or decompresses digital video. It can convert uncompressed video to a compressed format or vice versa.
  • a device that compresses video (and/or performs some function thereof) can typically be called an encoder, and a device that decompresses video (and/or performs some function thereof) can be called a decoder.
  • a format of the compressed data can conform to a standard video compression specification.
  • the compression can be lossy in that the compressed video lacks some information present in the original video. A consequence of this can include that decompressed video can have lower quality than the original uncompressed video because there is insufficient information to accurately reconstruct the original video.
  • Motion compensation can include an approach to predict a video frame or a portion thereof given a reference frame, such as previous and/or future frames, by accounting for motion of the camera and/or objects in the video. It can be employed in the encoding and decoding of video data for video compression, for example in the encoding and decoding using the Motion Picture Experts Group (MPEG)-2 (also referred to as advanced video coding (AVC) and H.264) standard. Motion compensation can describe a picture in terms of the transformation of a reference picture to the current picture. The reference picture can be previous in time when compared to the current picture, from the future when compared to the current picture, or can include a long term reference (LTR) frame. When images can be accurately synthesized from previously transmitted and/or stored images, compression efficiency can be improved.
  • MPEG Motion Picture Experts Group
  • AVC advanced video coding
  • H.264 H.264
  • LTR frames Long term reference (LTR) frames have been used in video coding standards such as MPEG-2, H.264 (also referred to as AVC or MPEG-4 Part 10), and H.265 (also referred to as High Efficiency Video Coding (HEVC)).
  • a frame marked as an LTR frame in the video bitstream is available for use as a reference until it is explicitly removed by bitstream signaling. LTR frames improve prediction and compression efficiency in scenes that have static
  • a decoder includes circuitry configured to receive a bitstream, store a plurality of long term reference frames in a reference list, retain a long term reference frame in the reference list for a length of time based on a retention time, and decode at least a portion of video using the long term reference frame retained in the reference list.
  • a method includes receiving, by a decoder, a bitstream. The method includes storing, by the decoder, a plurality of long term reference frames in a reference list. The method includes retaining, by the decoder, a long term reference frame in the reference list for a length of time based on a retention time. The method includes decoding, by the decoder, at least a portion of video using the long term reference frame retained in the reference list.
  • FIG. 1 illustrates an example reference list for frame prediction over a long period
  • FIG. 2 is a process flow diagram illustrating an example process of extended long term reference (eLTR) frame retention in which an eLTR frame is retained in the reference list;
  • eLTR extended long term reference
  • FIG. 3 is a system block diagram illustrating an example decoder capable of decoding a bitstream with eLTR frames retained in the reference list;
  • FIG. 4 is a process flow diagram illustrating an example process of encoding a video with eLTR frames retained in the reference list according to some aspects of the current subject matter that can enable compression efficiency improvements compared to some existing approaches;
  • FIG. 5 is a system block diagram illustrating an example video encoder capable of signaling for eLTR retention in the reference list.
  • FIG. 6 is a block diagram of a computing system that can be used to implement any one or more of the methodologies disclosed herein and any one or more portions thereof.
  • LTR long-term reference picture
  • a long-term reference picture may be used for better prediction of video frames in the cases where certain portions of the frame become occluded then uncovered repeatedly over time.
  • LTR is used over a duration of a scene or group-of-pictures, after which it is replaced or discarded.
  • explicitly signaled extended long-term reference (eLTR) frames may be retained in a reference list for explicitly signaled lengths of time.
  • Some implementations of the current subject matter may provide significant compression efficiency gains compared to some existing approaches.
  • An eLTR may be retained in a picture reference list, which may be used by a current frame or group of frames for prediction. While all other frames in the list change over relatively short period, the eLTR can be retained in the reference list.
  • FIG. 1 illustrates an example reference list for frame prediction over a long period.
  • video frames shown as shaded may be reconstructed using reference frames.
  • Reference list may contain frames that change over time and an eLTR that is retained.
  • an encoder conducts operation of eLTR selection and retention calculation.
  • Selected frames and a time of retention may be signaled to decoder, for example, using pairs (eLTRn, TRn) indicating an index for the eLTR (eLTRn) and a retention time (TRn) for frame n.
  • TRn retention time
  • a decoder may retain frame eLTRn for a period of TRn in reference list. After eLTRn frame has resided in reference list for at least TRn, the eLTRn frame may be marked as unavailable for further use. In some implementations, eLTRn frame may be maintained in memory but in an unavailable state.
  • encoder may explicitly signal a decoder to mark the eLTRn frame as available or as unavailable. For example, eLTRn frame previously marked as unavailable after passage of retention time TRn may be marked as available. Such feature may enable eLTRn to be used again in the future, such as for video containing scenes that switch back and forth.
  • an encoder may include a signal in a bitstream for a decoder to remove eLTRn frame from memory.
  • Decoder may remove eLTRn frame from reference list and memory based on such signal.
  • FIG. 2 is a process flow diagram illustrating a non-limiting example of a process 200 of eLTR frame retention in which an eLTR frame is retained in a reference list. Such eLTR retention may enable compression efficiency improvements compared to some existing approaches to video encoding and decoding.
  • Bitstream may include, for example, data found in a stream of bits that is an input to a decoder when using data compression.
  • Bitstream may include information necessary to decode a video.
  • Receiving may include extracting and/or parsing a block and associated signaling information from bitstream.
  • receiving bitstream may include parsing eLTR frames, indices to such frames (eLTRn), and associated retention times (TRn), where retention time is based on frames decoded and/or time within the video.
  • an eLTR frame may be stored in the reference picture list.
  • stored eLTR frame may be retained (e.g., maintained) in a reference list for a length of time based on an associated retention time (TRn).
  • TRn retention time
  • Decoding may include decoding a current block.
  • a received current coded block contained in bitstream may be decoded, for example, by using inter prediction.
  • Decoding via inter prediction may include using a previous frame, a future frame, and/or eLTR frame as a reference for computing a prediction, which can be combined with a residual contained in bitstream.
  • an eLTR frame may be utilized as a reference frame for inter prediction.
  • a second coded block may be received. Whether an inter prediction mode is enabled for second coded block may be determined;
  • a second decoded block may be determined using eLTR frame as a reference frame and according to inter prediction mode.
  • the decoding via inter prediction may include using eLTR frame as a reference for computing a prediction, which can be combined with a residual contained in bitstream.
  • FIG. 3 is a system block diagram illustrating a non-limiting example of a decoder 300 capable of decoding a bitstream 370 with eLTR frames retained in a reference list.
  • Decoder 300 may include an entropy decoder processor 310, an inverse quantization and inverse transformation processor 320, a deblocking filter 330, a frame buffer 340, motion compensation processor 350 and intra prediction processor 360.
  • bitstream 370 may include parameters (e.g., fields in a header of the bitstream) that signal eLTR indices (eLTRn) and retention times (TRn).
  • Motion compensation processor 350 may reconstruct pixel information using eLTR frames and retain the eLTR frames according to their associated retention times (TRn).
  • an eLTR frame (eLTRn) is received and retained in the reference list for at least an associated retention time
  • an eLTR frame eLTRn
  • eLTRn may be used as a reference for inter prediction mode, at least during the associated reference time.
  • bitstream 370 may be received by decoder 300 and input to entropy decoder processor 310, which may entropy decode the bitstream into quantized coefficients.
  • Quantized coefficients may be provided to inverse quantization and inverse transformation processor 320, which may perform inverse quantization and inverse transformation to create a residual signal, which may be added to an output of motion compensation processor 350 or intra prediction processor 360 according to a processing mode.
  • An output of motion compensation processor 350 and intra prediction processor 360 may include a block prediction based on a previously decoded block and/or eLTR frames maintained in reference list. Sum of prediction and residual may be processed by deblocking filter 630 and stored in a frame buffer 640.
  • FIG. 4 is a process flow diagram illustrating a non-limiting example of a process 400 of encoding a video with eLTR frames retained in the reference list according to some aspects of current subject matter that may enable compression efficiency improvements compared to some existing approaches.
  • a sequence of video frames may be encoded including determining one or more eLTR frames.
  • eLTR frame retention times TRn may be determined, for example, based on a length of time that an eLTR frame is utilized by
  • encoder/decoder where, for example, time is based on frames being decoded in a video.
  • additional signaling parameters may be determined. For example, whether and when to mark eLTR frames as unavailable or available may be determined, and whether and when each eLTR frame should be removed from memory may be determined.
  • eLTR retention time and additional signaling parameters may be included in a bitstream.
  • FIG. 5 is a system block diagram illustrating a non-limiting example of a video encoder 500 capable of signaling for eLTR retention in a reference list.
  • Example video encoder 500 receives an input video 505, which may be initially segmented or dividing according to a processing scheme, such as a tree-structured macro block partitioning scheme (e.g., quad-tree plus binary tree).
  • a tree-structured macro block partitioning scheme may include a partitioning scheme partitioning a picture frame into large block elements which may be referred to for purposes of this disclosure as coding tree units (CTU).
  • CTU coding tree units
  • each CTU may be further partitioned one or more times into a number of sub-blocks called coding units (CU).
  • a result of this portioning may include a group of sub-blocks that may be referred to for the purposes of this disclosure as predictive units (PU).
  • Transform units (TU) may also be utilized.
  • example video encoder 500 may include an intra prediction processor 515, a motion estimation / compensation processor 520 (also referred to as an inter prediction processor) capable of supporting eLTR frame retention, a transform /quantization processor 525, an inverse quantization / inverse transform processor 530, an in-loop filter 535, a decoded picture buffer 540, and an entropy coding processor 545.
  • motion estimation / compensation processor 520 may determine eLTR retention times and additional signaling parameters. Bitstream parameters that signal eLTR frame retention and additional parameters may be input to the entropy coding processor 545 for inclusion in output bitstream 550.
  • a block may be provided to intra prediction processor 510 or motion estimation / compensation processor 520. If block is to be processed via intra prediction, intra prediction processor 510 may perform processing to output a predictor. If block is to be processed via motion estimation / compensation, motion estimation / compensation processor 520 may perform processing including using eLTR frames as a reference for inter prediction, if applicable.
  • a residual may be formed by subtracting predictor from input video. Residual may be received by transform / quantization processor 525, which may perform transformation processing (e.g., discrete cosine transform (DCT)) to produce
  • transformation processing e.g., discrete cosine transform (DCT)
  • Quantized coefficients which may be quantized. Quantized coefficients and any associated signaling information may be provided to entropy coding processor 545 for entropy encoding and inclusion in an output bitstream 550. Entropy encoding processor 545 may support encoding of signaling information related to eLTR frame retention. In addition, quantized coefficients may be provided to inverse quantization / inverse transformation processor 530, which may reproduce pixels, which may be combined with predictor and processed by in loop filter 535, an output of which may be stored in a decoded picture buffer 540 for use by a motion estimation /
  • compensation processor 520 that is capable of supporting eLTR frame retention.
  • current blocks may include any symmetric blocks (8x8, 16x16, 32x32, 64x64, 128 x 128, and the like) as well as any asymmetric block (8x4, 16x8, and the like).
  • a quadtree plus binary decision tree may be implemented.
  • QTBT quadtree plus binary decision tree
  • partition parameters of QTBT may be dynamically derived to adapt to local characteristics without transmitting any overhead.
  • a joint-classifier decision tree structure may eliminate unnecessary iterations and control risk of false prediction.
  • a decoder may include an eLTR frame retention processor (not shown) that determines whether and when to mark eLTR frames as unavailable or remove from a reference list.
  • the current subject matter can be applied to a broadcast (and similar) scenario in which, in the middle of a retention period, a decoder tunes in.
  • an encoder may mark (e)LTR frame as an Instantaneous Decoding Refresh (IDR) type frame.
  • IDR Instantaneous Decoding Refresh
  • streaming may resume after the next available LTR (IDR) frame.
  • IDR Instantaneous Decoding Refresh
  • Such an approach may be similar to some current broadcast standards, which specify inter-frames as IDR frames.
  • the subject matter described herein provides many technical advantages. For example, some implementations of the current subject matter may provide for decoding blocks using an eLTR frame retained in the reference list. Such approaches may improve compression efficiency.
  • any one or more of the aspects and embodiments described herein may be conveniently implemented using digital electronic circuitry, integrated circuitry, specially designed application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) computer hardware, firmware, software, and/or combinations thereof, as realized and/or implemented in one or more machines (e.g ., one or more computing devices that are utilized as a user computing device for an electronic document, one or more server devices, such as a document server, etc.) programmed according to the teachings of the present specification, as will be apparent to those of ordinary skill in the computer art.
  • ASICs application specific integrated circuits
  • FPGAs field programmable gate arrays
  • aspects or features may include implementation in one or more computer programs and/or software that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.
  • a programmable processor which may be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.
  • Appropriate software coding may readily be prepared by skilled programmers based on the teachings of the present disclosure, as will be apparent to those of ordinary skill in the software art.
  • aspects and implementations discussed above employing software and/or software modules may also include appropriate hardware for assisting in the implementation of the machine executable instructions of the software and/or software module.
  • Such software may be a computer program product that employs a machine-readable storage medium.
  • a machine-readable storage medium may be any medium that is capable of storing and/or encoding a sequence of instructions for execution by a machine (e.g., a computing device) and that causes the machine to perform any one of the methodologies and/or
  • Examples of a machine-readable storage medium include, but are not limited to, a magnetic disk, an optical disc (e.g, CD, CD-R, DVD, DVD-R, etc.), a magneto optical disk, a read-only memory“ROM” device, a random access memory“RAM” device, a magnetic card, an optical card, a solid-state memory device, an EPROM, an EEPROM,
  • a machine-readable medium is intended to include a single medium as well as a collection of physically separate media, such as, for example, a collection of compact discs or one or more hard disk drives in combination with a computer memory.
  • a machine-readable storage medium does not include transitory forms of signal transmission.
  • Such software may also include information (e.g ., data) carried as a data signal on a data carrier, such as a carrier wave.
  • a data carrier such as a carrier wave.
  • machine-executable information may be included as a data-carrying signal embodied in a data carrier in which the signal encodes a sequence of instruction, or portion thereof, for execution by a machine (e.g., a computing device) and any related information (e.g, data structures and data) that causes the machine to perform any one of the methodologies and/or embodiments described herein.
  • Examples of a computing device include, but are not limited to, an electronic book reading device, a computer workstation, a terminal computer, a server computer, a handheld device (e.g, a tablet computer, a smartphone, etc.), a web appliance, a network router, a network switch, a network bridge, any machine capable of executing a sequence of instructions that specify an action to be taken by that machine, and any combinations thereof.
  • a computing device may include and/or be included in a kiosk.
  • FIG. 6 shows a diagrammatic representation of one embodiment of a computing device in the exemplary form of a computer system 600 within which a set of instructions for causing a control system to perform any one or more of the aspects and/or methodologies of the present disclosure may be executed. It is also contemplated that multiple computing devices may be utilized to implement a specially configured set of instructions for causing one or more of the devices to perform any one or more of the aspects and/or methodologies of the present disclosure.
  • Computer system 600 includes a processor 604 and a memory 608 that communicate with each other, and with other components, via a bus 612.
  • Bus 612 may include any of several types of bus structures including, but not limited to, a memory bus, a memory controller, a peripheral bus, a local bus, and any combinations thereof, using any of a variety of bus architectures.
  • Memory 608 may include various components (e.g, machine-readable media) including, but not limited to, a random-access memory component, a read only component, and any combinations thereof.
  • a basic input/output system 616 (BIOS), including basic routines that help to transfer information between elements within computer system 600, such as during start-up, may be stored in memory 608.
  • BIOS basic input/output system
  • Memory 608 may also include (e.g, stored on one or more machine-readable media) instructions (e.g, software) 620 embodying any one or more of the aspects and/or methodologies of the present disclosure.
  • memory 608 may further include any number of program modules including, but not limited to, an operating system, one or more application programs, other program modules, program data, and any combinations thereof.
  • Computer system 600 may also include a storage device 624.
  • a storage device e.g ., storage device 624
  • Examples of a storage device include, but are not limited to, a hard disk drive, a magnetic disk drive, an optical disc drive in combination with an optical medium, a solid-state memory device, and any combinations thereof.
  • Storage device 624 may be connected to bus 612 by an appropriate interface (not shown).
  • Example interfaces include, but are not limited to, SCSI, advanced technology attachment (ATA), serial ATA, universal serial bus (USB), IEEE 1394 (FIREWIRE), and any combinations thereof.
  • storage device 624 (or one or more components thereof) may be removably interfaced with computer system 600 (e.g., via an external port connector (not shown)).
  • storage device 624 and an associated machine-readable medium 628 may provide nonvolatile and/or volatile storage of machine- readable instructions, data structures, program modules, and/or other data for computer system 600.
  • software 620 may reside, completely or partially, within machine-readable medium 628. In another example, software 620 may reside, completely or partially, within processor 604.
  • Computer system 600 may also include an input device 632.
  • a user of computer system 600 may enter commands and/or other information into computer system 600 via input device 632.
  • Examples of an input device 632 include, but are not limited to, an alpha numeric input device (e.g, a keyboard), a pointing device, a joystick, a gamepad, an audio input device (e.g, a microphone, a voice response system, etc.), a cursor control device (e.g, a mouse), a touchpad, an optical scanner, a video capture device (e.g, a still camera, a video camera), a touchscreen, and any combinations thereof.
  • an alpha numeric input device e.g, a keyboard
  • a pointing device e.g, a joystick, a gamepad
  • an audio input device e.g, a microphone, a voice response system, etc.
  • a cursor control device e.g, a mouse
  • a touchpad e.g, an optical scanner
  • Input device 632 may be interfaced to bus 612 via any of a variety of interfaces (not shown) including, but not limited to, a serial interface, a parallel interface, a game port, a USB interface, a FIREWIRE interface, a direct interface to bus 612, and any combinations thereof.
  • Input device 632 may include a touch screen interface that may be a part of or separate from display 636, discussed further below.
  • Input device 632 may be utilized as a user selection device for selecting one or more graphical representations in a graphical interface as described above.
  • a user may also input commands and/or other information to computer system 600 via storage device 624 (e.g ., a removable disk drive, a flash drive, etc.) and/or network interface device 640.
  • a network interface device such as network interface device 640, may be utilized for connecting computer system 600 to one or more of a variety of networks, such as network 644, and one or more remote devices 648 connected thereto.
  • a network interface device include, but are not limited to, a network interface card (e.g., a mobile network interface card, a LAN card), a modem, and any combination thereof.
  • Examples of a network include, but are not limited to, a wide area network (e.g, the Internet, an enterprise network), a local area network (e.g, a network associated with an office, a building, a campus or other relatively small geographic space), a telephone network, a data network associated with a telephone/voice provider (e.g, a mobile communications provider data and/or voice network), a direct connection between two computing devices, and any combinations thereof.
  • a network such as network 644, may employ a wired and/or a wireless mode of communication. In general, any network topology may be used.
  • Information e.g, data, software 620, etc.
  • Computer system 600 may further include a video display adapter 652 for
  • a display device such as display device 636.
  • Examples of a display device include, but are not limited to, a liquid crystal display (LCD), a cathode ray tube (CRT), a plasma display, a light emitting diode (LED) display, and any combinations thereof.
  • Display adapter 652 and display device 636 may be utilized in combination with processor 604 to provide graphical representations of aspects of the present disclosure.
  • computer system 600 may include one or more other peripheral output devices including, but not limited to, an audio speaker, a printer, and any combinations thereof.
  • peripheral output devices may be connected to bus 612 via a peripheral interface 656. Examples of a peripheral interface include, but are not limited to, a serial port, a USB connection, a FIREWIRE connection, a parallel connection, and any combinations thereof.
  • phrases such as“at least one of’ or“one or more of’ may occur followed by a conjunctive list of elements or features.
  • the term“and/or” may also occur in a list of two or more elements or features. Unless otherwise implicitly or explicitly contradicted by the context in which it is used, such a phrase is intended to mean any of the listed elements or features individually or any of the recited elements or features in combination with any of the other recited elements or features.
  • the phrases“at least one of A and B;”“one or more of A and B;” and“A and/or B” are each intended to mean“A alone, B alone, or A and B together.”
  • a similar interpretation is also intended for lists including three or more items. For example, the phrases“at least one of A, B, and C;”“one or more of A,

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)

Abstract

Un décodeur comprend des circuits configurés pour : recevoir un flux de bits ; stocker une pluralité de trames de référence à long terme dans une liste de référence ; retenir une trame de référence à long terme dans la liste de référence pendant un laps de temps sur la base d'un temps de rétention ; et décoder au moins une partie d'une vidéo à l'aide de la trame de référence à long terme retenue dans la liste de référence. La présente invention concerne également un appareil associé, ainsi que des systèmes, techniques et articles associés.
EP20748672.1A 2019-01-28 2020-01-28 Signalisation explicite de rétention prolongée d'image de référence à long terme Pending EP3918799A4 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201962797806P 2019-01-28 2019-01-28
PCT/US2020/015414 WO2020159993A1 (fr) 2019-01-28 2020-01-28 Signalisation explicite de rétention prolongée d'image de référence à long terme

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EP3918799A1 true EP3918799A1 (fr) 2021-12-08
EP3918799A4 EP3918799A4 (fr) 2022-03-23

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EP (1) EP3918799A4 (fr)
JP (2) JP7498502B2 (fr)
KR (1) KR20210118155A (fr)
CN (2) CN113615184B (fr)
BR (1) BR112021014753A2 (fr)
MX (1) MX2021009024A (fr)
SG (1) SG11202108105YA (fr)
WO (1) WO2020159993A1 (fr)

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KR101335214B1 (ko) * 2006-03-15 2013-11-29 브리티쉬 텔리커뮤니케이션즈 파블릭 리미티드 캄퍼니 비디오 신호 전송 방법 및 비디오 코더
US8494049B2 (en) * 2007-04-09 2013-07-23 Cisco Technology, Inc. Long term reference frame management with error video feedback for compressed video communication
US9237356B2 (en) * 2011-09-23 2016-01-12 Qualcomm Incorporated Reference picture list construction for video coding
US10003817B2 (en) * 2011-11-07 2018-06-19 Microsoft Technology Licensing, Llc Signaling of state information for a decoded picture buffer and reference picture lists
CN103167283B (zh) * 2011-12-19 2016-03-02 华为技术有限公司 一种视频编码方法及设备
WO2013162980A2 (fr) * 2012-04-23 2013-10-31 Google Inc. Gestion de tampons d'images à références multiples permettant un codage de données vidéo
US9609341B1 (en) * 2012-04-23 2017-03-28 Google Inc. Video data encoding and decoding using reference picture lists
US9319679B2 (en) * 2012-06-07 2016-04-19 Qualcomm Incorporated Signaling data for long term reference pictures for video coding
US9332255B2 (en) * 2012-06-28 2016-05-03 Qualcomm Incorporated Signaling long-term reference pictures for video coding
WO2014111222A1 (fr) * 2013-01-16 2014-07-24 Telefonaktiebolaget L M Ericsson (Publ) Décodeur, codeur et procédés de codage d'une séquence vidéo
KR101674556B1 (ko) * 2015-07-27 2016-11-10 인하대학교 산학협력단 다수의 참조 프레임을 이용한 움직임 추정 장치 및 방법
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CN105933800A (zh) * 2016-04-29 2016-09-07 联发科技（新加坡）私人有限公司 一种视频播放方法及其控制终端

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JP2024100973A (ja) 2024-07-26
JP7498502B2 (ja) 2024-06-12
WO2020159993A1 (fr) 2020-08-06
KR20210118155A (ko) 2021-09-29
SG11202108105YA (en) 2021-08-30
JP2022524917A (ja) 2022-05-11
CN118714324A (zh) 2024-09-27
MX2021009024A (es) 2021-10-13
EP3918799A4 (fr) 2022-03-23
CN113615184A (zh) 2021-11-05
BR112021014753A2 (pt) 2021-09-28
CN113615184B (zh) 2024-08-09

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