Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/20—Design optimisation, verification or simulation
  • G06F30/23—Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2115/00—Details relating to the type of the circuit
  • G06F2115/04—Micro electro-mechanical systems [MEMS]

Definitions

• Nonprovisional Patent Application No. 15/406,600 entitled“Hierarchical Cascading in Two-Dimensional Finite Element Method Simulation of Acoustic Wave Filter Devices,” filed January 13, 2017, which claims priority to U.S. Provisional Application No.
• a wide frequency band e.g. 700 MHz at 0.5 MHz, or 1401 frequency points
• iterative hierarchical cascading may also be applied to three-dimensional simulations of SAW devices, which may otherwise be too complex for FEM simulations due to the high number of cross-sectional degrees-of-freedom involved.
• hierarchical cascading allows for independent calculation of sub-models at different frequency ranges and/or for independent calculation of different portions of the models (e.g. core blocks). This allows for parallelization and scalability, while avoiding problems of synchronization between independent computing units that occur during some implementations of parallel computing.
• FIG. 1 A is a model of an implementation of a surface acoustic wave device
• FIGs. 2 A and 2B are illustrations of an example of a unit block and a
• FIG. 3 is a graph of slowness curves for bulk acoustic waves in an
• FIG. 4A is an illustration of a series of computational meshes of unit blocks, for implementations of hierarchical cascading finite element analysis
• FIG. 4B is an illustration of conversion of a computational mesh of a unit block into a multi-port model, according to some implementations
• FIG. 4C is an illustration of cascading multi-port models to model a
• FIG. 4D is an illustration of the series of computational meshes of unit blocks of FIG. 4 A, after a first iteration of a hierarchical cascading process, according to some implementations;
• FIGs. 4E and 4F are illustrations of an iterative hierarchical cascading
• FIG. 4G is an illustration of a hierarchical cascading tree for a synchronous resonator, according to some implementations.
• FIGs. 5A-5C are illustrations of two and three dimensional models of an electrode array, according to some implementations.
• FIG. 6A is a flow chart of an implementation of a method for hierarchical cascading analysis
• FIG. 6B is a flow chart of an implementation of a method for iterative
• FIG. 7A illustrates graphs of admittance over frequency for a measured example surface acoustic wave resonator and a simulated surface acoustic wave resonator, according to some implementations
• FIG. 7B illustrates shear-horizontal polarization at selected frequencies for the example surface acoustic wave resonator of FIG. 7A, according to some
• FIG. 8 illustrates graphs of admittance over frequency for a simulated
• FIG. 9 is a graph of Q-factor over frequency for a simulated temperature compensated surface acoustic wave resonator, according to some implementations.
• FIG. 10 is an illustration of a decomposition of an array into a plurality of unique unit blocks, according to some implementations;
• FIG. 11 is an illustration of slowness curves for a linear surface acoustic wave device, according to some implementations;
• FIG. 12 illustrates graphs of admittance over frequency for example models of a surface acoustic wave device generated via implementations of direct and iterative hierarchical cascading FEM in two and three dimensions;
• FIG. 13 illustrates example displacement profiles for the surface acoustic wave device of FIG. 12, according to some implementations
• FIG. 14 is an example graph illustrating relative error in estimated harmonic admittance via iterative hierarchical cascading FEM over iteration count, according to some implementations
• FIG. 15 is a block diagram of an implementation of a system for hierarchical cascading in FEM simulations and for designing electronic filters
• FIG. 16 is a block diagram of a wireless telecommunications system
• FIG. 17 is a flow diagram illustrating the design and construction of a filter using the FEM hierarchical cascading technique, according to some implementations.
• FIG. 18 is a block diagram of a system for hierarchical cascading in FEM simulations and for designing electronic filters, according to some implementations;
• FIG. 19 is an illustration of an implementation of an example SAW
• multiplexer device and a corresponding graph of insertion loss by frequency for different inputs of the multiplexer device
• FIG. 20 is a block diagram of an implementation of a system for parallel computing of hierarchical cascading in FEM simulations.
• FIG. 21 is a flow chart of an implementation of a method for parallel
• a perfectly matched layer (PML) technique may be used to model the substrate crystal.
• Certain piezo-electric materials with unsuitable anisotropy are prone to instabilities in implementations using a convolution stretched- coordinate PML (C-PML) approach, and they remain difficult to simulate.
• C-PML convolution stretched- coordinate PML
• this anomalic category includes several technologically important SAW substrates, such as 128°YX-cut LiNbCh in two dimensions, and 42° YX-cut LiTaCh in three dimensions.
• a multi-axial PML (M-PML) technique may be used in some implementations to provide an acceptable, albeit less efficient solution.
• FIG. 1 A illustrated is a model of an implementation of a
• FIG. IB is an abstracted illustration 100’ (not to scale) of the implementation of the SAW device of FIG. 1 A.
• the SAW device 100 which may be a filter, resonator, coupling element, or any other such device, may comprise a finite array finite array of conductive electrodes 110 (e.g., the interdigitated metal fingers of a resonator) and a semi-infinite substrate crystal 108.
• conductive electrodes 110 e.g., the interdigitated metal fingers of a resonator
• semi-infinite substrate crystal 108 e.g., the interdigitated metal fingers of a resonator
• One or more dielectric or piezoelectric layers below, above, and between the electrodes 110 may also be modeled.
• the SAW structure 100’ may also comprise a passivation layer (e.g., S1O2) 112 disposed over the electrodes 110 and substrate 108.
• S1O2 passivation layer
• a regional domain consisting of the electrodes 110, a portion of the substrate 108 adjacent the electrodes 110, and a portion of a vacuum 106 above the electrodes 110 may be defined and modeled in fine detail via a mesh.
• the regional domain may be surrounded by an artificial computational material consisting of a substrate PML 104 and a vacuum PML 102, which interfaces smoothly with the modeled domain and which has the property that incident propagating acoustic waves are converted into exponentially decaying acoustic waves.
• the regional domain, along with the substrate PML 104 and vacuum PML 102, are computationally meshed and a frequency response is computed using the FEM. While this approach is unstable in some substrates with unsuitable anisotropy, in many implementations, using a PML is a very efficient solution to the open boundary problem.
• FIG. 1C is a modified illustration of the abstraction of FIG. IB representing the use of an implementation of a hierarchical cascading finite element analysis method on the SAW device of FIG. 1 A.
• the SAW device may be partitioned into portions or unit blocks 115B, of which many may be identical. Only unique unit blocks need be modeled or simulated, while identical unit blocks may be excluded from modeling.
• the sides of the device may be terminated in dedicated PML blocks 115 A, 115C for analysis, as external degrees-of-freedom.
• the device 100’ is accordingly analyzed as a hierarchical tree of cascading operations, where adjacent smaller blocks are combined into larger blocks, eventually covering the whole device. In 2D this is drastically more efficient than conventional FEM, and may also be applied in many implementations to 3D SAW simulation and bulk acoustic wave (BAW) devices.
• BAW bulk acoustic wave
• the device geometry is partitioned into a sequence of repeating unit blocks 200 (e.g. similar to unit block 115B discussed above), an example implementation of which is illustrated in FIG. 2A.
• a typical unit block 200 may include a rectangular substrate volume 202, an electrode 204, and the vacuum 206 above.
• the electrode 204 may consist of multiple metals, depending on implementation, and may be covered by a stack of dielectric layers (yellow and red in the illustration of FIGs. 2A and 2B).
• G L and G R denote the left and right edges of the unit block 200, respectively, while r e is the electrode boundary.
• the acoustic aperture dimension is into the page.
• brackets is the system matrix, consisting of the stiffness matrix K, damping matrix D, and mass matrix M. They are inherently symmetric.
• the vector x contains the DOFs of the model: the nodal values of mechanical displacement and electric potential at the nodes.
• the vector F contains the external sources-the charge density and the boundary stresses.
• the degrees-of-freedom and the external sources can be classified into those associated with the left edge (L), the right edge (R), interior (I), and the electric potential connected to an electrode (v).
• the system of equations (1) can be reordered as:
• A is the reordered system matrix.
• the equations associated with the electric DOF on the electrode have also been included; this can be interpreted as integration over charge density.
• each unit block may be
• the dedicated PML blocks at the sides also absorb radiation in the horizontal direction, as shown above in units 115A and 115C of FIG. IB.
• the different directions may require using different PML techniques, with different types coexisting in the corners. In various implementations, one or more of the following techniques may be employed.
• the stretching factors m may be complex- valued and frequency-dependent. Stretching is only applied in the direction where absorption is required, in many implementations.
• Re w3 With Re w3) > 0, the propagating wave is effectively converted into a decaying wave, which tends to zero as X 3 - ⁇ . Moreover, any residual wave component reflected from the bottom boundary will further decay on its way back upwards to the surface.
• An imaginary part Im w 3 ) > 0 can be interpreted as geometric scaling; it enhances the decay of surface modes into the PML. However, it also accelerates the oscillation of propagating waves.
• Fig. 3 is a graph of slowness curves for bulk acoustic waves (BAWs) in an implementation of a 128° YX-cut LiNbCb device. Blue, red, and magenta curves correspond to slow shear, fast shear, and longitudinal bulk-acoustic waves, respectively.
• BAWs bulk acoustic waves
• red, and magenta curves correspond to slow shear, fast shear, and longitudinal bulk-acoustic waves, respectively.
• the fast shear wave has concave slowness curvature.
• the arrows indicate the direction of power flow, parallel to the outward normal of the slowness curves.
• Multi-Axial Perfectly Matched Layer may be used to improve instability issues in the simulation.
• M- PML coordinate stretching is applied also parallel to the layer interface.
• the proportionality constant r may be chosen based on the anisotropy of the substrate and the direction of the PML. For r 0, the M- PML reduces to a conventional C-PML.
• a sufficiently large stretching ratio r stabilizes the M- PML.
• the M-PML technique is more prone to reflections than the C-PML technique, especially for shallow propagation angles.
• the computational mesh, the r- parameter, and the attenuation profile m ⁇ x) should be optimized simultaneously, carefully considering the trade- off between the absorbing efficiency of the M-PML and the strength of reflections.
• the 3x3 matrix in the above equation may be referred to in some implementations as the “B-matrix”.
• the FEM system matrix A in Eq. (2) is symmetric and very sparse.
• the B- matrix is also symmetric but full. It shares some similarity with the admittance matrices in network theory.
• This vector may be used to compute an extended B-matrix, defined as:
• the extended B-matrix enables correct handing of N-port devices in the cascading process. It remains symmetric. The effect of electrode resistivity can also be subsumed to the extended B-matrix.
• a B-matrix depends only on the number of DOFs at the edges and on the number of electric connections. If all mesh edges are compatible, the cascaded B- matrix has the same size as the original B-matrices. Moreover, cascaded B-matrices can be further cascaded to describe longer structures. Hence, in many implementations of hierarchical cascading, a B-matrix can describe SAW structures from a single unit block to aggregated sequences of arbitrarily many electrodes, providing easy and efficient scalability.
• the SAW structure may be described as a series of cascading operations.
• the device is decomposed into unit blocks, which typically contain only one electrode or none at all.
• the device structure is analyzed automatically to identify repeated patterns at different length scales; the aim is to use as few cascading operations as possible. This is somewhat analogous to text compression algorithms.
• FIG. 4A is an illustration of a series 400 of computational meshes of unit blocks 402, for implementations of hierarchical cascading finite element analysis.
• a SAW device may be conceptually partitioned into a series of unit blocks 402.
• the unit blocks may be substantially identical, in many implementations, or may be grouped into identical subsets (e.g. unit blocks having a ground connection to an electrode, unit blocks having a positive voltage connection to an electrode, etc.).
• each unit block may be modeled as a single multi-port device, with each port having many degrees-of-freedom.
• FIG. 4B is an illustration of conversion of a computational mesh of a unit block 402 into a multi-port model 402’, according to some implementations. As shown, the resulting model of the unit block may be represented by a B-matrix as discussed above.
• FIG. 4C is an illustration of cascading multi-port models 402’ to model a combination of unit blocks, according to some implementations.
• adjacent multi-port models 402A’, 402B’ may be combined (e.g. via Eqs. 11-14) to generate a combined unit block model 404’, which may similarly comprise a single multi -port device model with each port having degrees-of-freedom representing the combined contribution of each unit block 402’ contained within the combination.
• the combined B-matrix BAB of the combined unit block model 404’ is of the same size as matrices BA and BB.
• FIG. 4D is an illustration of the series of computational meshes of unit blocks of FIG. 4A, after a first iteration of a hierarchical cascading process, according to some implementations.
• individual unit block models 402’ may be combined into a series of combined unit block models 404’, each represented with a dashed outline.
• a single iteration has occurred, creating a second level of the hierarchy.
• the process may be repeated to further combine already-combined models into larger and larger blocks, until the entire device may be modeled as a B-matrix, as shown in the illustrations of FIGs. 4E and 4F.
• the combination unit blocks may be further combined to generate a single B-matrix model of all four individual unit blocks, with the process further iterating until a single B-matrix model represents the entire device.
• the full solution may be recovered from the single B- matrix model with inverse cascading, as discussed herein, to recover the original degrees-of-freedom.
• a resonator 420 may comprise a series of identical electrodes with different connectivity, represented by the values 0 (grounded), 1 (upper bus), and 2 (lower bus). Each node in the tree represents a B-matrix for the electrode sequence in the box.
• the system is too complex to be modeled directly. Instead, through cascading of steps 430-440, the unit blocks may be divided down into identical sets of representative blocks which may then be analyzed, and then reconstructed to generate the complete model.
• unique unit blocks 422 may be analyzed.
• Block 424 may be skipped, as it is identical to a block that has already been analyzed.
• the combination of each pair of unit blocks may be used to generate the four unit blocks at step 432.
• the blocks shown in white e.g. 00 and 12
• the blocks shown in grey are identical to the blocks in white, and need not be analyzed.
• larger blocks may be constructed as a combination of previously evaluated blocks and/or may be identical to already constructed blocks.
• the model of the device 420 may be decomposed into a structure that may be more efficiently analyzed, and cascaded to generate the complete model.
• the net electric currents can be directly evaluated as
• the other observables of interest can be calculated as a post- processing step.
• all internal degrees-of-freedom can be retrieved by inverting the cascading process shown in FIG. 4G.
• the hierarchical cascading tree may be walked
• step 602 core block FEM models may be identified, and at step 604, B-matrices for the core block models may be evaluated or solved.
• step 606 a cascading process may be performed to successfully evaluate larger unit blocks based on combinations of analyzed unit blocks.
• an inverse cascading process may be utilized at step 608 (shown in dashed line) to identify all internal degrees-of-freedom.
• post processing steps may be applied to finalize the model at step 610.
• a physical model of the AW structure is defined and partitioned into a plurality of original unit blocks.
• Each original unit block may comprise zero or one electrode in many implementations.
• At least one core block is identified within the plurality of original unit blocks, and an FEM analysis is performed to compute the electrical characteristics of the core block(s) and produce a sparse, symmetric FEM system matrix, A, for each core block.
• the FEM is used to compute the DOFs in the form of acoustic and electric fields inside of the core block(s) excited by the electric potential (if any) on the electrodes (if any) within the core block(s) and the forces and electric potentials occurring at the boundaries of the core block(s).
• the internal DOFs are removed from each of the meshed core block(s) to produce reduced system B-matrices or dense, symmetric“boundary matrices” representing reduced core blocks.
• Computing the response of each of the core blocks using the FEM thus may include generating an A-matrix having left-side boundary DOFs, right-side boundary DOFs, and internal DOFs, and removing the internal DOFs from the A-matrix to generate a B-matrix comprising only the left-side boundary DOFs, the right-side boundary DOFs, and the electric potential and net surface charge on the electrode(s) (if any), as discussed above.
• electrode resistive losses can be subsumed into the B-matrices.
• specified electrical connections may be employed to form extended B -matrices that define one or more types of original unit blocks from each core-block B-matrix (e.g. 0, 1, 2 as discussed above in connection with FIG. 4).
• the number of original unit blocks may be reduced down to a minimum number of types (each type with its own unique voltage), so that the unit blocks can be more efficiently cascaded down to a single block.
• a hierarchical cascading pattern is determined from the nature and pattern of the original unit blocks at step 606, and adjacent sets of unit blocks originating from the unit blocks (e.g. blocks 0, 1, 2 of FIG. 4G, as shown) are either combined or transferred from their current hierarchical level to the next in accordance with the determined hierarchical cascading pattern until a single block subsuming all of the original unit blocks is realized.
• a set of adjacent blocks may, e.g., include only original unit blocks, at least one original unit block and at least one cascaded unit block, or only cascaded unit blocks.
• cascading the responses of each set of adjacent unit blocks may include combining the extended and/or cascaded B-matrices of the respective set of adjacent unit blocks into a single new combined C-matrix having left-side boundary DOFs corresponding to the left-side boundary DOFs of a left one of the respective set of adjacent unit blocks, right-side boundary DOFs corresponding to a right one of the respective set of adjacent unit blocks, and internal DOFs (center DOFs in the case where the set of adjacent unit blocks only include two unit blocks) corresponding to shared edges or a shared edge between adjacent ones of the unit blocks; and removing the internal DOFs from the single new combined C-matrix to create a new cascaded B-matrix comprising only left-side boundary DOFs and right-side boundary DOFs.
• an original unit block or cascaded unit block Once the characteristics of an original unit block or cascaded unit block are computed, such computed original unit blocks or cascaded unit blocks can be conveniently referenced during subsequent cascading operations at the same hierarchical level or at the next hierarchical level.
• the cascading process may repeat iteratively for each subsequent hierarchical level until the FEM hierarchical cascading process has resulted in a single block subsuming all of the original unit blocks.
• FIGs. 5A-5C An example implementation of a unit cell is depicted in FIGs. 5A-5C.
• FIG. 5 A illustrates the unit cell in a 2D finite mode, with 16 nodes and 200 boundary degrees-of-freedom, resulting in 3200 interior degrees-of-freedom.
• FIG. 5B illustrates the unit cell in a 3D periodic mode, with 32 nodes and 200 vertical degrees-of-freedom, resulting in 6400 boundary degrees- of-freedom.
• periodic boundary conditions are applied along the x-direction.
• Hierarchical cascading can be applied by splitting the unit cell into small unit blocks along the aperture direction.
• a 2D simulation can be run in a few seconds per frequency point and can be run on a very modest hardware.
• a 3D periodic analysis takes a few hours and requires a heavy desktop with 32-64 GB of RAM.
• a 3D finite-structure simulation would require years of computation and several TB of RAM.
• FEM is particularly computationally demanding, because calculating frequency responses and other parameters with a high accuracy requires analyzing several nodes per wavelength, frequently 10, 20, or 30 or more nodes.
• an iterative cascading algorithm may be used. This expands on the implementation illustrated in FIG. 6A, or direct hierarchical cascading, by iteratively refining guesses for initial core blocks and modes while progressively reducing error rates until achieving a final model.
• a flow chart of an implementation of a method for iterative hierarchical cascading is illustrated in FIG. 6B. As shown, at step 602, core block FEM models are identified, and at step 620, an initial guess for the suitable modes is generated, for example based on 2D periodic solution.
• the core B-matrices are generated at step 622, similar to step 604 discussed above.
• the solution within the approximate base is calculated via the cascading process discussed above, and inverse cascading is applied, if desired, to generate a final approximate solution expressed in terms of the original DOFs.
• a local error at each unit block boundary is estimated and compared to a threshold at step 626.
• the error may be measured in terms of stress discontinuities across unit blocks, or a difference of displacement to that imposed by approximate boundary stresses.
• the error vectors across the device form a linear space, which is partially independent of the original modal base. Selected linearly independent components of that error space are included in the modal base of Eq. (21) at step 628, and the process is repeated. The iteration is continued until sufficient accuracy is reached at step 626 (e.g. accuracy greater than a threshold level, or error rates less than a threshold). As each iteration increases the dimension of the mode base, eventually the process will cover all the original DOFs.
• Post processing may then be applied at step 610, as discussed above.
• step 610 Post processing may then be applied at step 610, as discussed above.
• Matlab platform using a custom mesh generation algorithm and an FEM engine.
• the mesh generation is based on a modified version of Chew’ second Delaunay refinement algorithm; in particular, mechanisms were introduced to relax mesh fidelity criteria within thin films.
• a triangulated mesh is used in the vicinity of the electrodes: an increased element density around the electrode corners is highly beneficial for modeling the charge density distribution, resulting in improved accuracy of the simulated capacitance.
• the mesh is regular and consists of quadrilateral elements, as shown in FIG. 2B.
• the simulation speeds are reported for an elderly desktop PC (CPU i7-2600k, 3.4 GHz, 32 GB RAM), with computation distributed over four parallel threads.
• the first example is a synchronous resonator on a 42° YX- cut LiTaCh
• the simulated admittance curves are compared in the graph at the left of FIG. 7 A, with (in this case, the real portion of the admittance (Re(Y)) and the absolute admittance (
• the small differences are mostly due to differences in the modeling of resistivity.
• FIG. 7A also illustrates a visualization of the absolute power flow ⁇ P ⁇ at the selected frequencies shown, evaluated using inverse cascading.
• the white vertical lines mark the boundary between reflectors and transducer. Different color scale is used at different frequencies. Losses due to acoustic radiation are manifested as power flow towards the bottom or through the reflectors.
• the resonance frequency (1964 MHz) shows strong confinement of acoustic energy both laterally and in depth direction. In the middle of the stopband (2000-2100 MHz), the most prominent feature is localized bulk- wave radiation from the transition region between the IDT and the reflectors. Strong synchronous bulk-wave excitation can be seen at 2150 MHz.
• FIG. 7B illustrates a visualization of the dominant shear-horizontal component of the mechanical displacement at the selected frequencies.
• the second example demonstrates an advanced SAW structure, a
• TCSAW temperature compensated SAW
• PML2 is otherwise the identical but with more normal substrate between the surface and the PML; the rationale is to direct radiation from the unstable bottom PML to the stable lateral PMLs.
• the third one uses an optimized M-PML.
• the stretching ratio r ⁇ 0.02 seems sufficient to completely stabilize the M-PML.
• the stretching profile m3(c3) must be made more gradual than in the C-PML approach. Consequently, a thicker absorbing layer must be used to reach a comparable level of absorption.
• the side PMLs are implemented using the C-PML approach. All PMLs use the attenuation profile from Eq. (6).
• FIG. 9 shows the Q-factor simulated in the M-PML configuration.
• the Q- factor remains high from the resonance to the antiresonance (shown in dashed vertical lines).
• FIG. 12 illustrates graphs of admittance over frequency for example models of a surface acoustic wave device generated via implementations of direct and iterative hierarchical cascading FEM in two and three dimensions for ease of comparison.
• the 3D simulation shows pronounced radiation at frequencies above the resonance, characteristic to LSAW radiation to busbars.
• the interpretation is the confirmed by the displacement profiles shown in FIG. 13.
• the vertical lines indicate the boundaries between the PMLs, busbars, and the IDT. Note the asymmetry of the shear vertical component.
• the longitudinal displacement component u x vanishes due to antisymmetry about the electrode center.
• FIG. 14 is an example graph illustrating relative error in estimated harmonic admittance via iterative hierarchical cascading FEM over iteration count, according to some implementations shows the convergence of the harmonic admittance at 2000 MHz.
• An exponential convergence rate is achieved, however with spontaneous fluctuations in the error rate. This behavior seems characteristic to the iterative cascading, repeating over wide range of frequencies and from structure to another.
• the achieved average simulation speed was about 10-30 min / frequency point, depending on the frequency and on the convergence criterion.
• FIG. 15 is a block diagram of an implementation of a system for hierarchical cascading in FEM simulations and for designing electronic filters
• FIG. 16 is a block diagram of a wireless telecommunications system
• Such AW microwave filters are advantageous in applications that have demanding electrical and/or environmental performance requirements and/or severe cost/size constraints, such as those found in the radio frequency (RF) front ends of mobile communications devices, including cellphones, smartphones, laptop computers, tablet computers, etc. or the RF front ends of fixed- location or fixed-path communications devices, including M2M devices, wireless base stations, satellite communications systems, etc.
• RF radio frequency
• Example AW microwave filters described herein exhibit a frequency
• a telecommunications system 1610 for use in a mobile communications device may include a
• duplexer 1618 having a transmit filter 1624 and a receive filter 1626, a transmitter 1620 coupled to the antenna 1616 via the transmit filter 1624 of the duplexer 1618, and a receiver 1622 coupled to the antenna 1616 via the receive filter 1626 of the duplexer 1618.
• the transmitter 1620 includes an upconverter 1628 configured for converting a baseband signal provided by the controller/processor 1614 to an RF signal, a variable gain amplifier (VGA) 1630 configured for amplifying the RF signal, a bandpass filter 1632 configured for outputting the RF signal within an operating frequency band selected by the controller/processor 1614, and a power amplifier 1634 configured for amplifying the filtered RF signal, which is then provided to the antenna 1616 via the transmit filter 1624 of the duplexer 1618.
• VGA variable gain amplifier
• the receiver 1622 includes a notch or stopband filter 1636 configured for rejecting signal interference from the RF signal input from the antenna 1616 and transmitter 1620 via the receiver filter 1626, a low noise amplifier
• LNA 1638 configured for amplifying the RF signal from the stop band filter 1636 with a relatively low noise
• a bandpass filter 1640 configured for outputting the amplified RF signal within an operating frequency band selected by the controller/processor 1614
• a downconverter 1642 configured for down-converting the RF signal to a baseband signal that is provided to the controller/processor 1614.
• the function of rejecting signal interference performed by the stop-band filter 1636 can instead or also be performed by the duplexer 1618.
• transmitter 1620 can be designed to reduce the signal interference to the receiver 1622.
• the functions performed by the up converter 1628, VGA 1630, bandpass filter 1640, downconverter 1642, and controller/processor 1614 are oftentimes performed by a single transceiver chip or device.
• the function of the bandpass filter 1632 can be performed by the power amplifier 1634 and the transmit filter 1624 of the duplexer 1618.
• microwave filters for the RF front-end comprised of the duplexer 1618, transmitter 1620, and receiver 1622, of the telecommunications system 1610, and in particular the transmit filter 1624 of the duplexer 1618, although the same technique can be used to design acoustic microwave filters for the receive filter 1626 of the duplexer 1618 and for other RF filters in the wireless transceiver 1612.
• FIG. 17 is a flow diagram illustrating the design and construction of a filter using the FEM hierarchical cascading technique, according to some implementations.
• the filter requirements which comprise the frequency response requirements (including passband, return loss, insertion loss, rejection, linearity, noise figure, input and output impedances, etc.), as well as size and cost requirements, and environmental requirements, such as operating temperature range, vibration, failure rate, etc., are defined to satisfy the application of the filter (step 1702).
• the structural types of circuit elements to be used in the AW filter are selected; for example, the structural type of AW resonators and/or coupling elements (SAW, BAW, FBAR, MEMS, etc.) and the types of inductors, capacitors, and switches, along with the materials to be used to fabricate these circuit elements, including the packaging and assembly techniques for fabricating the filter, are selected (step 1704).
• SAW structural type of AW resonators and/or coupling elements
• BAW BAW, FBAR, MEMS, etc.
• inductors, capacitors, and switches along with the materials to be used to fabricate these circuit elements, including the packaging and assembly techniques for fabricating the filter.
• SAW resonators may be selected, which may be fabricated by disposing IDTs on a piezoelectric substrate, such as crystalline Quartz, Lithium Niobate (LiNbCh), Lithium Tantalate (LiTaCh) crystals or BAW (including FBAR) resonators or MEMS resonators.
• a piezoelectric substrate such as crystalline Quartz, Lithium Niobate (LiNbCh), Lithium Tantalate (LiTaCh) crystals or BAW (including FBAR) resonators or MEMS resonators.
• the selected circuit element types are SAW resonators and capacitors constructed on a substrate composed of 42-degree X Y cut LiTaCh.
• Nth order ladder topologies are described in U.S. Pat. Nos. 8,751,993 and 8,701,065 and U.S. patent application Ser. No.
• initial physical models of the filter's AW components are defined (or modified), e.g., by selecting a material, one or more of a number of finger pairs, aperture size, mark-to-pitch ratio, and/or transducer metal thickness (step 1708), and the physical models of the AW components are simulated using the FEM hierarchical cascading technique to determine their frequency-dependent electrical characteristics (step 1710).
• these electrical characteristics of the AW components are
• step 1712 incorporated into a circuit model of the entire filter network (step 1712), and the circuit model of the filter network is simulated (optionally optimizing non-AW component parameters) to determine the filter's frequency characteristics (step 1714).
• the simulated frequency response of the AW filter is then compared to the frequency response requirements defined at step 1702 (step 1716). If the simulated frequency response does not satisfy the frequency response requirements, the process returns to step 1708, where the physical model of the AW is modified. If the simulated frequency response does satisfy the frequency response requirements (step 1702), an actual acoustic filter is constructed based on the most recent physical models of the AW components
• the circuit element values of the actual acoustic filter will match the corresponding circuit element values in the most recent optimized filter circuit design.
• the FEM hierarchical cascading technique has been disclosed herein as being applied to SAW structures having strict periodicity, it should be appreciated that the FEM hierarchical cascading technique can be applied to devices having breaks in periodicity, such as“hiccup” resonators or devices with“accordion sections.” In the case of such devices, the FEM hierarchical cascading technique can be applied to the strictly periodic structures, whereas“one-off’ cells or small number of aperiodic cells can be inserted between the periodic sections.
• the term“SAW,” as used herein, includes all types of acoustic waves, such as quasi-Rayleigh waves,“leaky” SAW, Surface Transverse Waves, STW, Lamb modes, etc.— that is, all types of acoustic waves with propagation mainly near the surface of, or in a layer of limited depth, for which components radiated into the bulk represent undesirable“second-order” effects.
• a computerized filter design system 1800 may be used to simulate an AW structure and an AW filter using the design procedures discussed herein.
• the computerized filter design system 1800 generally comprises a user interface 1802 configured for receiving information and data from a user (e.g., parameter values defining the physical model of the AW structure and AW filter requirements) and outputting frequency-dependent characteristics of the AW structure and filter to the user; a memory 1804 configured for storing a filter design
• program 1808 (which may take the form of software instructions, which may include, but are not limited to, routines, programs, objects, components, data structures, procedures, modules, functions, and the like that perform particular functions or implement particular abstract data types), as well as the information and data input from the user via the user interface 1802; and a processor 1806 configured for executing the simulation software program.
• the simulation software program 1808 is divided into sub-programs, in particular, a conventional FEM program 1810 (which can be used to compute characteristics of the core blocks and PML absorber blocks); a hierarchical cascading program 1812 (which can be used to partition the physical model, identify core blocks, compute the characteristics of the core blocks, remove DOFs from core blocks, define types of unit blocks, determine hierarchical cascading pattern, identify and cascade sets of adjacent unit blocks, recognize a single unit block subsuming all original unit blocks, terminate the single block with absorber blocks, compute characteristics of absorber blocks, cascade the single subsuming block with the absorber blocks, and determine the frequency-dependent electrical characteristics of the entire terminated AW structure; and a conventional filter optimizer 1814 (which can be used to optimize and simulate the circuit model of the filter network).
• a conventional FEM program 1810 which can be used to compute characteristics of the core blocks and PML absorber blocks
• a hierarchical cascading program 1812 which can be used to partition the physical model, identify core
• hierarchical cascading in FEM simulations of SAW devices, which offers drastically reduced memory consumption and simulation times.
• iterative hierarchical cascading may also be applied to three-dimensional simulations of SAW devices, which may otherwise be too complex for FEM simulations due to the high number of cross-sectional degrees-of-freedom involved
• the present disclosure is directed to a method of generating an acoustic wave device.
• the method includes (a) partitioning, by a computing system, a physical model of an acoustic wave device into a plurality of core unit blocks.
• the method also includes (b) computing, by the computing system, characteristics for a first core unit block of the plurality of core unit blocks according to a modal matrix based on a first set of basis values.
• the method also includes (c) calculating, by the computing system, a single block representing the physical model of the acoustic wave device based on the computed characteristics for the first core unit block of the plurality of core unit blocks and derived characteristics for each other core unit block of the plurality of core unit blocks.
• the method also includes (d) determining, by the computing system, that one or more local errors at each boundary of the plurality of core unit blocks exceeds a threshold.
• the method also includes (e) responsive to the determination, repeating steps (b)-(d) with an adjusted modal matrix based on a second set of basis values, the second set of basis values comprising at least one independent component of an error vector associated with the one or more local errors.
• the method also includes (f) comparing, by the computing system, a frequency response of the calculated single block representing the physical model of the acoustic wave device to a set of frequency response requirements, responsive to determining that the one or more local errors at each boundary of the plurality of core unit blocks do not exceed the threshold.
• the method also includes (g) generating, by the computing system, a set of specifications for the acoustic wave device based on the comparison, the set of specifications serving as an input to a manufacturing process.
• the method includes deriving, by the computing system, characteristics for each other core unit block of the plurality of core unit blocks from the computed characteristics for the first core unit block; and combining, by the computing system, the first core unit block and each other core unit block into the single block such that the single block subsumes the first core unit block and each other core unit block.
• the method includes hierarchically cascading sets of adjacent unit blocks into the single block.
• the method includes (h) combining sets of adjacent unit blocks at a current hierarchical level to create cascaded unit blocks at a next hierarchical level; and (i) repeating step (h) for sets of adjacent unit blocks for the next hierarchical level until the single block is created, wherein each of the unit blocks is either a core unit block or a previously cascaded unit block.
• any of the unit blocks that are not combined at the current hierarchical level are transferred from the current hierarchical level to the next hierarchical level.
• a first unit block has previously computed characteristics, and at least one other of the unit blocks is physically and electrically identical to the first unit block, and the method further includes referencing the first unit block to assume the previously computed characteristics for the at least one other unit block when combining the sets of adjacent unit blocks at the current hierarchical level.
• the method includes generating an A-matrix
• each other core unit block of the plurality of core unit blocks are derived from the B-matrix of the first core unit block.
• the method includes cascading a first set of adjacent unit blocks into a first cascaded unit block by: combining B-matrices of the respective adjacent unit blocks of the first set into a first C-matrix having left-side boundary DOFs corresponding to the left-side boundary DOFs of a left one of the adjacent unit blocks, right-side boundary DOFs corresponding to a right one of the adjacent unit blocks, and internal DOFs corresponding to at least one shared edge between the adjacent unit blocks; and reducing the first C-matrix by removing the internal DOFs from the first C- matrix to a first new cascaded B-matrix of a first cascaded unit block comprising only left-side boundary DOFs and right-side boundary DOFs.
• the method includes identifying the one or more local errors as stress discontinuities across boundaries between unit blocks. In some implementations, the method includes identifying the one or more local errors as differences of displacement to that imposed by approximate boundary stresses between unit blocks.
• the computed characteristics for the first core unit block comprise acoustic and electric fields. In some implementations, all of the core unit blocks are physically identical to each other. In other implementations, at least two of the core unit blocks are physically different from each other.
• the present disclosure is directed to a filter design system.
• the system includes a processor; an interface coupled to the processor; and memory storing a hierarchical cascading program. Execution of the hierarchical cascading program by the processor causes the filter design system to perform actions comprising: (a) partitioning a physical model of an acoustic wave device into a plurality of core unit blocks; (b) computing characteristics for a first core unit block of the plurality of core unit blocks according to a modal matrix based on a first set of basis values; (c) calculating a single block representing the physical model of the acoustic wave device based on the computed characteristics for the first core unit block of the plurality of core unit blocks and derived characteristics for each other core unit block of the plurality of core unit blocks; (d) determining that one or more local errors at each boundary of the plurality of core unit blocks exceeds a threshold; (e) responsive to the determination, repeating steps (b)-(d) with an adjusted modal matrix based on a second set of basis values, the second set of basis values compris
• execution of the hierarchical cascading program further causes the filter design system to: derive characteristics for each other core unit block of the plurality of core unit blocks from the computed characteristics for the first core unit block; and combine the first core unit block and each other core unit block into the single block such that the single block subsumes the first core unit block and each other core unit block.
• execution of the hierarchical cascading program further causes the filter design system to: derive characteristics for each other core unit block of the plurality of core unit blocks from the computed characteristics for the first core unit block; and combine the first core unit block and each other core unit block into the single block such that the single block subsumes the first core unit block and each other core unit block.
• execution of the hierarchical cascading program further causes the filter design system to: derive characteristics for each other core unit block of the plurality of core unit blocks from the computed characteristics for the first core unit block; and combine the first core unit block and each other core unit block into the single block such that the single block subsumes the first core unit
• execution of the hierarchical cascading program further causes the filter design system to: (h) combine sets of adjacent unit blocks at a current hierarchical level to create cascaded unit blocks at a next hierarchical level; and (i) repeat step (h) for sets of adjacent unit blocks for the next hierarchical level until the single block is created, wherein each of the unit blocks is either a core unit block or a previously cascaded unit block.
• execution of the hierarchical cascading program further causes the filter design system to identify the one or more local errors as stress discontinuities across boundaries between unit blocks. In some implementations, execution of the hierarchical cascading program further causes the filter design system to identify the one or more local errors as differences of displacement to that imposed by approximate boundary stresses between unit blocks.
• FIG. 19 is an illustration of an implementation of an example
• SAW multiplexer device 1900 and a corresponding graph 1902 of insertion loss by frequency for different inputs of the multiplexer device 1900.
• a typical implementation of such a quadplexer device 1900 may include 32 unique SAW resonators. Output characteristics of the device may be simulated across a wide frequency band (e.g. 700 MHz) with high resolution (e.g. 0.5 MHz increments, yielding 1401 frequency points). Given a finite time to perform the output calculations for each frequency point for one resonator of 1 second, the total simulation of the quadplexer would require 44,832 seconds or 12.45 hours of simulation time) This may be impractical for many uses, particularly as designs are updated or modified, requiring repeated re-simulation.
• the calculations at each frequency point are independent of each other, and accordingly, the simulation may be divided amongst a plurality of computing units (e.g. virtual machines in a cloud server, physical machines in a cluster, etc.).
• a plurality of computing units e.g. virtual machines in a cloud server, physical machines in a cluster, etc.
• Frequency ranges may be provided to each computing unit for simulation, and an aggregating device may merge the results to generate a complete model, allowing for parallel calculation of sub-models.
• modeling of core blocks may similarly be parallelized by assigning different computing units of the cluster or cloud to model or solve matrices for different blocks.
• a highly complex acoustic device may be simulated as a combination of unit blocks.
• three unique unit blocks may be used to represent the entire device through various combinations. Each of the unit blocks may be considered
• FIG. 20 is a block diagram of an implementation of a system 2000 for
• One or more client devices 2002A-2002N operated on behalf of a circuit designer, analyst, or engineer may communicate via a network 2004 with a manager service 2006 and/or one or more computation servers 2010 of a cloud computation service 2008.
• Client device(s) 2002 may comprise any type and form of computing device, including laptop computers, desktop computers, embedded computers, portable or wearable computers such as tablet computing devices, virtual computing devices executed by one or more physical computing devices (e.g. remote or hosted desktop computing devices, web applications accessed by other computing devices, etc.).
• Client device(s) 2002 may be operated by a designer or analyst to provide frequency response requirements, physical structure limitations or designs, components, topology information, or other configuration details or characteristics of one or more acoustic devices, including filters, resonators, multiplexers, etc., referred to generally as configuration information, to a manager service 2006 for parallelization and processing.
• Client devices(s) may comprise one or more components of implementations of a computerized filter design system 1800 as discussed above, including memory devices, processors, user interfaces, operating systems, applications, network interfaces, or other such devices.
• Client devices(s) 2002 may communicate via a network 2004, which may comprise a wide area network (WAN) such as the Internet, a local area network (LAN), a virtual private network (VPN), a cellular network, a satellite network, a broadband network, or any combination of these or other networks.
• WAN wide area network
• LAN local area network
• VPN virtual private network
• a client device 2002 may communicate via a LAN to a switch or gateway to a fiber-based wide area network, with communications encrypted via a VPN connection with a manager service 2006.
• Client device(s) 2002 may thus comprise any appropriate physical interface(s) including Ethernet interfaces, cellular interfaces,
• WiFi 802.11
• Bluetooth 802.11
• Manager service 2006 may comprise one or more computing devices
• manager service 2006 may comprise a web application or other hosted application provided by a web server, database server, application server, or other such entity.
• manager service 2006 may comprise a plurality of virtual computing devices provided by one or more physical computing device (e.g. a cloud service or cloud application, etc.).
• Manager service 2006 may receive configuration information for acoustic devices from one or more client devices 2002 and may assign portions of a model or sets of calculations to different computation servers or computation units 2010 provided by a cloud computation service 2008.
• Cloud computation service 2008 may comprise one or more physical
• computing devices executing one or more virtual computing devices (instantiating or executing such virtual computing devices as needed to fulfill processing requirements, in many implementations) and may be deployed as a cluster, cloud, server farm, or other such deployment.
• a plurality of virtual computing devices may appear to a user of a client device 2002 as a single massively parallel computing device, which may be managed or accessed by a manager service 2006.
• cloud computation service 2008 may communicate with manager service 2006 via a second network or networks 2004.
• manager service 2006 may comprise a computation server 2010 of the cloud computation service 2008 (e.g. a first server 2010 acting as a manager, master, host, or otherwise directing or assigning tasks and aggregating results from other computation servers 2010).
• FIG. 21 is a flow chart of an implementation of a method 2100 for parallel computing hierarchical cascading in FEM simulations.
• a manager service may receive filter or frequency requirements, components, topology, or other device characteristics or configurations from one or more client devices.
• the configuration information may be sent via any suitable method, including as XML data, one or more arrays, a database or flat file, a circuit diagram or graph, a 2D or 3D model, or any other suitable format.
• the manager service may identify one or more core blocks for analysis. As discussed above, the manager service may generate a physical model of a device and may partition the physical model into a plurality of core unit blocks. Each core unit block may be associated with a
• the manager service may select a computation server of a
• the manager service may select a server based on load (e.g. a server having a lowest processor or memory utilization), based on latency (e.g. a server having lowest latency in communications to the manager service), via a round robin method, or any other such method.
• selecting the server may comprise instantiating or executing the server (or directing a cloud service to instantiate or execute the server, in some
• the manager service may assign a core block to the selected computation server for processing and analysis. Assigning the core block to the selected computation server may comprise transmitting configuration information of the core block, parameters of a physical model of the core block, frequency requirements, topology, or other information, or similar data.
• the selected computation server may compute characteristics for the core unit block as discussed above. For example, in some implementations, the computation server may compute characteristics for the core unit block according to a model matrix based on a set of basis values. Steps 2106-2018 may be repeated iteratively for each additional core block of the model.
• the manager service may receive the calculated core block models from each of the computation servers. Once all models have been received, the manager service may, in some implementations, aggregate the core block models into a single model, for example, by deriving a single block representing the physical model of the device. In other implementations, the manager service may provide the models to a computation server, which may derive the single block, as discussed above. In still other implementations, the manager service may provide the core block models to each of a plurality of computation servers for subsequent processing.
• the manager service may identify one or more frequency ranges subdividing a range according to a frequency response requirement of the acoustic device.
• Each range may be assigned to a separate computation server by the manager service, e.g., by selecting a server at step 2114, and assigning the range to the server for calculating a transfer function at sample points within the assigned frequency range at step 2116.
• each computation server may also perform optimizations on the model during analysis as discussed above (e.g. adjusting the modal matrix for a core unit block based on error vectors, etc.). Such optimizations may be performed if, for example, the calculated transfer function or frequency response within the predetermined range does not meet frequency requirements for the device, as discussed above. Steps 2114-2116 may be repeated for each additional frequency range with additional computation servers.
• the manager service may receive transfer functions or
• frequency responses within each assigned range from the computation servers may aggregate the received models into a frequency response across the entire combined frequency range.
• Aggregating the models may comprise generating a single frequency response across the entire range (e.g. by summing the individually calculated responses, by appending them to one another at each range border, etc.).
• aggregating the models may also comprise comparing the aggregated frequency response to frequency response requirements, and if the aggregated response matches the requirements or meets the requirements, generating a set of specifications for the acoustic wave device based on the comparison.
• the process may be repeated iteratively or in parallel for additional acoustic devices or components that are part of the circuit in some implementations.
• the manager service may parallelize analysis of a first acoustic device by segmenting the device into core unit blocks and assigning the blocks to a first set of computation servers for analysis, and simultaneously (or while waiting for results from the analysis) may parallelize analysis of a second acoustic device for a second set of computation servers.
• analysis, modeling, and optimization of even very complex devices may be divided amongst a plurality of computation servers acting independently under control of the manager service, drastically increasing efficiency and reducing time spent to perform calculations and model the devices.
• the design specifications may be provided to another computing device for manufacturing (e.g. for control over manufacturing processes).
• the present disclosure is directed to a method of generating an acoustic wave device via parallel computing.
• the method includes partitioning, by a manager service executed by a computing device, a physical model of an acoustic wave device into a plurality of core unit blocks.
• the method also includes assigning, by the manager service, each core unit block of the plurality of core unit blocks to a corresponding computing device of a plurality of additional computing devices, each additional computing device computing characteristics for the
• the method also includes determining, by the manager service, a single block representing the physical model of the acoustic wave device based on the computed characteristics for the core unit blocks.
• the method also includes generating, by the computing system, a set of specifications for the acoustic wave device based on the computed characteristics, the set of specifications serving as an input to a manufacturing process.
• the method includes determining the single block by providing the plurality of core unit blocks to at least one additional computing device, the at least one additional computing device combining the plurality of core unit blocks into a single block that subsumes each core unit block by hierarchical cascading sets of adjacent unit blocks into the single block.
• the method includes determining the single block by combining, by the manager service, each core unit block into the single block such that the single block subsumes each core unit block by hierarchically cascading sets of adjacent unit blocks into the single block.
• hierarchically cascading sets of adjacent unit blocks into the single block includes, for each of one or more sets of adjacent unit blocks of a hierarchical level of a plurality of hierarchical levels, combining sets of adjacent unit blocks at the hierarchical level to create cascaded unit blocks at a next hierarchical level until the single block is created, wherein each of the unit blocks is either a core unit block or a previously cascaded unit block.
• any of the unit blocks that are not combined at the current hierarchical level are transferred from the current hierarchical level to the next hierarchical level.
• a first unit block has previously computed characteristics, and at least one other of the unit blocks is physically and electrically identical to the first unit block, and the method further includes referencing the first unit block to assume the previously computed characteristics for the at least one other unit block when combining the sets of adjacent unit blocks at the current hierarchical level.
• the method includes generating the set of
• the present disclosure is directed to a filter design system.
• execution of the distributed hierarchical cascading program further causes the filter design system to: provide the plurality of core unit blocks to at least one additional computing device, the at least one additional computing device combining the plurality of core unit blocks into a single block that subsumes each core unit block by hierarchical cascading sets of adjacent unit blocks into the single block.
• any of the unit blocks that are not combined at the current hierarchical level are transferred from the current hierarchical level to the next hierarchical level.
• a first unit block has previously computed characteristics, and at least one other of the unit blocks is physically and electrically identical to the first unit block, and the first unit block is referenced to assume the previously computed characteristics for the at least one other unit block when combining the sets of adjacent unit blocks at the current hierarchical level.
• execution of the distributed hierarchical cascading program further causes the filter design system to: partition a predetermined frequency range into a plurality of sub-ranges; and assign each sub-range to a corresponding computing device of the plurality of additional computing devices, each additional computing device computing characteristics of the single block representing the physical model of the acoustic wave device for one or more frequencies within the corresponding assigned sub-range.
• Implementations of the subject matter and the operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them.
• Implementations of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on one or more computer storage medium for execution by, or to control the operation of, data processing apparatus.
• the program instructions can be encoded on an artificially-generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus.
• a computer storage medium can be, or be included in, a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more of them.
• a computer storage medium is not a propagated signal
• a computer storage medium can be a source or destination of computer program instructions encoded in an artificially-generated propagated signal.
• the computer storage medium can also be, or be included in, one or more separate components or media (e.g., multiple CDs, disks, or other storage devices). Accordingly, the computer storage medium may be tangible.
• the operations described in this specification can be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.
• the term“client or“server” include all kinds of apparatus, devices, and machines for processing data, such as a programmable processor, a computer, a system on a chip, or multiple ones, or combinations, of the foregoing.
• the apparatus can include special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).
• the apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination of one or more of them.
• the apparatus and execution environment can realize various different computing model infrastructures, such as web services, distributed computing and grid computing infrastructures.
• a computer program also known as a program, software, software
• application, script, or code can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing
• a computer program may, but need not, correspond to a file in a file system.
• a program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub-programs, or portions of code).
• a computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
• processors suitable for the execution of a computer program include both general and special purpose microprocessors, and any one or more processors of any kind of digital computer.
• a processor will receive instructions and data from a read-only memory or a random access memory or both.
• the essential elements of a computer are a processor for performing actions in accordance with instructions and one or more memory devices for storing instructions and data.
• a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks.
• mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks.
• a computer need not have such devices.
• a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device (e.g., a universal serial bus (USB) flash drive), to name just a few.
• Devices suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.
• the processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.
• implementations of the subject matter described in this specification can be implemented on a computer having a display device, e.g., a CRT (cathode ray tube), LCD (liquid crystal display), OLED (organic light emitting diode), TFT (thin-film transistor), plasma, other flexible configuration, or any other monitor for displaying information to the user and a keyboard, a pointing device, e.g., a mouse, trackball, etc., or a touch screen, touch pad, etc., by which the user can provide input to the computer.
• a display device e.g., a CRT (cathode ray tube), LCD (liquid crystal display), OLED (organic light emitting diode), TFT (thin-film transistor), plasma, other flexible configuration, or any other monitor for displaying information to the user and a keyboard, a pointing device, e.g., a mouse, trackball, etc., or a touch screen, touch pad, etc., by which the user can provide input to the computer
• a computer can interact with a user by sending documents to and receiving documents from a device that is used by the user; by sending webpages to a web browser on a user’s client device in response to requests received from the web browser.
• Implementations of the subject matter described in this specification can be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the subject matter described in this specification, or any combination of one or more such back-end, middleware, or front-end components.
• the components of the system can be interconnected by any form or medium of digital data communication, e.g., a
• Communication networks may include a local area network (“LAN”) and a wide area network (“WAN”), an inter-network (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks).
• LAN local area network
• WAN wide area network
• inter-network e.g., the Internet
• peer-to-peer networks e.g., ad hoc peer-to-peer networks
• the claimed combination may be directed to a subcombination or variation of a subcombination.

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