Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
  • G06F17/10—Complex mathematical operations
  • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
  • G06F17/141—Discrete Fourier transforms
  • G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06J—HYBRID COMPUTING ARRANGEMENTS
  • G06J1/00—Hybrid computing arrangements
  • G06J1/005—Hybrid computing arrangements for correlation; for convolution; for Z or Fourier Transform

Definitions

• the present invention relates to a device for calculating an analog Fourier transform.
• the invention is particularly applicable in the fields of radars, countermeasures and active decoys, more particularly in signal processing to improve the dynamics of the signals received, and in particular for the response to interference in very short times while remaining compatible with signal dynamics to be processed.
• analog processing retains an advantage over digital processing.
• the performance of signal processing in analog is however dependent on the processing dynamics which is limited, unlike digital processing.
• the use of Fourier transforms in analog poses the problem of the achievable dynamics, including the gain linked to the filters of the Fourier transformation. It is indeed necessary to be able to process signals whose level is below the noise and to extract these signals in order to process them.
• DRFM Digital Radio Frequency Memories
• the current methods of analog processing of the Fourier transforms are based on a principle of non-overflow of the dynamics.
• An object of the invention is to overcome the drawbacks of the prior art, in particular by making it possible to increase the detection performance of the signals embedded in the noise, while keeping the assurance that the saturation does not affect the processing of the signal.
• the subject of the invention is a device for calculating an analog Fourier transform, transforming an analog input signal with N components 0), 4 1 ) N 1 ) into an output signal with N components X (0), X (1) ... X (N-1) functions of said components 0), 4 1 ) 4 N ⁇ 1 ).
• said device comprising elementary addition and / or subtraction cells of analog type chained according to a butterfly type architecture to perform said functions, each elementary cell being able to perform a division by two conditional of the result of the addition operation or subtraction performed, the condition being the saturation of an addition and / or subtraction operation.
• each elementary cell receiving as input two signals (A, B) comprises at least:
• Said elementary cells being grouped by lines and by stages, said modules of the same stage are for example controlled by the same signal, said signal controlling the division by two as soon as at least one cell delivers saturation information.
• each elementary cell receiving as input two signals A, B comprises at least:
• saturation information of the operators of the preceding stages said module delivering control information function of said saturation information
• said multiplexer selecting one of said inputs as output as a function of said control information, the selected output constituting the first output of said cell
• a second multiplexer having as inputs said outputs of said subtractor, said multiplexer selecting as output one of said inputs according to said control information, the selected output constituting the second output of said cell
• Said memory includes, for example, a state machine delivering said control information.
• FIG. 8 an illustration of an example of programming a state machine controlling the stages of a device according to the invention in a serial architecture.
• the present invention advantageously makes it possible to improve the dynamics of an electronic system carrying out a discrete fast Fourier transform (FFT).
• FFT discrete fast Fourier transform
• the principle of the invention can be extended to other types of FFT implementation.
• the minimum input power P in, min is the input power from which the system provides an output signal S called exploitable, i.e. a signal to noise ratio at output SNR 0Ut, min sufficient to exceed the background noise F:
• the background noise is defined as the sum of the thermal noise P th and the noise factor NF of the system, that is:
• the maximum input power can be defined as the power at which distortions appear at the output of the system. In practice, we can consider intermodulation products of the third order.
• the discrete fast Fourier transform is a projection of the studied signal on a base made up of sinusoidal functions.
• the transform is a filter bank where each filter is tuned on one of the vectors of the projection base, that is to say one of the sinusoids. It is therefore a set of suitable filters for which we can calculate a coherent gain.
• the presence of such a gain means that the FFT discriminates between periodic signal and non-periodic signal (here, noise). It performs a coherent integration of the useful signal.
• a noisy signal processed by an FFT can potentially be extracted from the noise in which it is embedded.
• the FFT as a bank of adapted filters, can process periodic signals over a dynamic range which is not limited to the noise floor, also called SCV (“Sub Clutter Visibility”), mentioned in the introduction.
• the FFT therefore offers an interesting property in this DMC. Indeed, the signal remains "visible” even under a certain noise threshold since the coherent gain of FFT is added to the coherent signals (frequencies correlated by the FFT) without amplifying the noise.
• the dynamics of a signal is limited by the power source in particular. If the latter offers a VDD voltage of 1 volt, for example, no signal may exceed 1 volt. This means in the case of propagated additions that saturation is possible, altering the veracity of the information transmitted.
• a classic solution consists in systematically dividing the operands by 2 during an addition. The ownership of SCV is then lost in the noise accumulated over the divisions.
• the invention incorporates a division conditional on the architecture of the FFT as will be described later.
• the division takes place on the set of N samples if and only if saturation appears.
• the saturation of an operator performing an addition or subtraction operation corresponds to the overflow of the dynamics of this operator.
• Figure 1 illustrates a known calculation algorithm, used to optimize the calculation of an 8-point FFT, in this example.
• This algorithm is commonly called a butterfly.
• the transition from one computing stage (“Radix 2") to another is done by additions or subtractions. Multiplications are performed on the intermediate data, throughout the FFT calculation algorithm.
• the formula for the applied multiplier coefficients is known. These coefficients W, WN, W £, W are trigonometric constants less than 1. They are known as "twiddle" factors.
• FIG. 2 illustrates the implementation of the invention for a parallel type architecture. More particularly, FIG. 2 shows the architecture of FIG. 1 in a configuration according to the invention, the "twiddle" factors not being represented.
• the elementary cells which carry out the operations of addition and / or subtraction are chained according to a butterfly-type structure.
• the strings of elementary cells are arranged in parallel (by lines 1 ’, 2’) and the cells of the same rank among these strings are grouped by stages. Two stages 1, 2 are shown in FIG. 2.
• the invention proposes to perform a conditional division by two.
• Saturation can come from addition as well as subtraction.
• Each operator is provided internally with a comparator capable of detecting this saturation.
• An operator then has a third Sat-i, Sat 2 , Sat'-i, Sat ' 2 output indicating the saturation state, in the form of binary information.
• Each stage is fitted with one of a door 21, 22.
• this door performs the logic OR function between all of its inputs, the latter being the saturation states provided by all of the elementary operators 1 1, 12 upstairs.
• the OR gate selects, via a multiplexer 23, 24 the appropriate output for all basic operators:
• FIG. 3 illustrates the implementation for the case of a serial architecture, by illustrating more precisely the implementation at the level of an elementary operator.
• the processing of saturations is carried out in a different way. Indeed the samples of the FFT being serialized, one can be confronted for example in the case of saturation at a stage N (N ' th stage) with the k' th operation (k> 1). If it is possible to output the operations divided by two from this k ' th operation, this also means that the previous k-1 operations have passed through the stage N without being divided by two. It is then necessary to envisage a propagation of the division to the stages according to N + n in order to preserve the same ratio of scale on the set of the treated samples. To this end, the invention provides four outputs for elementary operators.
• FIG. 3 shows an example of implementation.
• the operator 31 represented is an adder which in fact performs the following operations:
• a multiplexer 34 selects one or other of these outputs as a function of a Dec command.
• the adder is also provided with an internal comparator for detecting saturation.
• the first output delivers the present addition A + B, it is selected by the multiplexer if no saturation is detected.
• the second output delivers the present addition divided by two, (A + B) / 2. It is selected if the present addition saturates.
• the third output delivers A / 2 k + B. It is selected when saturation has taken place in the previous stage after non-saturating additions have been transmitted to this stage. We must therefore compensate for these unsaturated additions to keep the same scale with future additions which will be halved.
• the fourth output delivers (A / 2 k + B) / 2. It is selected if the previous case takes place at the same time as saturation also occurs on this stage, hence the division by 2.
• an output 33 delivering “Sat” information reporting the operator's saturation state.
• This output 33 addresses a memory 32 which, from the saturation state of each operator for each stage, issues an output decision.
• This output decision is the Dec command described above which selects via the multiplexer 34 one of the outputs described above.
• the memory 32 therefore includes a program (state machine) which makes it possible to deliver the appropriate control information as a function of the saturation information of the current operator and of the saturation information of the operators of the preceding stages.
• the command information Dec can be coded on 2 bits to select one of the four inputs of the multiplexer.
• the memory 32 constitutes a control module in the form of a state machine.
• FIG. 3 presents an adder, one can provide on the same principle a subtractor which realizes:
• FIG. 4 illustrates the general case with Q stages of FFT 4 (4-point FFT), and Q - 1 series of twidle factors, for q ranging from Q - 1 to 1.
• an FFT 4 block can be broken down simply into two FFT 2 blocks as illustrated in FIG. 5.
• FIG. 5 illustrates this breakdown into showing the elementary blocks 51 (FFT 2 ) which are no longer of the radix 4 type but of the radix 2 type, with the elementary operations ei + e 2 and ei - e 2 .
• An FFT2 block thus performs the most basic operations of the algorithm, addition (ei + e 2 ) and subtraction (ei - e 2 ).
• This elementary block of the architecture is explained in FIG. 6 which follows.
• FIG. 6 therefore illustrates an elementary block 51, radix 2 block (FFT 2 ).
• the operators 61, 62 are of the type of that of FIG. 3.
• the addition operator 61 performs the operations described in relation to FIG. 3.
• the second operator 62 is a subtraction operator operating on the same principle as the addition operator 61 as described above.
• a first multiplexer 61 selects the output of the adder 61 or the output of a second multiplexer 62’ via a delay line 63 specific to the technology used and function of the stage.
• the second multiplexer 62 ’selects the output of the subtractor 62 or the input e of the elementary block.
• the adder 61 adds this input e and the output of the delay line.
• Subtractor 62 subtracts the input e from the output of the delay line.
• the multiplexers select one or the other of their inputs according to a logic state provided by a counter whose timing diagram is presented in FIG. 7 for each of the stages, opposite successive time periods t (1), t (2) ... t (16).
• An architecture with two serialized blocks is obtained, that is to say 4 FFT 2 blocks of the type of FIG. 6 which are called stage 1, stage 2, stage 3 and stage 4.
• stage 1, stage 2, stage 3 and stage 4 The results of the elementary operations are thus produced in series at the rates of counters specific to each floor.
• the memory 32 includes a state machine.
• Figure 8 explains the operations performed on each stage as well as their serialized outputs in the previous example with 4 stages of FFT 2 for a 16-point FFT.
• S represents the storage state during which the delay line 63 of an FFT 2 elementary block is filled.
• N 16
• its depth is, from floor to floor, of 8, 4, 2 and 1.
• Sat k represents a saturation which appeared in stage k.
• the selected states are (for the outputs of the adder or subtractor described above):
• State F alternate output 4 with output 2 (see timing diagrams below).
• stage 1 the adder and the subtractor do not need outputs 3 and 4.
• State F If ((Sat 3. (Sati + Sat 2 )) - (t (12) ⁇ t (14-i) ⁇ t (14)): observe the same timing diagram as above with output 4 and output 2 to exit 3 and exit 1.
• Stage 4 state machine
• memory 32 is for example a programmable memory PROM.

Landscapes

• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Mathematical Physics (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Data Mining & Analysis (AREA)
• Pure & Applied Mathematics (AREA)
• Mathematical Analysis (AREA)
• Mathematical Optimization (AREA)
• Computational Mathematics (AREA)
• Software Systems (AREA)
• Algebra (AREA)
• Databases & Information Systems (AREA)
• General Engineering & Computer Science (AREA)
• Discrete Mathematics (AREA)
• Computer Hardware Design (AREA)
• Automation & Control Theory (AREA)
• Evolutionary Computation (AREA)
• Fuzzy Systems (AREA)
• Complex Calculations (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=67660133

Family Applications (1)

Country Status (4)

Families Citing this family (1)

Family Cites Families (3)

• 2018
  • 2018-11-08 FR FR1871456A patent/FR3088451A1/fr not_active Withdrawn
• 2019
  • 2019-11-08 WO PCT/EP2019/080745 patent/WO2020094863A2/fr not_active Ceased
  • 2019-11-08 US US17/291,258 patent/US20220004595A1/en not_active Abandoned
  • 2019-11-08 EP EP19804669.0A patent/EP3877872A2/de not_active Withdrawn

Also Published As

Similar Documents

Legal Events