EP3850745A1

EP3850745A1 - Micro solar inverter

Info

Publication number: EP3850745A1
Application number: EP18815963.6A
Authority: EP
Inventors: Christopher Fromme; Marvin TANNHÄUSER
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 2018-11-29
Filing date: 2018-11-29
Publication date: 2021-07-21
Also published as: CN113169680A; WO2020108759A1; US20220123669A1; AU2018451265B2; AU2018451265A1

Abstract

The invention relates to a micro solar inverter for converting a DC voltage provided by a photovaltaic panel into an AC voltage. The micro solar inverter does not have a transformator and has a maximum height of 24mm.

Description

description

Micro solar inverter

The invention relates to a micro solar inverter according to the preamble of claim 1.

Photovoltaic systems have an increasingly important share in the supply of electrical energy. A photovoltaic system comprises several solar panels (= photovoltaic modules) that generate electrical energy when exposed to sunlight. The solar panels are typically built essentially next to each other, for example by arranging them in a rectangular pattern on a house roof.

There are several options for the electrical connection. Thus, the solar panels can be interconnected in one or more series, one series being referred to as a "string". For each string or for the entire photovoltaic system, a converter is then provided, which converts the resulting DC voltage of the solar panels into one While the power electronics are advantageously bundled in this embodiment, the power is one

Strings depend on the fact that each of the solar panels is optimally illuminated. Shading or other influences on one or a few solar panels disproportionately impair the performance of the string.

An alternative is the use of so-called optimizers (or optimizers), which are DC / DC actuators and are arranged on each of the solar panels and perform the so-called maximum power point tracking (MPP tracking) there. This means that the performance deficits of a solar panel do not have a negative effect on other solar panels. larpanels of the same string, but additional power electronics are required on each panel.

In a further alternative, micro solar inverters (micro solar inverters) are used. These are also arranged on each of the solar panels and convert the generated DC voltage into AC voltage. The power electronics are thus decentralized and the overall or string converter can be omitted. The MPP tracking is also carried out by the micro solar inverters. This has other advantages. For example, the micro solar inverters make it possible to work with a significantly lower voltage.

Known micro-solar inverters include a transformer and filter elements. Due to their relative bulkiness, the inductive and capacitive components largely determine the dimensions of the micro-solar inverter. A micro-solar inverter arranged on the back of a solar panel (side facing away from the sun) also projects beyond the frame of a solar panel, which encloses the actual solar cell area. It is therefore not possible to lay the solar panel flat on a flat surface, which makes handling and assembly difficult.

It is an object of the present invention to provide a micro solar inverter which reduces or solves the problem mentioned at the outset. This object is achieved by a micro solar inverter with the features of claim 1.

The micro-solar inverter according to the invention for converting a DC voltage provided by a photovoltaic panel into an AC voltage has an overall height of at most 24 mm, in particular an overall height of at most 20 mm.

This ensures that a solar panel with a panel area that includes solar cells and one the panel area enclosing frame and on the panel surface angeord Neten inventive micro solar inverter does not protrude the frame. Formulated positively, "not towered over" means that the overall height of the micro solar inverter is at most so great that its maximum elevation over the panel surface corresponds at most to that of the frame.

This ensures that handling, storage and transportation of a solar panel are significantly improved. In particular, the stacking of the solar panels is much less problematic and the solar panels can be transported to save space. Damage to components due to improper stacking with a micro solar inverter protruding beyond the edge is also avoided.

According to the invention, the micro solar inverter is constructed without a transformer. Since a transformer noticeably contributes to the construction height, a clear saving of space is achieved by a transformerless construction of the micro solar inverter, which has a particular effect on the height.

According to a development of the invention, the micro-solar inverter has a galvanically coupled electrical converter for converting the ones at the first connections

DC voltage into an output voltage. The electrical converter in turn comprises an up converter connected on the input side to the first connections, an inverse converter connected on the input side to the first connections and a series circuit comprising two capacitors connected to the output side positive pole of the up converter and the output side negative pole of the inverse converter, the output side negative pole of the up converter and the positive pole of the inverse converter on the output side is connected to the center connection between the capacitors. Such a converter from a combination of a step-up converter (boost converter) with an inverse converter (inverting buck-boost converter) can provide a comparatively high output voltage by connecting the outputs in series. Since each of the converters only has to provide about half the output voltage, the respective transmission ratio is significantly reduced compared to the case of a single converter. This makes it possible to provide a high transmission ratio of, for example, more than 20, in particular more than 25, without a transformer. In addition to an improvement in efficiency, this also saves the size of the transformer.

In a further embodiment of the invention, the step-up converter can comprise a first series circuit of a first semiconductor switch or a first diode with a second semiconductor switch. The external connections of the first series connection form the poles of the step-up converter on the output side. Furthermore, the step-up converter comprises a first inductance, which is connected to the center connection of the first series circuit and the positive pole of the input voltage. In this way, a step-up converter is implemented.

A unidirectional energy flow is made possible by using a diode. If the first series connection comprises the first semiconductor switch, both energy flow directions are supported by the step-up converter. In order to clarify the design variants, it is repeated in other words that the first series circuit can either have two semiconductor switches or else a semiconductor switch and a dio de. Both construction variants can be combined with the variants mentioned below. The inverse converter can comprise a second series circuit of a third semiconductor switch with a fourth semiconductor switch or a second diode. One of the external connections forms the negative pole of the inverse converter on the output side and the other external connection is connected to the positive pole of the input voltage. Furthermore, the inverse converter comprises a second inductance, which is connected to the center connection of the second series circuit and the center connection between the capacitors. This creates an inverting render buck boost converter. Using the second diode in turn enables a unidirectional energy flow. In contrast, if the second series connection comprises the fourth semiconductor switch, both energy flow directions are supported by the inverse converter. In order to clarify the design variants, it is repeated in other words that the second series circuit can either have two semiconductor switches or a semiconductor switch and a dio de. Both construction variants can be combined with the variants mentioned below and before.

At least part of the first to fourth power semiconductor can be designed as a wide-bandgap switch, in particular gallium nitride switch, in particular as a self-locking gallium nitride switch or as a cascode with a self-conducting gallium nitride switch. This enables low-loss switching even at very high frequencies. High switching frequencies, in turn, allow the inductive and capacitive components used for the filtering to be selected to be smaller, which in turn enables the construction space, in particular the overall height, to be reduced. As switching frequency for the gallium nitride switch, a frequency of at least 200 kHz, in particular at least 500 kHz, is used in a special embodiment at least 1 MHz. A particular advantage of the use of wide bandgap switches and the high switching frequency associated with them is that the first and / or second inductor is chosen to be smaller and can therefore be designed as circuit board inductors. This enables a further reduction in the height required.

The electrical converter preferably comprises a full bridge, which is connected on the input side to the output-side poles of the up and inverse converters. In particular, the micro solar inverter is designed in such a way that the power semiconductors of the full bridge are operated at least part of the operating time as a pole reverser. The power semiconductors of the full bridge can be MOSFETs, GaN switches or other semiconductor switches.

In a further advantageous embodiment of the invention, at least some of the half bridges comprise a series-connected first and second power semiconductors, a controller for the power semiconductors, a line starting from the connection node of the power semiconductors and a device for measuring the current in the line. The controller is designed to compare the current with an upper and a lower threshold value and to switch off the first power semiconductor when the upper threshold value is reached and to switch on the second power semiconductor after a first dead time. Furthermore, the control is designed to switch off the second power semiconductor when the lower threshold value is reached and to switch on the first power semiconductor after a second dead time has elapsed. In the sense of a method for controlling the affected half bridges with a series-connected first and second power semiconductors, the current in a line starting from the connection node of the power semiconductors is measured and compared with an upper and a lower threshold value, when the first threshold value is reached, the first one Power semiconductor turned off and the second power semiconductor turned on after a first dead time, and turned off when the lower threshold value of the second power semiconductor and turned on after a second dead time of the first power semiconductor.

Reaching the upper threshold means reaching or exceeding in the sense of a "greater than or equal to" or only exceeding in the sense of a "greater than". Analogously, reaching the lower threshold means reaching or falling below in the sense of "less than or equal to" or only falling below in the sense of "less than". The power flow of the half-bridge can run from the line to the external connections of the power semiconductors or vice versa. The direction of current flow in the line can be directed away from the power semiconductors, which is considered herein as positive current flow, or toward the power semiconductors, which is considered as negative current flow. The device for measuring the current can be provided close to the half bridge in the line. Alternatively, the device can also be arranged in a return line from a load to one of the external connections of the power semiconductors, with which the current in the line is measured despite the other placement. In particular, the inductive load or part of the inductive load can therefore be arranged between the location of the current measurement and the half-bridge. In other words not a fixed switching frequency is selected, the switching eitpunkte _Z defines the power semiconductor, but the circuit of the power semiconductor is made based on the measured current values and threshold values for the current. Thus, for example, leads a change in the load of the half bridge to the fact that the temporal Stromände tion becomes smaller, then extends the time until the current reaches one of the thresholds and switch _Z eitpunkte move further apart. This corresponds to a reduction in the switching frequency. The resulting switching frequency is between 100 kHz and 500 kHz, for example.

This advantageously enables a direct choice of the mean value for the current and a direct choice of the ripple current. The desired average value of the current is implemented by the control within only one period. Especially at high switching frequencies, this can be seen as a P behavior, which simplifies the control enormously. In the case of digital controls, this method also makes it possible to keep the control frequency well below the switching frequency. This would lead to difficulties with the previous methods because there is usually a more complex timing behavior. The method makes it possible to control systems with very high switching frequencies (several 100 kHz up to the megahertz range) even without large computing power, for example with simple and inexpensive microcontrollers. In addition, this process is very robust with changing input and output voltages and thus creates extensive possibilities in system design. Another advantage is that with this half bridge the ripple current can be selected independently of the operating point, which was not possible with previous methods. A particular advantage of the half-bridge according to the invention is that the current remains in the range of the threshold values even when the current behavior changes, for example as a result of load changes, and thus remains at the mean current value which is predetermined as the setpoint value, since the switching behavior of the power semiconductors is determined by the threshold values and adapts the current measurement to the current behavior. The same applies to changes in the default values. For example, if the setpoint for the mean current - and thus the threshold values - is raised, the current will reach the upper threshold value later or the lower threshold value earlier than before, which shifts the switching times of the power semiconductors and raises the mean current value to the new desired value.

It is particularly advantageous that at the high switching frequencies that can now be achieved in a comparatively simple manner, the installation-space-intensive inductive and capacitive components can be reduced in size and thus installation space and in particular installation height can be saved.

Other possible features and measures include:

- The circuit of the micro solar inverter can have a fifth semiconductor switch between the first inductor and the positive pole of the input voltage. Furthermore, the circuit in this case comprises a sixth semiconductor switch or a third diode between the first inductance and the negative pole of the input voltage. Normally, the step-up converter can only generate higher voltages than the input voltage at its output. Due to the fifth and sixth semiconductor switches, it is advantageously possible to represent voltages smaller than the input voltage. If the circuit has the sixth semiconductor switch, both directions of energy flow are supported. If the circuit has the third diode, the energy flow direction is supported from the input voltage side.

- The circuit can comprise a third inductor, which is connected in series in the first series circuit between the first semiconductor switch or the first diode and the second semiconductor switch. This further increases the possible gear ratio for the step-up converter. The first and third inductors are constructed as a common inductor with a center tap for the second semiconductor switch. A common inductance means that the inductors have a common magnetic circuit, that is to say are arranged on a common core.

The circuit can comprise a fourth inductance, which is connected in series in the second series circuit between the third semiconductor switch and the fourth semiconductor switch or the second diode. This further increases the possible gear ratio for the inverse converter. The second and fourth inductors are constructed as a common inductor with a center tap for the third semiconductor switch. As with the first and third inductors, a common inductor means that the inductors have a common magnetic circuit, that is to say they are arranged on a common core.

- The semiconductor switch of the step-up converter and the inverse converter can be operated by the control device in offset timing. This has the effect that the switching frequency of the circuit doubles compared to the switching frequency of the semiconductor switches, for example in the step-up converter. pelt appears. This reduces the size required for the inductances and capacitances of EMC filters, for example at the input of the converter. This makes the components significantly smaller and lighter. Since the size and weight of these components typically have a significant share in the overall size and the total weight of a transducer, the entire transducer thus becomes noticeably smaller and lighter.

- The step-up and the inverse converter can be operated so that their output voltages are the same. Alternatively, they can be operated so that their output voltages are different from each other.

- The controller can include a first and second comparator, to which the measured current is fed as the first input signal, the upper threshold being fed to the first comparator as a second input signal and the lower threshold being fed to the second comparator as the second input signal. The controller can include a digital controller that forwards the upper and lower threshold values to the comparators via a D / A converter (digital-to-analog converter, DAC). The outputs of the comparators can be converted in a modulator to control signals for the power semiconductors. The result is a simple structure, since microcontrollers are now available in which D / A converters, comparators and the modulator are integrated. The method can thus be implemented without additional hardware.

- The controller can calculate the threshold values from specifiable values for the mean value of the current and for the ripple current in the output line. For example, the threshold values from the sum and difference of the mean value and ripple current be calculated. Advantageously, only values relevant for operation have to be specified from outside the control, while the control generates the correct control values therefrom.

- The controller can be configured to use a minimum value for the ripple current. In other words, the control can force that a minimum distance between the upper and lower threshold value is maintained, this minimum distance corresponding to the minimum value for the ripple current. This ensures that the switching frequency resulting from the distance between the threshold values, which increases as the ripple current decreases, does not become too high.

- The controller can use values as the upper and lower threshold values that characterize different current directions. The lower threshold value can be chosen so that it has a different sign than the desired average current. This particularly advantageously allows reloading of the output capacitors of the power semiconductors. This in turn makes it possible to switch the power semiconductors on at low voltage, ideally without voltage. In other words, the ripple current is selected so large that the threshold values assume different signs, that is, they indicate different current directions. Half the amplitude of the ripple current is then greater than the mean current value. It may also be sufficient to use the value 0 A as one of the threshold values. This also enables the output capacities of the power semiconductors to be reloaded, thus enabling voltage-free switching on.

The controller can advantageously use the threshold value, which characterizes a different current direction than the current direction of the mean value for the current, from the summed output capacitor. Calculate the capacitance of the power semiconductors, the inductance in the output line and the voltage at the input and output of the half-bridge.

- The controller can set the dead times so that the power semiconductors are switched on without voltage. This results in a significant reduction in switching losses. Furthermore, a considerable improvement in the EMC properties is achieved, since a resonant switching process takes place. The edges of the switching voltage are significantly flatter and rounded. The spectrum of such a switching voltage shows considerably lower amplitudes in the harmonics.

- The controller can either calculate the dead times or select from a stored table of values. For example, the calculation can be based on the summed output capacitance of the power semiconductors, the inductance in the output line and the voltage at the input and output of the half bridge. Alternatively, the half-bridge can have means for measuring the voltage across the first and second power semiconductors. A circuit can then be based on the measured voltage, which enables safe resonant switching.

- The first and second dead times are expediently different from one another, since the reloading of the capacities of the power semiconductors takes place at different absolute currents and thus takes different times.

Further advantages and features can be found in the following description of exemplary embodiments with reference to the figures. In the figures, the same reference symbols denote the same components and functions. Show it:

Figure 1 is a solar panel with a micro solar inverter in

Top view,

FIG. 2 the side view of the solar panel,

FIG. 3 shows a diagram of the electrical circuit of the micro-solar inverter,

FIGS. 4 and 5 alternative designs for an input stage of the electrical circuit,

FIG. 6 shows another embodiment for the circuit,

FIG. 7 shows a circuit section with a half bridge with a first control circuit,

FIG. 8 shows a circuit diagram and current profile,

9 shows the half-bridge with a second control circuit, FIG. 10 shows the half-bridge with a third control circuit, FIG. 11 shows a simulated switching behavior.

FIG. 1 shows a highly schematic top view of the rear of an exemplary solar panel 1 with a micro solar inverter 2 belonging to the solar panel 1. The micro solar inverter 2 is arranged near a side edge of the solar panel 1. The solar panel 1 is enclosed by a frame 3. FIG. 2 shows a side view of the solar panel 1. The side view shows that the micro solar inverter 2 rests on the back of the solar panel 1. The micro-solar inverter 2 is so flat that it does not protrude from the frame 3. In other words, the height of the micro solar inverter 2 is less than the projection of the frame over the rear of the solar panel 1. For this purpose, the height of the micro solar inverter 2 in this example is 22 mm, with other possible values for the height 24 mm, 20 mm or 19 mm. In the side view it can be seen that the fact that the micro-solar inverter 2 does not protrude beyond the frame 3 means that such a ches solar panel 1 can be enclosed with packaging, the dimensions of which are not influenced by the micro solar inverter 2, but rather the size of which is given only by the frame 3.

In order to realize the low height in comparison to known micro solar inverters, it is necessary to reduce the size required, particularly in the case of passive components, especially inductive and capacitive components. For this purpose, a scarf device in the micro-solar inverter 2 is used in this exemplary embodiment, which is shown in FIG. 3.

The circuit comprises an input stage E, a full bridge V and an output filter. The design of the input stage E corresponds to an interconnection of a step-up converter and an inverse converter, the respective outputs being connected in series. The input stage E has a first and a second input connection 11A, 11B for the input voltage, the first input connection 11A being used as a positive pole. Furthermore, the input stage E has a first and a second output connection 13A, 13B, the first output connection 13A likewise typically representing the positive pole. The input stage E also has three electrical nodes 12A, 12B, 12C, on the basis of which the structure is described.

The first node 12A is connected directly to the second input connection 11B and continues to be connected to ground. A first inductor LI is arranged between the first input connection 11A and the second node 12B. A first semiconductor switch S1 is arranged between the first output terminal 13A and the second node 12B. Between the second node 12B and the first Node 12A is a second semiconductor switch S2 is arranged. Between the first output terminal 13A and the th ers ^¬ node 12A, a first capacitor Cl is arranged, which is the output of the boost converter, which is formed of the first diode Dl, the second semiconductor switch S2 and the first inductor LI. A third semiconductor switch S3 is arranged between the first input connection 11A and the third node 12C. A fourth semiconductor switch S4 is arranged between the second output terminal 13B and the third node 12C. A second inductor L2 is arranged between the third node 12C and the first node 12A. Arranged between the second output connection 13B and the first node 12A is a second capacitor C2, which represents the output of the converter, which is formed from the second diode D2, the third semiconductor switch S3 and the second inductor L2. The semiconductor switches S1 ... 4 in the converter 10 are GaN switches in this example. These enable a particularly high switching frequency, which in turn ensures that passive components can be smaller in size. Other wide bandgap switches can be used in place of the GaN switches. The switching frequency for this

Switch is variable, as described below and is between values of about 100 kHz and about 500 kHz.

In operation of the circuit, the step-up converter generates a positive voltage across the first capacitor CI. This positive voltage is inherently at least as large as the A ^¬ input voltage at the input terminals 11A, 11B. The inverter, in turn, generates a negative voltage at the second output terminal 13B relative to the first node 12A. By connecting the two capacitors CI, C2 in series, the amount of the output voltage between the two output connections 13A, 13B is equal to the sum of the amounts of the two created tensions. Thus, the gear ratio, which results at a given input and output voltage, is halved for the step-up converter and the inverse converter.

The output connections 13A, 13B of the input stage E are connected to the external connections of the full bridge V. The full bridge V comprises four further semiconductor switches S7, S8, S9,

S10. The middle connection of a first half bridge of the full bridge V with the seventh and ninth semiconductor switches S7, S9 is connected to a fifth inductor L5. The middle connection of the second half bridge of the full bridge V with the eighth and tenth semiconductor switches S8, S10 is connected to a sixth inductor L6. The center connections are also connected via a third capacitor C3. The two center connections are also connected to an EMI filter 61. The output of the EMI filter 61 represents that at the output connections 53A, 53B for the circuit. A large capacitance (not shown in the figure) is present at the circuit input in order to draw as little pulsating power as possible from the solar panels.

A control device for the circuit which controls the semiconductor switches S1 ... S8 is not shown in FIG. For the function as an inverter, the first and second semiconductor switches S1, S2, ie the up converter, are controlled with pulse width modulation in such a way that at the output of the step-up converter, ie on the first capacitor CI, the curve of the voltage UC1 takes the form of successive half-waves . The third and fourth semiconductor switches S3, S4, ie the inverse converter, are controlled so that at the output of the inverse converter, ie on the second capacitor C2, the course of the voltage UC2 also takes the form of successive half-waves. The boost converter and the buck-boost converter are thus in Ge contrast to the typical operation as a DC-DC converter is now so be exaggerated, that they each stante at its output just no con ^¬ DC voltage produce. The polarity of the voltage UC2 at the second capacitor is such that, overall, there is an increased amplitude for the voltage profile between the first and second output terminals 13A, 13B. With the same amplitude of the two voltage curves UC1, UC2 to twice the amplitude of the Halbwel ^¬ results in sum le.

The resulting half-wave is applied to the external connections of the full bridge V. The full bridge V will now be controlled in such a ^¬ that the polarity of the half-wave changes with each half-wave and thus a sinusoidal clamping voltage in the ideal case extends across the center terminals of the full bridge V results. To do this, you switch between two switching states. In the first switching state of the eighth and ninth semiconductor ^¬ switches S8, S9 are switched on and off, the seventh and tenth half ^¬ conductor switches S7, S10. In the second switching state, the seventh and tenth semiconductor switches S7, switches S10 been ^¬ and the eighth and ninth semiconductor switch S8, S9 off. The change between these switching states occurs with every half-wave. The frequency of the resulting sinusoidal voltage curve expediently corresponds to the frequency of the supply network, for example 50 Hz. The half-waves are then generated in such a way that they follow one another at 100 Hz and the full bridge V must switch the polarity at 100 Hz, so that two half-waves each result a complete sine wave results. From this it follows that the semiconductor switches S7 ... S10 have to switch with only 100 Hz, so comparatively rarely for converter conditions. Therefore, such switches can be USAGE ^¬ det, which are optimized for low conduction losses in the full bridge advantageous. Since the boost converter 3 is not in a position in the circuit of the figure, a lower voltage than the input voltage clamping ^¬ to generate at its output, which is generated Halbwel le at the first capacitor CI incomplete. In time ranges in which the voltage should actually be lower than the input voltage in line with the half-wave, it still corresponds approximately to the input voltage. The Steue is approximately facility appropriately designed to handle this prob ^¬ lem. For this, the control means being staltet may be, at least in the said time ranges the voltage waveform of the sine wave conductor switch by the circuit of the half ^¬ S7 ... S10 to generate the full-bridge V. For this purpose, the semiconductor switches S7 ... S10 must be switched at high frequency in these time ranges and the voltage form must be set using pulse width modulation. The fifth and sixth inductors L5, L6 and the third capacitor C3 are designed for the necessary filtering of the resulting voltage form even with a high-frequency switching of the full bridge V.

FIGS. 4 and 5 show alternative configurations of the input stage E. The input stage 30 according to FIG. 4 comprises the components of the input stage E according to FIG. 3. In addition, a fourth node 12D is present between the first inductance LI and the first input connection 11A. A fifth semiconductor switch S5 is arranged between the fourth node 12D and the first input terminal 11A. A sixth semiconductor switch S6 is arranged 12A is ^¬ between the fourth node and the first node 12D.

The additional semiconductor switches S5, S6 in conjunction with the components of the step-up converter ensure a grain combination of step-down and step-up converters (Engl, a buck-boost converter) realized. By turning off the sixth semiconductor switch S6 and turning on the fifth semiconductor switch S5, the properties of the step-up converter can be established. If an output voltage is to be generated which is lower than the input voltage, the first semiconductor switch S1 can be switched on and the second semiconductor switch S2 can be switched off and thus only the down converter can be used. Thus, the restriction of the converter according to FIG. 3 with regard to the output voltage is eliminated and all positive DC voltages and waveforms can be generated whose amplitude is not too great.

In an alternative operating mode, the first, second, fifth and sixth semiconductor switches S1, S2, S5, S6 can be switched diagonally. For this purpose, a switch is made between two switching states, the first and sixth semiconductor switches S1, S6 being switched on in the first switching state and the second and fifth semiconductor switches S2, S5 being switched on in the second switching state. In this mode of operation, the step-up converter and the step-down converter therefore act at the same time and not independently of one another.

Another embodiment of the input stage is shown in Figure 5. The design of the input stage 40 according to FIG. 5 is based on the input stage according to FIG. 3. In addition to this, the input stage 40 has a third inductance L3 between the second node 12B and the first semiconductor switch S1. In this example, the first and third inductors LI, L3 are constructed as a common inductor with center tap, to which the second semiconductor switch S2 connects. Furthermore, the input stage 40 has a fourth inductance L4 between the third node 12C and the fourth semiconductor switch S4. The second and fourth inductors L2, L4 are constructed analogously to the first and third inductors LI, L3 in this example as a common inductor with a handle, to which the third semiconductor switch S3 connects. By designing the input stage 40 according to FIG. 5, even higher transmission ratios can be achieved between the output voltage and the input voltage.

FIG. 6 shows, as a further exemplary embodiment for the switching of the micro-solar inverter 2, an inverter 90 which is designed for use in a single-phase, three-wire network (split phase grid). The design of the inverter 90, including the design of the control device, largely corresponds to the design of the circuit according to FIG. 3. In addition, however, the first node 12A is provided as a further input for the EMI filter 61 and is led out of it as a neutral conductor. The other functionality corresponds to the circuit according to FIG. 3.

FIG. 7 shows a greatly simplified section of a circuit 100 with a half bridge 102, which corresponds, for example, to the pair of first and second semiconductor switches S1, S2 and / or the pair of third and fourth semiconductor switches S3, S4 from FIG. 3. The half bridge 102 can also be one of the bridges from the full bridge V. Half-bridge 102 comprises two power semiconductors 108, 110 connected in series, such as MOSFETs. Often, the half bridge 102 is connected with the external connections 104, 106 to a DC voltage 114, for example to the intermediate circuit of a converter. The center connection 112 between the power semiconductors 108, 110 is connected to an inductive load 116. The inductive load 116 represents all types of loads, which can also be only partially inductive, and for structures in which the inductive part of the load comes about, for example, due to a line inductance. The inductive load 116 can therefore be a dedicated component as well as a parasitic element or both together.

The control of the power semiconductors 108, 110 is carried out by a control unit 120. The control unit 120 comprises a digital controller 122, a first and second comparator 124, 126 and a modulator 128. It is possible that these elements are parts of a single microcontroller and are therefore constructed as a single component. Likewise, these elements can also be partially or completely present as separate components. Furthermore, the control unit 120 comprises a current measuring device 130, which detects the current entering or leaving the center connection 112 as a signal 131.

The first comparator receives the signal 131 for the measured current and a first threshold value 132 for the maximum current as input signals. The second comparator also receives the signal 131 for the measured current and a second threshold value 134 for the minimum current as input signals. The threshold values 132, 134 are made available by the controller 122. The controller 122 can calculate this from, for example, default values for the average current and the current ripple. These default values can be predetermined from the outside, for example by a higher-level converter control, or determined by the controller 122 itself. The output signals of the comparators 124, 126 are fed into the modulator 128. The modulator 128 sets these and stored values for dead times to be used. into drive signals for the power semiconductors 108, 110, which are passed on to the respective gate driver.

By comparing the measured current with the threshold values 132, 134 for the maximum and minimum current and

Forwarding into the modulator 128 is achieved that the active power semiconductor 108, 110 is switched off when the maximum current is reached and, after waiting for the dead time to prevent a short circuit in the half bridge 102, the other power semiconductor 108, 110 is switched on. When the minimum current is reached, the active power semiconductor 108, 110 is also switched off and the other power semiconductor 108, 110 is switched on after waiting for the dead time.

A resulting circuit diagram with a switching profile 202 for the upper power semiconductor 108, a switching profile 204 for the lower power semiconductor 110, a voltage profile 206 via the lower power semiconductor 110 is shown together with a resulting simplified current profile 208 in FIG. 8. The dead times 210, 212, which elapse after a respective power semiconductor 108, 110 has been switched off, are greatly extended for better recognition. Figure 8 shows that the resulting current profile is approximately triangular.

If the current profile is flatter at any time, the corresponding threshold value 132, 134 is reached later and the corresponding power semiconductor 108, 110 is switched off only later. The procedure described for the control of the power semiconductors 108, 110 thus does not work with a fixed switching frequency. The instantaneous effective switching frequency rather results from the specifications of the threshold values 132, 134 or the specifications for the middle one Current and the ripple current, the inductance 116 and the voltages 114, 117, which determines the current steepness. The current switching frequency can therefore also fluctuate and can change if the default values are changed.

In the circuit of FIG. 3, such half bridges can be used particularly advantageously if the voltage curve generated is a waveform, for example the sequence of sine half waves. The half bridges then do not generate them in the otherwise customary pulse width modulation with a fixed switching frequency, but continuously adjusted duty cycle. Rather, the mean current value, which matches the instantaneous value of the half waveform, is continuously adjusted. The controller 120 sets upper and lower matching the current average

Threshold values that also vary continuously. The correct voltage results from the circuit of the power semiconductors 108, 110, which in the circuit of FIG. 3 correspond to the pair of first and second semiconductor switches S1, S2 and / or the pair of third and fourth semiconductor switches S3, S4, the circuit follows the threshold values and thus automatically reaches the correct voltage.

FIG. 9 again shows a section of a circuit with the half bridge, but with a modified structure of the control unit 120. In this case, the dead times 210, 212 are no longer permanently stored in the modulator, but rather are specified by the controller 122. The dead times 210, 212 can thus be changed by the controller 122 and adapted to the operating situation. Such an adaptation can be used to reduce the switching losses by allowing a resonant reloading of the output capacitances of the power semiconductors 108, 110. For this purpose, with a positive mean value of the current, the threshold value 134 for the minimum current is set to a negative value, that is to say to a value with a different sign than the mean value and the threshold value 132 for the maximum current. If the mean value of the current is negative, the threshold value 132 for the maximum current is set to a positive value, that is again to a value with a different sign than the mean value and the threshold value 134 for the minimum current.

The values required for reloading can be calculated in sufficient approximation as follows:

Designate:

I _L the lower threshold 134 for the current

L the value of inductance 116 in the output line

Ui the voltage across the two power semiconductors 108, 110, that is, between the upper outer connection 104 of the upper power semiconductor 108 and the lower outer connection 106 of the lower power semiconductor 110

U2 the voltage 117

C the summed output capacitance of the power semiconductors 108, 110, that is

C ⁼ C ₀ SS, S1 + C ₀ SS, S2 and

I _H denotes the upper threshold value 132 for the current

If the term under the root has a value <0, the respective threshold value is set to 0.

The dead times 210, 212 can be determined in various ways by the controller 122. The suitable determination of the dead times 210, 212 enables the power semiconductors 108, 110 to be switched on in a voltage-free manner. On the one hand, the dead times 210, 212 can be calculated or read from a predefined and stored table (look-up).

The following formulas can be used, for example, to calculate the dead times 210, 212 in a sufficient approximation:

Designate:

t _dioi , _min the minimum dead time 210 for the upper power semiconductor 108

L the value of inductance 116 in the output line

U2 the voltage 117

C is the summed output capacitance of the power semiconductors 108, 110

Inscribed:

t _db 2 _{, min} the minimum dead time 212 for the lower power semiconductor 110

Another possibility is to make a structural adjustment, which is shown in Figure 10. 10, the control unit 420 comprises a voltage measuring device 402, 404 for each of the power semiconductors 108, 110. The signals 403, 405 of the voltage measuring devices 402, 404 are fed to a third and fourth comparator 406, 408. A fixed low voltage, for example 1 V, is used as the second input signal for the third and fourth comparators 406, 408. The OFF output signals of the third and fourth comparators 406, 408, the modulator 128 are supplied to and used by this, to be the turn _Z eitpunkt for the respective power semiconductor 108, 110 to use the time at which the clamping voltage over the power semiconductor 108, 110 is low, for example 1 V.

Figure 11 shows the waveform of the voltage 206, current 207, and the turn _Z nits 502a, b for the first and second power semiconductor 108, 110 as a result of a simulation. The switching edges of voltage 206 are clearly flattened. Here, the output capacities are reloaded before the respective power semiconductor 108, 110 is switched on. This means that the device is switched on without voltage. The flatter edges of the switching voltage mean significantly lower amplitudes of the harmonics and thus also ensure better EMC properties of the structure. Since the switching frequency can become very high with very small current ripple values, it is advantageous to implement a minimum value for the current ripple. The controller 122 is designed to implement and maintain this minimum value. This limits the switching frequency to a desired maximum.

Claims

1. Micro solar inverter (2) for converting a DC voltage provided by a solar panel (1) into an alternating voltage, the micro solar inverter (2) being constructed without a transformer and having a height of at most 24 mm.

2. Micro solar inverter (2) according to claim 1, which has a height of at most 20 mm.

3. Micro-solar inverter (2) according to claim 1 or 2 with a galvanically coupled electrical converter for converting the direct voltage present at first connections (11A, 11B) into an output voltage, comprising:

a step-up converter connected on the input side to the first connections (11A, 11B),

- An inverse converter connected on the input side to the first connections (11A, 11B) and

- A series circuit comprising two capacitors (CI, C2) connected to the output-side positive pole (13A) of the step-up converter and the output-side negative pole (13B) of the inverse converter, the output-side negative pole of the step-up converter and the output-side positive pole of the inverse converter with the center connection ( 12A) are connected between the capacitors (CI, C2).

4. micro-solar inverter (2) according to claim 3, wherein the up converter comprises a first series circuit of a first semiconductor switch (Sl) or a first diode with a two-th semiconductor switch (S2), the outer connections of which form the output-side poles of the step-up converter and a first inductance (LI), which is connected to the center connection (12B) of the first series circuit and the positive pole (11A) of the input voltage.

5. Micro-solar inverter (2) according to claim 4, wherein the converter comprises a second series circuit of a third semiconductor switch (S3) with a fourth semiconductor switch (S4) or a second diode, of which an external connection is the output-side negative pole (13B ) of the inverse wall ^¬ coupler forms and the other external connection to the positive terminal (11A) of the input voltage is connected to the buck-boost converter further comprises a second inductor (L2) connected to said center terminal (12C) of the second series circuit as the medium connection (12A ) is connected between the capacitors (CI, C2).

6. Micro solar inverter (2) according to claim 4 or 5, in which at least part of the first to fourth semiconductor switches (S1 ... 4) are designed as gallium nitride switches, in particular as self-locking gallium nitride switches or as cascode with a self-conducting gallium nitride switch.

7. Micro solar inverter (2) according to claim 6, in such a way that the switching frequency for the gallium nitride switch is a frequency of at least 200 kHz, in particular at least 500 kHz, at least 1 MHz is used in a special embodiment.

8. Micro solar inverter (2) according to one of claims 4 to 7, wherein the first and / or second inductor (LI, L2) are circuit board inductors.

9. Micro solar inverter (2) according to one of claims 3 to 8 with a full bridge (V), the input side of which is connected to the ^¬ output-side poles (13A, 13B) of upward and inverse converter.

10. micro-solar inverter (2) according to claim 9, designed such that the power semiconductors (S7 ... 10) of the full bridge (V) are operated at least in part of the operating time as a pole reverser.

11. Micro-solar inverter (2) according to one of the preceding claims, in which at least part of the half-bridges (102) comprise:

- A series-connected first and second semiconductor switch (S1 ... 4, S7 ... 10, 108, 110),

a controller (120) for the semiconductor switches (S1 ... 4, S7 ... 10, 108, 110),

- A line that starts from the connection node (112) of the semiconductor switches (S1 ... 4, S7 ... 10, 108, 110),

- A device (130) for measuring the current in the line,

the controller (120) being designed,

- compare the current with an upper and a lower threshold value (132, 134),

- When the upper threshold value (132) is reached, the first power semiconductor (108) is switched off and the second power semiconductor (110) is switched on after a first dead time, and

- When the lower threshold value (134) is reached, switch off the second power semiconductor (110) and switch on the first power semiconductor (108) after a second dead time.

12. Solar panel (1) combines with a panel surface, the solar cells to ^¬ and the panel surface enclosing frame (3) and, arranged on the panel surface micro-solar inverter (2) according to one of the preceding claims, wherein the micro solar inverter (2) does not protrude the frame (3).