EP3824604A1 - Apparatus for buffered transmission of data - Google Patents
Apparatus for buffered transmission of dataInfo
- Publication number
- EP3824604A1 EP3824604A1 EP19770169.1A EP19770169A EP3824604A1 EP 3824604 A1 EP3824604 A1 EP 3824604A1 EP 19770169 A EP19770169 A EP 19770169A EP 3824604 A1 EP3824604 A1 EP 3824604A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- data packet
- buffer
- data
- valid
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 title description 6
- 239000000872 buffer Substances 0.000 claims abstract description 152
- 238000000034 method Methods 0.000 claims description 33
- 238000004891 communication Methods 0.000 description 4
- 230000001960 triggered effect Effects 0.000 description 2
- 239000011647 vitamin D3 Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/6245—Modifications to standard FIFO or LIFO
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9084—Reactions to storage capacity overflow
- H04L49/9089—Reactions to storage capacity overflow replacing packets in a storage arrangement, e.g. pushout
- H04L49/9094—Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/56—Queue scheduling implementing delay-aware scheduling
- H04L47/564—Attaching a deadline to packets, e.g. earliest due date first
Definitions
- the present invention relates to a device for buffered transmission of data.
- the present invention relates to a device with two data buffers (hereinafter referred to as buffers) and control logic which controls write and read accesses to the buffers.
- Devices for buffered transmission of data are known from the prior art, which have three buffers. Said devices have a buffer for writing data and a buffer for reading data, while the third buffer is used to transfer the data between the ports.
- the invention enriches the prior art, as devices and methods according to the invention enable a transmission between a transmitter and a receiver, in which only two buffers are required, the transmitter nevertheless being able to write data into the device at any time.
- a device comprises a data input, a data output, a first buffer, a second buffer, and a control logic, wherein the control logic is set up, data packets that are received via the data input in the first buffer or to direct the second buffer and to mark them as valid or invalid, and to provide data packets which are to be output via the data output from the first buffer or the second buffer, the control logic also being set up to provide a data packet which is to be output via the data output to make available from the first buffer if the data packet at the time of a start of reading out is written into the first buffer to provide the data packet from the second buffer if the data packet is written into the second buffer at the time of the start of the readout and to provide the data packet from the buffer which has the latest valid data packet if at the start of the readout no data packet is written into the buffer.
- the term "data input” as used in the description and the claims is to be understood in particular as a communication link via which data can be transmitted to the device.
- the communication connection can be, for example, an electrically conductive connection, by means of which current and / or voltage levels representing data can be supplied to the device.
- data output as used in the description and the claims is to be understood in particular as a communication connection via which data can be output by the device.
- the communication link can be an electrically conductive connection, for example, by means of which the device can output current and / or voltage levels representing data.
- buffer as used in the description and the claims is to be understood in particular as a memory element (component) or an addressable area in a memory element (component). This means that a distinction between buffers is based both on a logical distinction, for example with regard to addressable areas in a memory element (component, for example “DP-RAM Page 1, DP-RAM Page 2”), and on a distinction can refer to the storage elements (components) involved.
- control logic is to be understood in particular to mean a circuit which is set up on the basis of an analysis of the state of the device or of the read and read data supplied to the device / or read / write requests to control the device and in particular to choose from which buffer a data packet is to be made available and into which buffer a data packet is to be written.
- data packet as used in the description and the claims, is to be understood in particular as binary-coded information which is transmitted / received in a block, the information typically having a context.
- a data packet often has a fixed structure which enables binary-coded information to be assigned a corresponding section of the data packet.
- start of reading is to be understood in particular as a point in time immediately before the output of a first bit of a data packet to be provided.
- the point in time can be calculated, for example, by subtracting from the point in time at which a first bit is actually output the time required by the control logic to decide from which buffer the data packet is to be provided.
- invalid and “invalid” as used in the description and the claims relate in particular to the correctness of data packets (or to the correctness of the data packet content).
- An incorrect data packet is, for example, a data packet in which a write error was made when writing to the buffer (and thus the form and / or content of it incorrectly deviates from an advised data packet), or a data packet that is correct in the Buffer was written but contains incorrect information (due to a previous error).
- a device thus enables a continuous flow of data from the transmitter (data generator) to the receiver (data consumer) by alternately writing data packets into the two buffers and making them available from the two buffers.
- the device can be used, for example, as a 2-buffer FIFO in automation technology and implemented there in a transceiver.
- the transceiver can be used, for example, for the forwarding of process data from a field bus to a local bus (for example in a bus coupler or a bus controller).
- the process data can be written in the 2-buffer FIFO in the form of data packets / data blocks (fixed length).
- the control logic can monitor that the data corresponds exactly to a previously configured data block length.
- the data can be identified by the transmitter as “valid” or “invalid”.
- the sender can declare the data invalid while writing. With a "valid" signal, on the other hand, the sender can announce that the data provided is valid.
- the receiver can also be supplied with data from the other buffer in order to receive the last valid data. It is also possible to provide a data packet while the data packet is being written into the buffer.
- the control logic is preferably set up to mark a data packet as invalid if, while the data packet is being provided from one of the buffers, a data packet is started to be written into one of the buffers.
- control logic is set up to mark a data packet as invalid if, while a data packet is provided from a buffer, a part of the data packet that is still to be read is overwritten.
- control logic is set up to generate a read error signal when a data packet is read out, which is identified as invalid during or after the writing of the data packet.
- the transmission of invalid or out-of-date data packets can thus be avoided.
- the read error signal thus indicates whether a currently read data packet is valid or not.
- control logic is set up to provide the data packet, which is to be output via the data output, from the buffer that was last described when no data packet is written into the address areas at the start of the reading and in the buffer described last written data packet is marked as valid.
- control logic is set up to provide the same latest valid data packet until a newer, valid data packet is available.
- the last valid data can thus be output (or read) several times until newer valid data is written to the FIFO. This can ensure that the recipient can be continuously supplied with data that is valid (if there is no error).
- control logic is preferably set up to generate an overflow signal when a valid data packet is overwritten without having been read out.
- the control logic is preferably set up to generate an underflow signal if a valid data packet is read out several times.
- the device can be in a system (for example
- Automation system that integrates a transmitter (e.g. a sensor) and has a receiver (for example a central control unit) in order to provide a continuous stream of data packets transmitted by the transmitter, buffered.
- a transmitter e.g. a sensor
- a receiver for example a central control unit
- the transmitter is set up to read back a data packet from the buffer that has the latest valid data packet and to write it back into the device if the transmitter does not have a more current valid data packet, but is set up to do so at certain times Write data packet into the device.
- a method for transmitting data packets from a transmitter to a receiver by means of a device with a first buffer and a second buffer and a control logic comprises writing data packets into the first buffer or the second buffer and labeling the data packets as valid or invalid, and reading a data packet from the first buffer if the data packet is written into the first buffer at the time of a start of reading out, and reading out the data packet from the second buffer if the data packet is started at the time of reading out is written into the second buffer, and the data packet is read out of the buffer which has the latest valid data packet if no data packet is written into the buffers at the start of the reading.
- the method further comprises generating a read error signal if, while a data packet is being read from one of the buffers, a data packet is started to be written into one of the buffers.
- the method further comprises generating a read error signal when a data packet is read out, which is identified as invalid during or after the writing of the data packet.
- the method preferably further comprises generating an overflow signal (“overflow signal”) if a valid data packet is overwritten without having been read out.
- the method preferably furthermore comprises generating an underflow signal (“underflow signal”) when a valid data packet is read out several times.
- the method preferably further comprises generating an empty signal if no buffer has a valid data packet.
- the method further comprises reading back, by the transmitter, a data packet and rewriting the read back data packet into a buffer if the transmitter does not have a more current valid data packet, but is set up to transmit a data packet at certain times Device to write.
- FIG. 1 shows a device according to the invention in accordance with an embodiment
- FIG. 2 illustrates a state of the device shown in FIG. 1, in which neither write nor read access takes place
- FIG. 3 illustrates a state of the device shown in FIG. 1 in which there is no write but read access
- FIG. 4 illustrates a state of the device shown in FIG. 1, in which write and read access take place
- FIG. 5 illustrates a state of the device shown in FIG. 1 in which a read-back access takes place
- FIG. 6 illustrates a state of the device shown in FIG. 1 in which write and read-back access take place; 7-24 illustrate exemplary sequences of write and read accesses; and
- 25 shows a flowchart of a method for transmitting data packets from a transmitter to a receiver.
- the device 10 comprises a data input 12 and a data output 14. Via the data input 12, the device 10 is connected to a transmitter 16 (data producer). The transmitter 16 generates data packets at regular intervals, which are to be transmitted to a receiver 18 (data consumers). The receiver 18 is connected to the data output 14 of the device 10 and requests data packets at regular intervals, or reads data packets from the device 10 at regular intervals.
- a transmitter 16 data producer
- the transmitter 16 generates data packets at regular intervals, which are to be transmitted to a receiver 18 (data consumers).
- the receiver 18 is connected to the data output 14 of the device 10 and requests data packets at regular intervals, or reads data packets from the device 10 at regular intervals.
- the device 10 further comprises a first buffer 20, a second buffer 22 and a control logic 24.
- the control logic 24 is set up to receive data packets via the data input 12 in the first buffer 20 or the second To direct buffer 22.
- the control logic 24 can establish a data connection between the data input 12 and the first buffer 20 or a data connection between the data input 12 and the second buffer 22 by means of a first switch 26.
- first switch 26 Depending on the position of the first switch 26, data packets received via the data input 12 are thus written into the first buffer 20 or into the second buffer 22.
- the control logic 24 is also set up to mark data packets written in the first buffer 20 or the second buffer 22 as valid (invalid) or as invalid (invalid). Marking a data packet as valid or invalid can be based on a signal from transmitter 16, for example when transmitter 16 signals that a data packet is faulty.
- the transmitter 16 can be connected to the control logic 24 via a first control line 28 and can indicate to the control logic 24 during the writing of a data packet or after the writing of the data packet whether the data packet or the written part of the data packet is valid or are invalid.
- the transmitter 16 can also announce a write access to the device 10 to the control logic 24 via the first control line 28 or indicate completion of a write access.
- the control logic 24 is also set up to provide data packets that are to be output via the data output from the first buffer 20 or the second buffer 22.
- the control logic 24 can establish a data connection between the first buffer 20 and the data output 14 or a data connection between the second buffer 22 and the data output 14 via a second changeover switch 30.
- data packets output via the data output 14 are read out of the first buffer 20 or the second buffer 22.
- the same data packet can be provided several times in succession, as long as no newer (valid) data packet is written into the device 10.
- the receiver 18 can be connected to the control logic 24 via a second control line 32.
- the control logic 24 can indicate to the receiver 18 during the reading out of a data packet or after the reading out of the data packet has ended whether the data packet or the part of the data packet read out is valid or invalid.
- the receiver 18 can also announce a read access to the device 10 to the control logic 24 via the second control line 32 or indicate completion of a read access.
- the control logic 24 can also track which buffer 20, 22 is described with a valid data packet and how old the data packets stored in the buffers 20, 22 are. 2 illustrates a state of the device 10 shown in FIG. 1, in which neither write nor read access takes place.
- the first buffer 20 comprises a first data packet and the second buffer 22 a second data packet.
- the control logic 24 determines which of the data packets is valid. If only one of the data packets is valid, the device 10 makes this data packet available to the receiver 18. If both data packets are valid, the device 10 provides the receiver 18 with the newer of the two valid data packets (ie the data packet with the newer time stamp ti> to). If both data packets were invalid, this would be signaled to the receiver 18 or neither of the two data packets would be provided to the receiver 18.
- the device 10 If, as shown in FIG. 3, a request is made by the receiver 18 and no new data packet is written into the device 10 at the time of reading, the device 10 provides the receiver 18 with the latest valid data packet (ie the data packet with the newer time stamp ti> to) ready. If, on the other hand, as shown in FIG. 4, a data packet which has a newer time stamp t2> ti is written into the device 10 at the time of the request by the receiver 18, this is made available to the receiver 18. The provision can be canceled if the data packet written in the first buffer 20 is identified as invalid. The data packet written in the first buffer 20 can also be identified as invalid if the receiver 18 overtakes the sender 16 when reading a data packet when the data packet is written and there is therefore a risk that the receiver 18 will be provided with an inconsistent data packet.
- the control logic 24 is thus set up to provide a data packet, which is to be output via the data output 14, from the first buffer 20 if the data packet is written into the first buffer 20 and the data packet is written out at the time of reading start to be provided to the second buffer 22 if the data packet is written into the second buffer 22 at the time of the start of the readout. If there is no data packet in at the start of reading If the buffers 20, 22 are written, the data packet is made available from the buffer 20, 22 which has the latest valid data packet.
- the read data packet can be marked as invalid. If the data packet read out is identified as invalid, the readout process can be terminated and the receiver 18 (immediately or at a next readout time) read out the (now latest) data packet from the respective other buffer 20, 22. Alternatively, the receiver 18 can continue the readout process and discard the read data packet.
- control logic 24 can also mark the data packet as outdated, whereby the receiver 18 can be informed that the data packet is valid but outdated. The receiver 18 can then abort the reading of the data packet, which is now marked as obsolete, and (immediately or at a next reading time) read the (newer) data packet from the respective other buffer 20, 22. Instead of canceling the reading out, the receiver 18 can also completely read out a data packet marked (as invalid and / or outdated) and reject the read data packet or forward it marked as invalid. This can be indicated, for example, if aborting the reading would produce a reading error that would have to be overcome by clearing the buffers 20, 22.
- a data packet can be read back by the transmitter 16 from a buffer 20, 22.
- the transmitter 16 can extract information from the read back data packet and transfer this information into a data packet to be written into the device 10 (or replace information in the data packet with the extracted information).
- information for example, a value, such as a measured value
- the read-back can be done while reading the Buffers 20, 22 take place as well if no data packet is read out of the buffer 20, 22.
- the transmitter 16 can read back a data packet from one buffer 20, 22, while the transmitter 16 writes a data packet into the other buffer 20, 22.
- any buffer 20, 22 (preferably the one described with the latest valid data packet) can also be read out by the receiver 18.
- FIG. 7 illustrates an exemplary sequence of write and read accesses in the device 10.
- Fig. 9 illustrates an exemplary sequence of writing
- Fig. 10 illustrates an exemplary sequence of writing
- Fig. 11 illustrates an exemplary sequence of write and read accesses in which write and read accesses overlap, thereby reducing transmission latency. If the transmitter 16 identifies a data packet as invalid, the receiver 18 can abort the reading of the data packet or, as shown in FIG. 11, continue the reading and reject the read data packet. For this purpose, the receiver 18 can continuously evaluate the validity signal and discard a data packet if the validity signal signals an invalid data packet while the data packet is being read out.
- FIG. 12 illustrates an exemplary sequence of write and read accesses, in which a write process begins during a read process.
- the validity signal is set to “invalid”, so that the receiver 18 cancels the read process or discards the data packet read out.
- Figure 13 illustrates an exemplary sequence of write
- Read accesses which differs from the sequence shown in FIG. 12 in that the data packet is identified by the transmitter 16 as invalid. This makes the first one again in the subsequent reading process
- Read accesses in which a write and a read access are started in the same clock cycle ("clock cycle").
- the validity signal is set to "invalid", so that the receiver 18 cancels the reading process or discards the data packet read out.
- Read accesses in which a read access is slower than a parallel write access so that the transmitter 16 begins to write a new data packet, while the receiver reads out an older data packet, so that it is now out of date.
- the validity signal is set to "invalid", so that the receiver 18 cancels the readout process, discards the read data packet or forwards it as marked as outdated.
- Read accesses which differs from the sequence shown in FIG. 16 in that the data packet is identified by the transmitter 16 as invalid. As a result, the first data packet is read out again in the subsequent reading process.
- the receiver 18 illustrates an exemplary sequence of write and read accesses in which a read access to empty buffers 20, 22 takes place. Since the validity signal is set to "invalid", the receiver 18 recognizes that the data packet read out is to be discarded. After a first data packet has been written into a buffer 20, 22 by the transmitter 16, the device 10 signals that it is no longer empty and that a valid data packet can be provided.
- FIG. 19 illustrates an exemplary sequence of write and read accesses, which differs from the sequence shown in FIG. 18 in that the first data packet is identified by the transmitter 16 as invalid.
- the validity signal is therefore set to “invalid”, so that the receiver 18 cancels the reading process or discards the data packet read out.
- Figure 20 illustrates an exemplary sequence of write and read accesses that trigger an overflow signal.
- a valid data packet is written into a buffer 20, 22 before a valid data packet written previously in the device 10 has been read out.
- the overflow can, as indicated in Fig. 20, the transmitter 16 and the receiver 18 to different Times are signaled, for example, the transmitter 16 when starting to write the valid data packet and the receiver 18 when reading the valid
- Figure 21 illustrates an exemplary sequence of write
- Read accesses which differs from the sequence shown in FIG. 20 in that the receiver 18 tries to read out the data packet, but the readout attempt fails. In this case, no overflow signal is triggered, although the data packet cannot be read out successfully.
- Fig. 22 illustrates an exemplary sequence of write
- Read accesses which differs from the sequence shown in FIG. 20 in that a data packet is written into the device, but is marked as invalid, so that the lack of read access does not cause a validly written data packet to be overwritten.
- Figure 23 illustrates an exemplary sequence of write
- Read accesses that trigger an underflow signal The same valid data packet is read out twice. As illustrated in FIG. 24, the underflow signal is also triggered when the second readout of the same valid data packet is interrupted or the previously valid data packet is deprecated during the readout and is thus identified as invalid.
- step 34 data packets are written into the buffers 20, 22 and identified as valid or invalid. If the data packet is written into one of the buffers 20, 22 at the time of reading out a data packet, the data packet is read out of the respective buffers 20, 22 in step 36 or 38. However, if no data packet is written into one of the buffers 20, 22 at the time of reading out, the data packet is read out from the buffer 20, 22 which has the latest valid data packet. As a result, the transmitter 16 can write data into the device 10 at any time and the receiver 18 can read out data from the device 10 at any time.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Communication Control (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102018005618.0A DE102018005618B4 (en) | 2018-07-17 | 2018-07-17 | Device for the buffered transmission of data |
PCT/IB2019/055289 WO2020016681A1 (en) | 2018-07-17 | 2019-06-24 | Apparatus for buffered transmission of data |
Publications (1)
Publication Number | Publication Date |
---|---|
EP3824604A1 true EP3824604A1 (en) | 2021-05-26 |
Family
ID=67997651
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19770169.1A Pending EP3824604A1 (en) | 2018-07-17 | 2019-06-24 | Apparatus for buffered transmission of data |
Country Status (5)
Country | Link |
---|---|
US (1) | US11570121B2 (en) |
EP (1) | EP3824604A1 (en) |
CN (1) | CN112352403B (en) |
DE (1) | DE102018005618B4 (en) |
WO (1) | WO2020016681A1 (en) |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7568066B2 (en) * | 2006-09-26 | 2009-07-28 | Arcadyan Technology Corporation | Reset system for buffer and method thereof |
US8094952B2 (en) * | 2007-09-19 | 2012-01-10 | Ricoh Company, Ltd. | Image processing apparatus and image processing method |
CN102640462B (en) * | 2009-11-11 | 2015-12-09 | 新思科技有限公司 | Integrated circuit for Buffering Service request is arranged |
JP2011150684A (en) * | 2009-12-21 | 2011-08-04 | Sony Corp | Cache memory and cache memory control device |
JP5583563B2 (en) | 2010-12-06 | 2014-09-03 | オリンパス株式会社 | Data processing device |
US9641464B2 (en) * | 2012-04-30 | 2017-05-02 | Nxp Usa, Inc. | FIFO buffer system providing same clock cycle response to pop commands |
JP2014191622A (en) * | 2013-03-27 | 2014-10-06 | Fujitsu Ltd | Processor |
US9524242B2 (en) * | 2014-01-28 | 2016-12-20 | Stmicroelectronics International N.V. | Cache memory system with simultaneous read-write in single cycle |
EP3169002B1 (en) * | 2015-11-13 | 2019-01-02 | Airbus Operations GmbH | Method for transmitting prioritized data and a transmitter |
US10216656B2 (en) * | 2016-09-27 | 2019-02-26 | International Business Machines Corporation | Cut-through buffer with variable frequencies |
US20180176144A1 (en) * | 2016-12-19 | 2018-06-21 | Futurewei Technologies, Inc. | APPARATUS FOR SELF-REGULATER (SR) LAST-IN, FIRST-OUT (LIFO) SCHEDULING IN SOFTWARE DEFINED NETWORKS (SNDs) WITH HYBRID TRAFFIC |
US10248330B2 (en) * | 2017-05-30 | 2019-04-02 | Seagate Technology Llc | Data storage device with buffer tenure management |
-
2018
- 2018-07-17 DE DE102018005618.0A patent/DE102018005618B4/en active Active
-
2019
- 2019-06-24 EP EP19770169.1A patent/EP3824604A1/en active Pending
- 2019-06-24 WO PCT/IB2019/055289 patent/WO2020016681A1/en unknown
- 2019-06-24 CN CN201980039855.6A patent/CN112352403B/en active Active
-
2021
- 2021-01-19 US US17/152,309 patent/US11570121B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20210144100A1 (en) | 2021-05-13 |
WO2020016681A1 (en) | 2020-01-23 |
US11570121B2 (en) | 2023-01-31 |
CN112352403A (en) | 2021-02-09 |
DE102018005618A1 (en) | 2020-01-23 |
DE102018005618B4 (en) | 2021-10-14 |
CN112352403B (en) | 2023-12-19 |
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