DE2922597A1 - CACHE STORAGE AND METHOD FOR OPERATING A DATA PROCESSING SYSTEM - Google Patents

Description

BLUMBACH. WESER. BERGEN ". KRAMER ZWIRNER · BREHM

PATENT LAWYERS IN MUNICH AND WIESBADEN 2 ^ 22 ^ 9 7

-4-

Palenlconsull RadedcestraOe 43 8000 Munich 60 Telephone (089) 883603/883604 Telex 05-212313 Telegrams Patentconsult Patenlconsull Sonnenberger Straße 43 6200 Wiesbaden Telephone (06121) 562943/561998 Telex 04-186237 Telegrams Patentconsult

Western Electric Company Incorporated Chang, S.J.

Broadway, New York NY 10038, USA ¹ " ^19th

Cache Storage and Method of Operation a data processing system

The invention relates to cache memories for a data processing system with a device for storing data words, an addressable identifier for each Data word and an indication of the validity or invalidity of each word and a method of operation a data processing system with a processor, a main memory and a cache memory, wherein in the cache memory data words required by the processor, an addressable identification for each data word and an indication of the validity or invalidity of each word is stored.

Munich: R. Kremer Dipl.-Ing. · W. Weser Dipl.-Phys. Dr. rer. nat. . H.P.Brehro Dipl.-Chem. Dr. phil. nat. Wiesbaden: P. G. Blumbach Dipl.-Ing. · P. Bergen Dipl.-Ing. Dr. jur. · G. Zwirner Dipl.-Ing. Dipl.-W.-Ing.

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In order to reduce the effective memory access time with reasonable effort, there are systems according to the state of the art known to have a processor, high capacity, low speed main memory (with reference to the Working speed of the processor) and a cache memory of small capacity and high speed, comparable with the operating speed of the processor. Information required by the processor is taken from read from main memory, made available to the processor and written to cache memory. 'If the processor If the same information is needed again, it is read directly from the cache memory to reduce the processing delay to avoid that occurs when reading the main memory. When the cache memory is full and the Processor needs information that is not stored in the cache memory, so the desired information must be taken from the Main memory recovered and a memory location identified in the cache memory to store this new information to save. A satisfactory cache location for receiving new information is provided by one of several , commonly used replacement methods are identified, for example by a random replacement or replacement of the information that has not been used for the longest time. The replacement of information in the cache memory creates new information in this memory ready for use by the processor. *

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In data processing systems, to reduce the required storage space and to simplify the Coding or programming that uses system subroutines. However, this can cause time delays cause there return addresses and the contents of processor registers must be saved when entering a subroutine, so that when returning from. the subroutine processing can be resumed. In many data processing systems, subroutines do a variety of main memory writes and reads, which creates inequality delays between the memory access time and the processor cycle time. In data processing systems that have a cache memory the delay is reduced by the fact that the information required for subroutine operations processed via the cache memory.

Subroutine information required to start normal processing when returning from a subroutine are only required once, namely when returning from the subroutine. If a cache memory for inclusion is used by subroutine information, the subroutine information that the processor receives from the Cache memory has been read, is not needed again, but remains in the cache memory until it is used by the respective Replacement procedure is removed. Accordingly, the operation is

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of cache memory is not as efficient as possible.

The invention has set itself the task of solving these difficulties to eliminate. For this purpose, it is based on a cache memory of the type mentioned at the beginning and is identified by an arrangement which, when addressing the memory with an identifier in response to that Identification is stored, as well as an indication that the corresponding data word is valid, and a read signal an indication of invalidity with reference to the data word saves.

For the aforementioned method for operating a data processing system the invention is characterized in that when addressing the cache memory with one in it stored identification and, if the corresponding data word is valid, a read operation causes a Invalidity indication for this data word is saved. This immediately becomes a storage location in the cache memory to receive new information read from main memory, and it is not necessary to that useless information, for example previously read Subroutine information, by repeatedly using the replacement procedure from the cache memory removed.

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Another feature of a preferred embodiment of the invention is a read operation so formed is that useless information read from main memory is not written into cache memory. If a requested data word is not in the cache memory is stored (this is called cache "miss") and therefore has to be read from the main memory, the read data word is passed to the processor, but not to the Written in cache memory.

Another feature of the preferred embodiment of the invention is that two write operations for Hereinafter referred to as normal writing and special writing are available. With a normal A data word is written directly into the main memory, but not into the cache memory. The cache memory however, it is queried. If a cache hit occurs, either the data word can be updated brought or removed from the cache memory in that the validity bit of the cache memory location that led to the hit must be set to the invalid state (whether the data word is up to date brought in or removed depends on the user's choice). A Data location is written to both cache memory and main memory.

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The following is the preferred embodiment of FIG Invention described with reference to the drawings. 1 shows the block diagram of a data processing system;

Figures 2 through 5 are a detailed block diagram of a cache memory according to the invention according to Figure 1; Fig. Β the assignment of Figs. 2-5.

The cache memory 102 in FIG. 1 takes a subset of the in the main memory 103 stored data words, so that processor 101 has quick access to this subset of data words. Those stored in cache memory 102 Data words are located in the data memory 107 and are based on of a directory identified as Tag Store 106 is designated. The storage locations of the tag store 106 correspond to the storage locations of the data store 107 and take on address labels (tags) for identifying the data words in the data memory 107. Any location of the label memory contains a valid bit to enable the. current status of the data word in the corresponding Specify the storage location of the data memory. A valid validity bit (state H or logical 1) indicates that the corresponding data word in data memory 107 is valid is. On the other hand, an invalid validity bit (state L or logic 0) indicates that the corresponding data word is invalid and cannot be used by processor 101.

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A cache memory is referred to as purely associative, when each main memory data word can be stored in any memory location in the cache memory. In one associative cache memory, each stored address tag must be checked to see if a specified Word is stored in the cache memory. A cache memory is said to be group associative if any given Main memory data word can only be stored in a subset of storage locations of the cache memory. A group-associative cache memory reduces the circuit complexity and / or that for performing a cache operation required time, since only the appropriate subset of address labels needs to be checked to determine whether a specified data word is in the cache memory. The cache memory 102 of the embodiment of the invention is group-associative and has a group size equal to 4 (see Fig. 2-5). It should be noted that any group size could be used and that the invention in can be applied in the same way to a data processing system that uses a purely associative cache memory.

The processor 101 addresses the memory system with the main memory 103 and the cache memory 102 by providing the main memory address of a desired data word. The main memory address is for the cache memory operation divided into two groups of address bits. the

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Low-digit address bits (ADDR) address storage locations in label memory 106 and in data memory 107 over lines 108. The high-order address bits serve as the address tags (AT) stored in tag memory 106 for identification of data words stored in the data memory 107 are stored, and are the label memory 106 and a hit display circuit 116 via the line ■ lines 109 supplied. The tag memory control circuit generates the valid bits and controls the read and write operations of the tag memory 106, the data memory control circuit 111 controls the read and write operations of the data memory 107. These control circuits will be described in detail below.

In order to determine whether the desired data word is stored in the cache memory, the subgroup of 4 address labels, which could possibly identify the desired data word, read from the label memory 106 and used Hit indicator circuit 116 given. There they are compared with the address labels of the desired data word. If there is a match between any of the from the label memory 106 read address labels and that of the processor on the line 109 supplied address label of the desired data word is present and also from the Address label read from the address memory also contains a valid valid bit, then a hit signal is generated. In the other case, a false signal is generated. The meeting

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fer / error signal is sent via line 117 to processor 101, to data memory control circuit 111 and to tag memory control circuit 110 transmitted.

The replacement circuit 113 takes the from the tag memory 106 read valid bits to select a cache location in which a new one is currently not data word stored in the cache memory is to be stored. If any of the data words in the subgroup of Data storage locations which correspond to the new data word is marked as invalid in the label memory 106, then one of those memory locations which contain an invalid data word is preferably selected. If all 4 memory locations, • which are available to accept the new data word contain valid data, then one of these memories will be set up sooner random basis selected for replacement. The way of working the replacement circuit 113 will be described in detail later.

The processor 101 issues 4 different instructions to the cache memory 102, namely normal reading, special reading, normal writing and special writing. The commands can come from processors are generated of a known type, for example by a microcode on the basis of predetermined program instructions, which processor 101 executes. The read / write signal (R / W,

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State L or logic 0 for writing and state H or Dogisch 1 for reading) and the special signal (SPL, state L or logic 0 for special and state H or logic 1 for normal) "the cache memory 102 over the line

105 or 119 supplied. In the case of write operations, the processor 101 supplies data words on the data bus 112, and for write operations the processor accepts data words on the data bus 112. At the beginning the processor creates the command signals, the address signals and data signals (if necessary) and then activates the signal Cache-GO (CAGO, active in state L or logical 0). The Cache-GO signal is fed to a sequence circuit 115 via the line. The sequential circuit 115 provides timing pulses necessary for cache memory operations are required and will be described in more detail later.

Figures 2 through 5 form a detailed block diagram of the group associative cache memory 102. The tag memory

106 has 4 independent but identical label storage modules 201, 202, 203, 204. The data memory has accordingly

107 4 independent but identical data storage modules 410, 411, 412, 4.13, which correspond to the label memory modules. All of the tag storage and data storage modules are connected simultaneously over lines 108 with the low-order address bits addressed to the main memory address. When a data

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Word is stored in the data memory 107, it is located in one of the data memory modules at an address which is the same is the low-order address bits of the main memory address for the data word. In addition, if a data word in is stored in one of the data memory modules, the data word address label (the high-order bits of the main memory address for the data word) are stored in the corresponding address memory module in order to display this. Each address memory module location also contains a validity bit, which shows the status of the corresponding stored in the data storage module Data word, i.e. whether the data word is valid and can be used by the processor or is invalid. Accordingly The first step in a cache operation is to read the tag memory modules to see if the desired data word is stored in the cache memory.

During the initial phase of the cache memory cycle, the tag memory modules are read by the sequencer 115 based on the timing signal T. The address labels, which are read from the label memory modules at the address supplied by the processor 101 on the lines 108, are fed to the associated comparison circuits 301, 302, 303, 304, which are part of the hit display circuit 116 the lines 109 is supplied, the other input signal to the comparison circuits 301 to 304. If the from a label memory

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module read address label with the address label on the Lines 109 match, then the respective comparison circuit outputs a signal H from its output terminal an associated NAND gate of the NAND gates 305, 306, 307 and 308. The valid bits read from the tag memory modules are also fed to NAND gates 305-308. If a comparison circuit supplies a signal H, indicating that a match has occurred and when the associated valid bit is also an H signal which indicates that the stored data word is valid, then the relevant NAND gate signals the NAND gate 305 to 308 a hit by emitting a signal L at its output terminal. The signals of the NAND gates 305 to

308 are stored in a buffer 309 and inverted, so that the contents of the tag storage modules can be changed while retaining the hit or misinformation will. The Q outputs of the bistable buffer

309 follow their corresponding data inputs D for so long the signal at the actuation connection G is high. When the signal at the actuation connection goes to L, then the signals at the time of the transition at the data inputs pending, held in the bistable buffer 309 until the signal at the actuation connection G goes back to H. The sequencer 115 supplies 4 equal timing pulses T 0, T 1, T2 and T 3, which are active in the L or logic 0 state. The inverter 310 sets the correct polarity so that those generated by NAND gates 305-308

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Signals registered during the timing pulse T1 and held at the termination of the timing pulse T1 will. If a cache hit is detected in one of the tag memory modules, then the corresponding hit signal is A, B, C or D (which is carried on one of the lines 317, 318, 319 or 320) to H. The NOR gate 311 takes receives the hit signals from the output terminals Q of the bistable buffer 309 and generates an error signal (state H or logical 1) on line 117 if no hit is detected.

The replacement circuit 113 determines which cache location (i.e. a storage location in a label storage module and the corresponding storage location in a data storage module) to be used to store a new data word that the processor needs, but not at the moment is stored in cache memory. The replacement circuit selects the invalid one for the replacement of a memory section Contains data if one of the locations of the available subset of locations contains invalid data. If more than one location in the subgroup contains invalid data, then the replacement circuit 113 selects that Storage location in the data storage module with the highest priority, with A versus B, B versus C and C versus D. is preferred. If all storage locations of the subgroup contain valid data words, then the replacement switch goes

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device 113 switches to "random", i.e. it chooses at random one of the spebher make the subgroup for inclusion of the new data word. The valid bits read from the tag memory modules are sent to the priority encoder 312 of FIG Replacement circuit 113 supplied. If all 4 inputs to priority encoder 312 are high, then the signals are at the output connections AO, A1 and GS all to H. That would correspond to the case for which the data words in all data storage modules are valid, and accordingly, the replacement circuit 113 relies on the replacement method on a random basis the end. If any of the signals at the input terminals of the priority encoder 312 is low, then the signal is at the output terminal GS to L, and the signals at the output terminals AO and A1 are as follows: ■ · ' If the signal at input terminal 1 is low, then the signals at output terminals AO and A1 are low The signal at the input terminal 1 is high, the signal at the input terminal 2 but is at L, then the signals at the output connections AO and A1 are at H and L. If the signals at the input connections 1 and 2 are at H, but the signal at input connection 3 is at L, then the signals at output connections AO and A1 are at L or H. If the signals at input connections 1, 2 and 3 are at H ", but the signal at the input terminal 4 is at L, then the signals at the output terminals AO and A1 are both at H. The output signals of the priority encoder 312 become the bistable latch 313 transmitted, which is similar to the buffer 309 described above.

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is borrowed. When the signal at the input terminal G of the bistable Latch 313 is high, then the signals at output terminals 1Q, 2Q and 3Q follow the signals at the data input connections 1D, 2D and 3D. When the signal at the actuation connection G goes to L, then the signals that are present at the time of the transition at the data input connections were present, held at the output terminals Q until the signal at terminal G can go high again. The trailing edge of the timing signal T1 from the sequencer 115 holds the output signals of the priority encoder 312 in the bistable buffer memory 313 after the Output signals from the priority encoder had the opportunity to stabilize.

The signals at the output terminals 1Q and 2Q of the buffer 313 are fed to inputs 1A and 2A of data selector 314. The signal at the output terminal 3Q of the Latch 313 controls data selector 314. Replacement on a random basis is made using the 2-bit counter 315, which is incremented every time the processor 101 delivers a cache GO signal. The output signals of counter 315 go to inputs 1B and 2B of data selector 314. As hit and miss signals in cache memory operation occur on a random basis, the count value of the 2-bit counter 315 is close to a random number. The replacement circuit 113 transitions to replacement on a random basis if it is out of the tag memory modules

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read valid bits are in the state H and indicate that the addressed subgroup of data words is valid. In this case, all 4 inputs of the priority encoder 312 are high, so that the signal at the output terminal GS is high and is held in the bistable buffer memory 313. The output signal 3Q of the buffer 313 selects in this If the input signals 1B and 2B from the counter 315 for transmit to decoder 316. On the other hand, when an input to the priority encoder 312 is low, so the signal at the output terminal GS goes to L, and the signals at the output terminals AO and A1 of the priority encoder 312, which are held in the latch 313, are selected and via the inputs 1A and 2A of the data selector 314 led to decoder 316.

The decoder 316 generates a memory actuation signal H an one of its output terminals (1Y0 to 1Y3) and a signal L at the other 3 output terminals depending on the signals at the input connections 1A and 1B, as follows: for 1A and 1B both L, 1YO is at H (memory actuation D, MED); 'for IA and 1B on H or, L is 1Y1 on H (memory activation C, MEC); for 1Δ and 1B on L and H, respectively, 1Y2 is on H (memory actuation B, MEB); for 1A and 1B both high, 1Y3 is high (memory actuation A, MEA).

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ORIGSMAL IMSPECTED

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The tag memory control circuit 110 generates signals to the Reads and writes the tag storage modules 201 to 204 and also generates the valid bits that are stored in the tag storage modules are written, depending on the read / write signals and special signals of the Processor, the signals from the hit indicator circuit 116, the timing pulse T2 from the sequencer 115 and the signals from the replacement circuit 113. The data memory control circuit 111 generates signals for reading and writing of the data storage modules 401 to 404 and for forwarding data words to and from the data memory 107 as a function from the same signals that control the tag memory control circuit 110 as well as the main memory complete signal MMC. The following table summarizes the read / write operations that the Tag Store 106 can perform and the data memory 107 depending on certain combinations of processor control signals and hit / miss signals from the hit indicator circuit 116 executes. The table does not indicate the respective label memory module to be processed and the corresponding data storage module, since this depends on the respective hit information of the hit display circuit 116 depends, namely A, B, C or D in the case of a cache memory hit, and also from the respective memory actuation signal of the replacement circuit 113, namely MEA, MEB, MEC or MED in the event of a cache miss.

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processor
tax
signals Hit /
Miss -21-
Validity
bit
Status ** label
Storage
surgery 29 * 22597
data
Storage
surgery 1-read
normal Hit X Read Read 2-reading
normal Miss V Read/
To write To write 3-reading
special Hit I. Read/
To write Read 4-reading
special
5 letter
normal Miss
Hit X
■ ι | y] * Read
Read/
To write !To write 6 letter
normal Miss X. Read 7-letter
special. Hit V Read/
To write To write 8 letter
special Miss V Read/
To write To write

** V = valid, I = invalid, X = irrelevant

* required to use the cache memory at normal

Write on the latest. Stand to bring when

a cache hit occurs.

The tag memory control circuit 110 has 4 identical ones Tag store control logic circuits 205, 206, 207, 208 each of which is associated with a corresponding label storage module. Each of the control logic circuits 205-208 has decoding circuits which respond to the control signals from the processor 101, the hit / miss signals from the hit indicator circuit 116 and the memory actuation signals from the replacement circuit 113 respond. As the tag store control logic circuits are identical, will only

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the control logic circuit 205 is shown and described in detail. The NAND gates 209, 210, 211, 212, 213, 214 serve as decoders and supply a signal H at the output of the NAND gate s 214 for the following combinations of cache control signals and internally generated signals: Normal ^ read ^ ·, miss and memory actuation signal A; Special, write, miss and memory actuation signal Aj Special, write and hit signal Aj Normal, write and hit signal A; Special, read and hit signal A.

These combinations of signals correspond to the signal combinations 2, 8, 7, 5 or 3 in the table above. When any of these signal combinations from the tag store control logic circuit 205 is offered, the NAND gate 215 is actuated. Then the timing pulse causes T2 from the sequencer 115 the signal at the output of the NAND gate 215 on L to go, whereby the address label (AT), which the processor 101 makes available on the line 109, in the address memory module 201 is written to that memory location which is determined by the processor 101 on lines 108 supplied address signals is specified. Before arriving of the timing pulse T2, the tag storage modules 201 to 204 are in a read mode of operation in order to receive input signals for the hit indicator circuit 116 and the replacement circuit g 113 'to deliver.

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As indicated above, a valid data word is indicated by a signal H for the valid bit and an invalid one Data word by a signal L for the valid bit. For a normal write operation where a cache hit occurs, there are two alternative types of surgery:

1) The data word in data memory 107 that corresponds to the hit can be brought up to date by writing the new data word into the data memory 107 will; or

2) the data word in data memory 107 that corresponds to / the hit has resulted can in effect be removed by placing an invalid validity bit in the corresponding memory location of the label memory 106 is written.

The first possibility is created by the fact that the line 220 is omitted and the NAND gate 4o4 in the data memory control circuit 111 is provided to the new data word to write into the data memory 107. The second option is created by omitting NAND gate 404 and providing line 220 so that an invalid Valid bits are generated and written into the label memory 106 will. The NAND gate 216 is accordingly either by the output signals of the NAND gates 212 and 213 or by the Output of NAND gate 213 alone controlled to be invalid To generate valid bits to be written into the tag storage module 201. NAND gate 212 speaks on the combination of the signals normal, write and hit

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remote signal A, and the NAND gate 213 to the combination of the signals special, read and hit signal A. The NAND gate 216 is responsive to the output of one or both NAND gates 212 and 213 for an invalid valid bit for these two signal combinations. Line 220 is provided as an optional option to the output of the NAND gate 212 to one of the inputs of the NAND gate 216 to connect. The NAND gate 212 corresponds to the signal combination 5 in the table above and the NAND gate 213 the signal combination 3 in the table. The generated validity bit is stored in the corresponding label memory module registered at the same time as the address label (AT). A valid validity bit is generated for all other signal combinations with the status given in the table above for the validity bit, i.e. for all these signal combinations the validity bit is either valid or without Meaning. Inverter 219 provides the correct polarity for the valid bit, while inverters 217 and 218 provide signals with the correct polarity for the NAND gates 210, 211, 212, 213. The tag store control logic circuits 206, 207, 208 work similarly when performing operations for the label storage modules 202, 203 and 204 are to be executed.

The data memory control circuit 111 has NAND gates 401, 402, 403, 404, which provide a signal L at their output connections for the following combinations of input signals:

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Special, write and miss signal;

Normal, read, miss and main memory complete signals (MMC generated by main memory 103 when a main memory giant operation is completed); Special and write signal;
Normal and write signal.

As indicated above, NAND gate 404 is provided as an optional option when line 220 is not present is to keep the cache information up to date in normal write where a hit occurs bring. The NAND gates 401 and 402 decode Cacte operations, in which the data memory 107 is written on a cache miss signal, and the NAND gates 403 and 404 decode Cache operations when data memory 107 is written on a cache hit. The choice of which Data storage module is written under the control of the cache miss replacement circuit 113 and by the hit indicator circuit 116 for a cache hit. Accordingly, two groups of read / write gates are required, the NAND gates 406, 407, 408, 409 for a cache miss and the NAND gates 4ΐ4, 415,416, 4i7 for a Include cache hits. The output of the NAND gate

405 is high when either of the NAND gates 401, 402 is actuated and one of the memory actuation signals is also high. This combination of signals operates one of the NAND gates

406 to 409. The output of NAND gate 418 is on

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H if one of the NAND gates 403, 404 is actuated and if so a hit has occurred, one of the hit signals is also high. This combination of signals is actuated one of NAND gates 414 through 417. NAND gate 419 takes the timing pulse T2 from the sequencer 115 and the main memory termination signal from the main memory 103 on. When one of these signals occurs, which are low in the active state, the output of the NAND gate 419 goes to H. This output signal is one of the groups of NAND gates 406 to 409 or 417 to via the actuated NAND gate 419 transferred to the corresponding data storage module to write. The inverters 420, 421, 422 provide the correct signal polarity.

Bus transceivers 501 to 505 transmit either signals from the data connections E to the data connections F or Signals from the data connections F to the data connections E or represent a high impedance between the data connections E and F, depending on the control signals at the DIR and G connections. The bus transceivers are among each other identical and constructed in the same way as the bus transceiver 501 which includes AND gates 513, 514, inverters 515, 516, and bus drivers 517 and 518. A signal H at the actuation connection G of a bus transceiver separates the connections E from the connections F. A signal L at the actuation connection G actuates the bus transceiver and transmits the

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ORIGINAL INSPECTED "

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Control for the direction of the signal flow to the signal at the direction terminal DIR so that when the signal is high, data from the terminals F to the terminals E, and when the signal is low, data is transmitted from the E to the F terminals. The processor 101 controls the bus transceivers 505 to control the flow of data between the ' Main memory 103 and the data bus 112 to control. The NOR gates 423 through 426 determine which of the bus transceivers 501 through 504 is being operated. If one of the output signals of the NAND gate 401-404 is low, indicating that one of data storage modules 410-413 is being written should be, 'the output of the NAND gate 427 goes high, whereby the output signals of all 4 NOR gates 423 to 426 brought to L and all bus transceivers 501 to 504 operated will. The direction of data transfer is determined by the signal from NAND gate 428 which is low for the combination of read and cache hit signals, but for all others Signal combinations H is. The bus transceivers are in a disconnected state with high impedance or are transmitting data from the data bus 112 to the data storage modules if the processor is not requesting a read operation to detect noise to prevent the data bus for all other operations. Accordingly, data signals from the data bus 112 are at the data connections of data storage modules when one of them receives signals from one of the groups of NAND gates to 409 or 414 to 417 is written. When the signal from NAND gate 427 is low, the outputs of the

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NOR gates 423 to 426 of the hit signals A, B, C and D of the hit display circuit 116 from. Venn a hit in one of the tag memory modules A, B, C or D is detected, the hit signal transmitted to the NOR gates 423-426 goes A, B, C or D to H, whereby the output of the corresponding NOR gate goes to L and the corresponding bus transceiver actuated. If the signal from NAND gate 428 is low and the signal from one of NOR gates 423 to 426 are at L, the bus transceiver corresponding to the data storage module which contains the data word becomes the caused the cache hit, and the direction of the data flow goes from the connections E to the connections F, so that the read from the corresponding data storage module Data word is transmitted to the data bus 112.

Sequencer 115 provides internal timing pulses for cache memory operations. The sequential circuit assumes Clock signal from processor 101 on line 506 and is triggered by a cache GO signal from processor 101 on line 506 Line 114 activated. The cache GO signal from the processor is synchronized with the clock signal, so that the sequential circuit 115 provides complete clock pulse timing signals. The D flip-flops 507, 508, 509, 510 speak to you Transition L-H of the signal to their clock connections and transmit the signal present at connection D to connection Q. They can be set or deleted directly using the L signals at the S and C connections. The decoder 511 deco-

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converts signals at its input terminals 1A and 1B to provide a signal L at the output terminal corresponding to the instantaneous input signals, and signals H at the remaining output connections 1YO to 1Y3. The flip-flops 508, 509, 510 are cleared (Q = 0, Q = 1) and the flip-flop 501 is set (Q = 1, Q = 0) when the Sequence circuit 115 is activated by the cache GO signal from processor 101. The cache GO signal results in a low to high signal transition at the clock connection of the flip-flop 508, whereby the flip-flop is set and the logical 1 at the connection D to port Q is transmitted. Setting the flip-flp 508 eliminates the direct clear signal for flip-flops 509 and 510, leaving them on the clock signal from the processor can address. During the first full clock cycle, the signal at the output 1YO of the decoder circuit 511 is low and the other outputs 1Y1 to 1Y3 are at H. The next L-H transition of the clock signal, the flip-flop 509 is set, while the flip-flop. 510 remains deleted. This changes the input signals of the decoder circuit 511 so that that the signal at the output terminal 1Y1 goes low and the signals at the output terminals 1YO, 1Y2 and 1Y3 are on H. At the n-th next L-H transition of the clock signal, the flip-flop 510 is set while the flip-flop 509 is set remain. As a result, the output signal of the decoder 511 is switched on in such a way that the signal at the output connection 1Y3 is L and the signals at the remaining output connections are H. The next L-H transition of the clock signal will be

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the flip-flop 509 is cleared and the flip-flop 510 remains set. As a result, the output signal of the decoder 511 is switched so that the signal at the output terminal 1Y2 goes low and the signals at the remaining output terminals are high. At the next low to high transition of the clock signal flip-flop 510 is cleared and flip-flop 509 remains clear. This causes the signal to rise at the output terminal 1Y2 The signal at the output terminal 1Y0 is high and the signal at the terminals 1Y1 and 1Y3 remains high. Of the Transition from L to H at the clock connection of the flip-flop 507 brings this flip-flop into the clear state, whereby the flip-flop 508 is deleted, which in turn deletes the flip-flops 509 and 510 and applies a locking signal L to these flip-flops, so that they cannot respond to the signal transitions of the clock signal. Bas signal L at the output terminal 1Y0 becomes delayed by the delay element 512 a short period of time before it is applied to the setting terminal of the flip-flop 507 is applied and the flip-flop 507 sets to remove the direct erase inhibit signal on the flip-flop 508 and prepare sequencer 115 for activation by the cache .G0 signal from processor 101.

Two memory scan operations will now be described in order to improve the operation of the cache memory and let it be understood more fully. These operations are once a normal read accompanied by a cache miss signal, and on the other hand, a special reading, accompanied by

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a Caclie-Treff er signal. To simplify the description it is assumed that the memory actuation signal A (MEA) for the cache miss signal is high and that the hit signal A is high for the cache hit. The processor 101 generates the Control signals, the address label signals, the data store and label store address signals and then asserts the cache GO signal. In the case of normal reading, the read / write signal and the special signal are both high, which means that the NANB gate 209 is being prepared. During the first two The tag memory modules 201 to 204 at the address supplied by the processor 101 are read by timing pulses. The address labels read are given to the comparison circuits 301 to 304 and the valid bits read to the NAND gates 305-308 and the priority encoder 312. When the timing pulse T1 stops, the output signals become the NAND gates 305-308 are held in the bistable latch 309, and the output signals of the priority encoder 312 are stored in the bistable buffer 313 saved. Since a failure is assumed, the output of the latch 309 is low and the output is low of the NOR gate 311 is accordingly at H. The output signals of the latch 313 depend on the Status of the valid bits that have been read from the tag memory modules and control the memory actuation signals from the decoder 316 as described above under the action of the replacement circuit 113. The Memory actuation signal A (MEA) has been assumed to be H for simplicity of description. When the signal MEA and

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the fault signal are high, the NAND gate 209 is actuated and provides an output signal L to an input of NAND gate 214 to operate NAND gate 215. None of the Inputs of NAND gate 216 is low, so its output is low and the output of inverter 219 is high to produce a valid valid bit. The timing pulse T2 from sequencer 115 causes the NAND gate 215, the address label supplied by the processor 101 and the valid valid bit from the inverter 219 into the label memory module 201 at the address addressed by the processor. The data memory 107 leads to this point in time no operations. The processor 101 receives the miss signal from the hit indicator circuit 116 and determines that a main memory read operation must be performed. The processor maintains the signals for the cache memory and executes a main memory read operation. When the read operation is finished and valid data is stable on the data bus main memory sends a main memory complete (MMC) signal on line 118 to cache memory 102. The NAND gate 402 is activated by the normal, read and miss signal and activated by the main memory end signal, so that it produces a signal L at its output. This signal operates the NAND gate 427 which drives the bus transceivers 501 to 504 activated via NOR gates 423 to 426. The direction of the data flow goes from the data connections F. the data terminals E due to the signal H from the NAND gate 428. The NAND gate 406 is activated by signals H

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from the NAND gate 405 and the MEA signal from the replacement circuit 113, so that the main memory completion signal drives the output of NAND gate 406 low to transfer the data on data bus 112 into the data storage module A in the memory location addressed by processor 101. Accordingly, the address label is im Tag storage module 201 along with a valid valid bit saved, and the corresponding memory location in Data storage module 410 contains the correct one from main memory read data word.

The next memory scan will be a special read where a cache hit occurs. The read / write signal is high and the special signal is low. The address label signals and the address signals are the same as previously. The NAND gate 213 is activated by the read / write signal and the special signal prepared by the processor. The label memory modules are read and the information is again transmitted to hit display circuit 116 and replacement circuit 113. However, in the event of a hit one of the hit signals A, B, C or D to H, while the Hit / miss signal from NOR gate 311 is low. The hit signal A has been assumed to be H for simplicity of description. The hit signal A activates the NAND gate 213, which generates an invalid valid bit and also causes the label memory module 201 to be written. Simultaneously the bus transceiver 501 is actuated via the NOR gate. The data flow is from the data connections E to the

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Data connections F due to the signal L from the NAND gate
428 directed. The data storage module 410 is read and the read data word is transmitted to the processor via the data bus 112. The desired data memory word is thus read from the cache memory, and this data word is stored in the
Tag storage module 201 is marked invalid, which in effect removes it from the cache so that the memory location can be used immediately for new information to be written into the cache. The other memory operations listed in the table above are performed by the cache memory in a similar manner.

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Claims (6)

BLUMBACH · WESER ". BERGEN. KRAMER ZWIRNER BREHM --- PATENT LAWYERS IN MUNICH AND WIESBADEN '2922597 Patentconsult Radeckestraße 43 8000 Munich 60 Telephone (089) 883603/883604 Telex 05-212313 Telegrams Patentconsult Palentconsult Sonnenberger Straße 43 6200 Wiesbaden Telephone (06121) 562943/561998 Telex 04-186237 Telegrams Patentconsult Western Electric Company Incorporated Chang, S.J.1-19 222 Broadway, New York N.Y. 10038, USA Cache memory and method for operating a data processing system Patent claims: Cache memory for a data processing system with a device for storing data words, an addressable one Identification for each data word and an indication of the validity or invalidity of each Word, ^ " marked by an arrangement (110) which, upon addressing the memory with an identifier, in response to that Identification is stored, as well as an indication that the corresponding data word is valid, and on a Read signal stores an invalid information with reference to the data word. . Munich: R. Kramer Dipl.-Ing. · W. Weser Dip! .- Phys. Dr. rer. nat. · H. P. Brehm Dipl.-Chem. Dr. phil. nat, Wiesbaden: P. G. Blumbach Dipl.-Ing. P. Bergen Dipl.-Ing, Dr. jur. . G. Zwirner Dlpl.-Ing. Dipl.-W.-Ing. 909 8 51/0682 2022597 2. Cache memory according to claim 1, characterized in that when the memory is through a Identification is addressed which is not stored or for which the data word is designated as invalid, the arrangement (110, 111) depending on a normal read signal, the data word, the identification and a designation that writes validity, but does not write in response to a special read signal. 3. Cache memory according to claim 1, characterized in that when the memory is addressed by an identifier, the arrangement (110, 111) in response to the stored identification, an indication that the corresponding data word is valid and a normal write signal stores an indication of the invalidity for the data word and in response to a special write signal the data word, the identification and writes an indication of the validity for the data word. 4. Cache memory according to claim 1, characterized in that when the memory is addressed by an identifier, the arrangement (110, 111) in response to the stored identification, an indication that the corresponding data word is valid and a normal write signal the data word and a validity 909851/0682 2122197 writes specification with reference to the data word, and in response to a special write signal writes the data word, inscribes the identification and an indication of validity with reference to the data word. 5. A method for operating a data processing system with a processor, a main memory and a cache memory, wherein in the cache memory required data words by the processor, an addressable identifier for each Data word and an indication of the validity or invalidity of each word are stored, characterized in that when addressing the cache memory with an identification stored in it and, if the corresponding one Data word is valid, a read operation has the effect that an invalid statement is stored for this data word. 6. Method for programming a data processing system with a processor, a main memory and a cache • Storage, • characterized in that the system operated according to the method according to claim 5 will. 909851/0682