EP3724983A1

EP3724983A1 - Control of electrical converter with paralleled half-bridges

Info

Publication number: EP3724983A1
Application number: EP18814969.4A
Authority: EP
Inventors: Johannes BURKHARD; Jürgen BIELA; Uwe Drofenik
Original assignee: ABB Schweiz AG
Current assignee: Hitachi Energy Ltd
Priority date: 2017-12-13
Filing date: 2018-12-13
Publication date: 2020-10-21
Also published as: WO2019115701A1

Abstract

An electrical converter (10) comprises at least two phase branches (12A, 12B, 12C, 12N), each phase branch comprising at least two half-bridges (16), which are connected in parallel to a DC link (14) and which are connected via midpoints (18) for providing a phase output (A, B, C, N) for the phase branch. A method for controlling an electrical converter (10) comprises: determining setpoint phase signals (V_i,ABC*) for the phase branches from actual phase voltages (V_ABC ⁰) and actual phase currents (i_L,ABC ⁰), which are determined from measurements, and from reference phase voltages (V_dq0*) for the phase branches (12A, 12B, 12C, 12N); determining a phase duty cycle (d_A, d_B, d_c, d_N) for each phase branch (12A, 12B, 12C, 12N) from the setpoint phase signals (V_i,ABC*); determining a half-bridge duty cycle (d_Aj, d_bj, d_cj, d_Nj) for each half-bridge (16) by adding a duty cycle correction (Δd_Aj, Δd_Bj, Δd_Cj, Δd_Nj) for the half-bridge (16) to the phase duty cycle (d_A, d_B, d_C, d_N) for the phase branch (12A, 12B, 12C, 12N) to which the half-bridge (16) belongs, wherein the duty cycle correction is determined from actual half- bridge output currents (i_L,A_j ⁰, iL,B_j ⁰, i_L,C_j ⁰, i_L,N_j ⁰) of the half-bridges (16) of the phase branch, which actual half-bridge output currents (i_L,A_j ⁰, i_L,Bj⁰, i_L,C_j ⁰, i_L,N_j ⁰) are determined from measurements.

Description

DESCRIPTION

Control of electrical converter with paralleled half-bridges

FIELD OF THE INVENTION

The invention relates to a method and a controller for controlling an electrical converter as well as to the electrical converter. Furthermore, the invention relates to a hybrid transformer.

BACKGROUND OF THE INVENTION

For interconnecting electrical grids, energy conversion systems are used, which transform a current of a first frequency and/or a first voltage into a current of a second frequency and/or a second voltage. For high-current low-voltage conversion systems, for example a hybrid transformer with a low-voltage side converter, a large number of semiconductor chips has to be connected in parallel for the converter. Employing wide bandgap semiconductor switches like, for example, GaN based switches may allow very low losses, a simple and reliable cooling (with natural convection and no fan) and a very high compactness of the converter.

If half-bridges of the converter are paralleled for high current capability, it is possible to increase the switching frequency of the output current by interleaving of the half-bridges, which may allow a reduction of filter size and cost. Paralleling a large number of such half- bridges may result in an inhomogeneous current distribution due to small differences of parasitics, semiconductor properties, local temperatures and/or small disturbances in the control patterns. This may be especially a problem with small-sized chips like those based on GaN, where a large number may be required. Inhomogeneous current distribution may result in increased losses of a few switches that will then fail earlier as the others.

Generally, currents in paralleled half-bridges may be balanced in a passive way by adding inductively coupled components, such as interphase transformers, which, however, would increase size, cost, losses and complexity of the whole converter. Alternatively, it may be possible to actively balance currents in paralleled half-bridges. The scientific article“Design and control of a grid-connected interleaved inverter” by M. A. Abusara and S. M. Sharkh, IEEE Transactions on Power Electronics, 2013, shows an interleaved three-phase inverter with paralleled half-bridges. Each of the paralleled half bridges has a separate boost inductor current controller with the same reference current provided by an outer voltage controller.

EP 2 665 170 A 1 shows a power converter system, which supplies a three-phase current to a transformer. Every phase of the current is generated by two half-bridges. A controller generates the switching signals for the half-bridges from measurements of currents between the half-bridges and a filter.

US 2016/373 044 Al shows a converter system, in which two three-phase converters are connected in parallel for supplying a motor. Each of the converters generate PWM switching signals for each of its phases based on measurement of its output phase currents and the sum phase currents.

DESCRIPTION OF THE INVENTION

It is an objective of the invention to provide an electrical converter with paralleled and optionally interleaved half-bridges having a homogeneous current distribution. It is a further objective of the invention to provide an electrical conversion system with high efficiency, high reliability and a long lifetime.

These objectives are achieved by the subject-matter of the independent claims. Further exemplary embodiments are evident from the dependent claims and the following description.

A first aspect of the invention relates to a method for controlling an electrical converter. A further aspect of the invention relates to an electrical converter, which is controlled with such a method.

According to an embodiment of the invention, the electrical converter comprises: at least two phase branches, each phase branch comprising at least two half-bridges, which are connected in parallel to a DC link and which are connected via midpoints for providing a phase output. Furthermore, the electrical converter may comprise a controller, which performs the method.

Each phase branch may convert a DC voltage from the DC link into an AC voltage provided at the phase output. The DC link may comprise a capacity, which is connected in parallel to the half-bridges of all phase branches. A half-bridge may comprise two semiconductor switches, which are connected in series and which provide the midpoint of the half-bridge in between them. It has to be noted that one semiconductor switch may be composed of several semiconductor devices, such as transistors, which are connected in parallel.

According to an embodiment of the invention, the method comprises: determining setpoint phase signals, or setpoint phase voltage signal, for the phase branches from actual phase voltages and actual phase currents, which are determined from measurements, and from reference phase voltages for the phase branches. For all or some of the phase branches, an actual phase voltage and an actual phase current may be measured. Each actual phase voltage and/or actual phase current may be measured before or after an electrical filter connected to the phase outputs. It also may be possible that the actual phase current is determined from actual half-bridge output currents through the midpoints of the half-bridges of the phase branch.

According to an embodiment of the invention, the method further comprises: determining a phase duty cycle for some or all of the phase branches from the respective setpoint phase signal. A setpoint phase signal may determine, how the phase voltage of the respective phase branch should be. Therefrom, duty cycles for each phase branch may be determined.

A duty cycle may be a number, for example between 0 and 1 . A phase duty cycle for a phase branch may indicate how long the phase branch should be connected to the DC link during one cycle.

According to an embodiment of the invention, the method further comprises: determining a half-bridge duty cycle for each half-bridge by adding a duty cycle correction for the half bridge to the phase duty cycle for the phase branch to which the half-bridge belongs, wherein the duty cycle correction is determined from actual half-bridge output currents of the half- bridges of the phase branch, which actual half-bridge output currents are determined from measurements.

A half-bridge duty cycle for a half-bridge may indicate how long the half-bridge should be connected to the DC link during one cycle.

In the invented control structure, the current balancing control may be seen as fully decoupled from a main current control loop, which may allow designing independent and highly dynamic current control, enabling effective current balancing. For all or some phase branches, the actual half-bridge output currents may be measured, for example directly the midpoints of the respective half-bridges. From these currents, a duty cycle correction is determined for every half-bridge. For example, the duty cycle correction for a half-bridge may be determined based on a deviation of the respective actual half-bridge current from an averaged half-bridge current for the respective phase branch. In the end, the half-bridge duty cycle for a half-bridge may be determined by adding the duty cycle correction for the half-bridge to the phase duty cycle of the respective phase branch.

According to an embodiment of the invention, the method further comprises: switching semiconductor switches of the half-bridges based on the respective half-bridge duty cycle, wherein the half-bridges of a phase branch are switched to generated half-bridge output currents summing up to the actual phase current of the phase branch. The method may comprise determining switching signals for the half-bridges from the half-bridge duty cycles, for example by pulse width modulation. The semiconductor switches may be switched based on the switching signals.

The semiconductor switches of the half-bridges are switched to produce an output voltage adapted to the corresponding half-bridge duty cycle. This may be achieved with pulse width modulation of a carrier signal for the half-bridge. When the carrier signal is higher as the duty cycle value, then an upper switch of the half-bridge is switched on, else a lower switch is switched on. The carrier signal may be a triangular or zig-zag signal.

According to an embodiment of the invention, the half-bridges of a phase branch are switched in an interleaved way to generate the half-bridge output currents, which then may be seen as interleaved half-bridge output currents. Interleaved output currents may be currents, which sum up to the desired phase current, but which may have different instantaneous current values at one time point. The interleaved output currents may have a triangular shape and/or may be phase shifted with respect to each other. For example, interleaved output currents may be achieved by phase shifted carrier signals for pulse width modulation.

With the method, an active current balancing for the paralleled half-bridges for all or some of the phase branches may be achieved in a simple way. The method or controller comprises two control parts, which may be seen as decoupled from each other. A first control part determines phase duty cycles based on the phase voltages and phase currents of each phase branch. A second control part determines duty cycle corrections for the half-bridges of a phase branch from (solely) current deviations in the half-bridges. Usually, the current imbalance of a half-bridge are independent from the currents of other phase branches and half-bridges of other phases, from the common phase duty cycle and from the phase voltages. The current imbalances may therefore effectively be eliminated or at least reduced by a duty cycle correction provided by the first control part, which need not influence the second control part. As a result, the second control part may be designed independently of the first control part. A stability of the controller may not be disturbed by the current balancing. The two-part control may result in a simple controller design and may reduce an implementation effort.

By applying the method, no additional interphase-transformers may be required in the converter. This may result in lower cost, reduced complexity, lower losses and a very high power density. Furthermore, a converter operated with the method may have a higher scalability, which may be used for processing high currents.

According to an embodiment of the invention, the duty cycle correction for a half-bridge is determined from a deviation of an actual half-bridge output current from an averaged half- bridge output current, which averaged half-bridge output current is the sum of the half-bridge output currents of the respective phase branch, the half-bridge belongs to, divided by the number of half-bridges of the respective phase branch. The output currents of all half-bridges of one phase branch may be summed up and an averaged output current may be determined by dividing by the number of half-bridges. By subtraction the averaged output current from the actual output current of one half-bridge, a difference current and/or a deviation from the averaged current may be determined. This difference and/or deviation may be used for determining the half-bridge duty cycle correction.

According to an embodiment of the invention, the duty cycle correction is determined from the deviation of the actual half-bridge output current with proportional or proportional integral control. It may be that the duty cycle correction is determined from the deviation by multiplication with a constant factor. However, also more complicated control schemes additionally including differential and/or integrational control may be possible.

According to an embodiment of the invention, the duty cycle correction of one half-bridge of a phase branch is determined from the sum of the duty cycle corrections of the other half- bridges of the phase branch. Since the half-bridge output currents sum up to the phase current, it may be assumed that the duty cycle corrections of one phase branch sum up to 0. In this case, one of the duty cycle corrections may be determined from the other ones, which may save computational power of the controller. According to an embodiment of the invention, the actual phase current for a phase branch is determined by adding the determined actual half-bridge output currents of the half-bridges of the respective phase branch. It may be that the actual phase current is not determined with an additional sensor, but is determined from the already present measurements for the actual half-bridge output currents. It has to be noted that in this case, the actual phase current is indicative of the phase current before an electrical filter, which may be connected to the phase outputs. This may be beneficial in view of the first control part, which may then react faster in view of its control objectives.

According to an embodiment of the invention, the setpoint phase signals are determined with an outer voltage control loop and an inner current control loop. It may be that the first control part is based on cascaded control.

The reference phase voltages and the actual phase voltages may be input into the outer voltage control loop for determining setpoint phase currents. There may be a setpoint phase current, i.e. value to which the phase current should be controlled for all or some of the phase branches. The setpoint phase currents and the actual phase currents then may be input into the inner current control loop for determining the setpoint phase signals.

According to an embodiment of the invention, actual filtered phase currents determined from current measurements after an electrical filter connected to the phase outputs are additionally input to the voltage control loop for determining the setpoint phase currents. This may enhance the quality of the setpoint phase currents.

According to an embodiment of the invention, the actual phase voltages and the actual phase currents are transformed into a dq-system. These electrical quantities may be transformed from an ABC-system into the dq-system. The ABC-system is an electrical system, in which the measured electrical quantities, such as the phase currents and the phase voltages, are directly measured. In the ABC-system, the electrical quantities seen as vectors are rotating with the frequency of the respective current/voltage and are considered independently from each other, although they may sum up to 0. In the dq-system, the electrical quantities are rotated with the fundamental frequency of the respective current/voltage to be substantially constant and are furthermore transformed into two electrical quantities by considering the 0 sum of the three ABC-system-components.

In the case, when also a neutral phase current has to be controlled and/or is generated by the converter, the first and/or second control part may be performed in a dqO-system, in which also, the sum of the electric quantities of the ABC-system is considered, which then may deviate substantially from 0.

According to an embodiment of the invention, the setpoint voltages are transformed into an ABC-system before the duty cycles are determined. After the determination of the setpoint voltages in the dq(0)-system, they may be transformed back into the ABC-system, where the duty cycles then may be determined.

A further aspect of the invention relates to a controller for an electrical converter adapted for performing the method as described in the above and in the following. For example, the method may be implemented in a DSP or FPGA. It also may be possible that the method is at least partially implemented in software, which is executed in a processor.

As already mentioned, the electrical converter with such a controller, which controls the electrical converter with the method as described in the above and in the following, is an aspect of the invention.

According to an embodiment of the invention, the electrical converter comprises (solely) three-phase branches. These three-phase branches may be controlled to generate a three- phase current with 120° phase shift. In this case, the first control part may be partially performed in the dq-system.

According to an embodiment of the invention, the electrical converter comprises four phase branches including a phase branch for providing a neutral point voltage. Three phase branches may be controlled to generate a three-phase current with substantially 120° phase shift. The fourth branch may be controlled to generate a neutral point current for equalizing the three-phase current.

A four-phase converter may be used for equalizing a three-phase electrical system, such as a low voltage electrical, by interconnecting the electrical converter in series between the three-phase electrical system and a neutral point.

According to an embodiment of the invention, the midpoints of the half-bridges of one phase branch are connected via inductances with the phase output of the phase branch. These inductances may be chosen, such that a triangular half-bridge output current is generated from the voltages connected by the respective half-bridge to its midpoint.

According to an embodiment of the invention, a passive electrical filter interconnects the phase outputs of the phase branches. For example, the phase outputs of the converter, possible including a neutral phase output, may be interconnected via star-connected capacities. Alternatively or additionally, the electrical filter may include inductances connected in the phase outputs.

According to an embodiment of the invention, a semiconductor switch of a half-bridge is composed of at least two semiconductor devices connected in parallel with electrically interconnected gates. For example, the parallel connected semiconductor devices may be switched with one gate signal, i.e. they may be hardware paralleled. The semiconductor devices may be tuned, such that it is not necessary to account for possible imbalances between them. Equal current sharing between the semiconductor devices may be achieved by individually tuned gate-resistors and a symmetric placement of the devices.

According to an embodiment of the invention, the semiconductor devices are GaN transistors. Some or all of the half-bridges may comprise several hard-paralleled GaN devices forming the upper semiconductor switch and an equal number of hard-paralleled GaN devices forming the lower semiconductor switch. With GaN devices, natural convection cooling of the electrical converter may be possible, since a switching with rather low losses and high frequency is possible. No cooling fan may be necessary, which may enhance the reliability of the electrical converter.

A further aspect of the invention relates to a hybrid transformer comprising an electrical converter as described in the above and in the following.

According to an embodiment of the invention, the hybrid transformer comprises a primary side winding arrangement connectable to a first electrical grid and a secondary side winding arrangement connectable to a second electrical grid. Both the primary side winding arrangement as well as the secondary side winding arrangement may comprise three windings for each phase of the respective grid. The phase outputs of the electrical converter may be series-connected with windings of the secondary winding arrangement. In such a way, the electrical converter may be used for equalizing the second electrical grid. It also may be that the electrical converter has a neutral phase, which then may be series-connected with a neutral point of the second electrical grid.

According to an embodiment of the invention, the hybrid transformer further comprises an auxiliary winding arrangement coupled with the primary side winding arrangement and a converter, for example a rectifier, for rectifying a current from the auxiliary winding arrangement and for supplying the DC link of the electrical converter. The electrical energy for supplying the electrical converter and/or for equalizing the second electrical grid may be drawn from the first electrical grid. According to an embodiment of the invention, the first electrical grid is a medium voltage grid and/or the second electrical grid is a low voltage grid. The electrical converter may be connected to the low voltage side of a transformer supplying a low voltage distribution grid. In this context, a medium voltage may be a voltage between 2 kV and 50 kV. A low voltage may be a voltage up to 1 kV.

It has to be understood that features of the method as described in the above and in the following may be features of the controller, the converter and the hybrid transformer as described in the above and in the following, and vice versa.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject-matter of the invention will be explained in more detail in the following text with reference to exemplary embodiments which are illustrated in the attached drawings.

Fig. 1 schematically shows a circuit diagram for an electrical converter according to an embodiment of the invention.

Fig. 2 schematically shows a circuit diagram for a semiconductor switch for the electrical converter of Fig. 1.

Fig. 3 shows a control scheme illustration of a controller and a control method according to an embodiment of the invention.

Fig. 4 shows a part of the control scheme of Fig. 3 in more detail.

Fig. 5 shows a hybrid transformer according to an embodiment of the invention.

Fig. 6 shows a diagram with currents without the balancing control of the control method of Fig. 3.

Fig. 7 shows a diagram with currents with the balancing control of the control method of Fig. 3.

The reference symbols used in the drawings, and their meanings, are listed in summary form in the list of reference symbols. In principle, identical parts are provided with the same reference symbols in the figures. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Fig. 1 shows an electrical converter 10 comprising four phase branches 12A, 12B, 12C and 12N, each of which provides a phase output A, B, C, N of the electrical converter. Each of the phase branches 12A, 12B, 12C and 12N is connected in parallel to a DC link 14, which comprises a capacity CDC.

Furthermore, each phase branch 12A, 12B, 12C and 12N is composed of p half-bridges 16, which are connected in parallel to the DC link 14 and which midpoints 18 are connected with the respective phase output A, B, C, D. Every midpoint 18 is connected via an inductance L with the respective phase output A, B, C, D.

Every half-bridge 16 is composed of an upper semiconductor switch 20 A and a lower semiconductor switch 20B, which are series-connected and which provide the respective midpoint 18 in between them. The semiconductor switches 20A, 20B are controlled by a controller 22, which generates the gate signals for the gates of these switches.

The phase outputs A, B, C, N may be interconnected with a passive electrical filter 24, which, as shown, may comprise star-connected capacitors CA, CB, CC and CN. Also, the inductances L may be seen as an electrical filter or a part of the electrical filter 24.

Under the control of the controller 22, the phase branches 12A, 12B, 12C, 12N convert the DC link voltage VDC into the phase voltages VA, VB, VC, VN, which are AC voltages. These voltages may be measured across the star-connected capacitors CA, CB, CC and CN.

Usually, the three-phase voltages VA, VB, VC may be substantially sinusoidal voltages, which are phase shifted by 120° with respect to each other. The neutral point voltage VN may be used for equalizing a neutral point of an electrical system that is interconnected with the three-phase outputs A, B, C of the electrical converter 10.

Fig. 1 also shows the half-bridge output currents i_L,Bj , ii .c _j, ii .x_j, which flow from the midpoints 18 of the half-bridges 16 via the inductances L to the respective phase output A, B, C, N of the respective half-bridge 12A, 12B, 12C, 12N. The sum of these half-bridge output currents per phase branch, i.e. the phase current, is denoted by ΪO,A, ΪO,B, io,c, ΪO,N.

It has to be noted that it is also possible that the converter 10 may solely comprise the phase branches 12A, 12B, in which cases it may provide a two-phase output current. Furthermore, it may be possible that the converter 10 solely comprises the phase branches 12A, 12B, 12C, i.e. may provide a three-phase output current without a neutral phase. Fig. 2 shows an example of a semiconductor switch 20A, 20B that may be employed in the half-bridges 16 of the electrical converter 10. Each semiconductor switch 20A, 20B may be composed of at least two switchable semiconductor devices 26, which are connected in parallel. Furthermore, the semiconductor devices 26 may be connected to the same gate line and therefore may be switched by the same gate signal from the controller 22. The semiconductor devices 26 may be GaN transistors.

Fig. 3 shows a block diagram of a control scheme that may be performed by the controller 22. The controller comprises a first control part 28, which may be seen as a cascaded controller, and a second control part 30, which may be seen as a balancing controller. The electrical converter 10 is indicated as a box inside the first controller part 28. Inside the box, also the part of the converter 10 with the half-bridges 16 and the part with the electrical filter are schematically shown.

The first, cascaded control part 28 comprises an outer voltage controller 32, an inner current controller 34, a duty cycle generator 36 and a pulse width modulator 38. Furthermore, several transformers 40A, 40B, 40C, 40D are present, which are adapted for transforming electrical quantities in the ABC-system into electrical quantities in the dqO-system and vice versa.

The second, balancing control part 30 comprises a current balancing controller 42 and several adders 44 for summing current values.

In the following, the electric quantities for the phases A, B, C are summarized in a corresponding vector. For example, the phase voltages VA, VB and Vc are summarized in the phase voltage vector VABC. It has to be noted that electrical quantities summarized in a vector also may be seen as three individual quantities.

For performing the control, in the electrical converter 10, the actual phase voltages of the phases A, B, C or the actual phase voltage vector V_ABC ⁰ and the actual half-bridge output currents fix,⁰, iL,Bj°, ir.x j⁰, i\.₍ j° are measured.

In the cascaded controller part 28, the setpoint phase signals or setpoint phase signal vector Vi, _ABC ^* are determined with the voltage controller 32 as outer voltage control loop 32 and the current controller 34 as inner current control loop.

The actual phase voltage vector VABC⁰ is transformed with the transformer 40A into a dqO-system. The resulting transformed actual phase voltage vector V_dqo° is input into the voltage controller 32. Optionally, it is possible that actual filtered phase currents, which are composed into an actual filtered phase current vector io,ABC°, are determined from current measurements after or within the electrical filter 24. The actual filtered phase current vector IO.ABC⁰ is transformed with the ABC-dqO transformer 40C into the dqO-system. The resulting transformed actual phase current vector ii ._dqo° may also be input into the voltage controller 32 as a current-feed-forward control signal.

From a reference phase voltage vector Vd_qo*, which may be provided from a superordinated controller, the actual phase voltage vector Vd_qo° and optionally the (transformed) filtered phase current vector io,d_qo°, the voltage controller 32 determines a setpoint phase current vector or reference vector ii_..dqo^*.

The setpoint phase current vector ii ._dqo \ the actual phase voltage vector Vd_qo° and a phase current vector i r _..dqo°, which was transformed into the dqO-system, are input into the current controller 34, which determines a setpoint vector or reference vector Vi,d_qo* for the phase signal vector transformed into the dqO-system.

The transformed actual phase current vector ii ._dqo° is generated with the transformer 40B, which receives an actual phase current vector IL,ABC⁰ from the adders 44, which add the actual half-bridge output currents to the respective component of the actual phase current vector ILABC⁰.

The setpoint vector Vi,d_qo* in the dqO-system is transformed into a setpoint vector or reference vector Vi,ABC* in the ABC-system with the transformation or transformer 40D. In particular, the setpoint signals from the vector Vi,ABC* are transformed back into the ABC- system before the phase duty cycles d_A, du, dc, d_N are determined by the duty cycle generator 36.

It has to be noted that in the case of a three-phase converter 10, i.e. without the phase branch 12N, the controllers 32, 34 may be supplied with quantities transformed into a dq- system (without the 0-component). While in the dqO-system, the vectors are all three- component vectors, in the dq-system, the vectors are all two-component vectors.

It may be beneficial to implement the control loops 32, 34 in the rotating dq(0)-reference frame, since the AC quantities of a symmetrical three-phase system may then be transformed to DC quantities, which may be controlled with simple PI controllers 32, 34. For a converter 10 with four phase branches 12A, 12B, 12C, 12N, a further degree of freedom has to be controlled which is represented by the 0-component of the dqO-system. For example, a conventional cascaded dq-control with an inner current and outer voltage control loop may be extended by a separate channel for the 0-component. In this way, a simple control structure for a four-phase converter 10 may be obtained.

In the end of, the duty cycle generator 36 determines a phase duty cycle d_A, dn, dc, d_N for each phase branch 12A, 12B, 12C, 12N from the setpoint phase signals VL_ABC ^*, i.e. in the case of an additional neutral phase branch 12N, four phase duty cycles are determined from a three-component vector. The outputs of cascaded control 28 are the common phase duty cycles d_A, de, dc, d_N. All parallel half-bridges 16 of one phase branch 12A, 12B, 12C, 12N are associated with the same common phase duty cycle d_A, dn, dc, d_N.

With the aid of the current balancing controller 42, a half-bridge duty cycle d_Aj, de_j, dq, d_Nj is then determined for each half-bridge 16 by adding a duty cycle correction Ad_Aj, Ade_j, Adq, Ad_Nj for the half-bridge 16 to the phase duty cycle d_A, dn, dc, d_N for the phase branch 12A, 12B, 12C, 12N to which the half-bridge 16 belongs.

The duty cycle corrections Ad_Aj, Ade_j, Adq, Adq are determined by the current balancing controller 42 from the actual half-bridge output currents ii .is_j ⁰, ii .q⁰, ii .q⁰, as will be explained in more detail below with respect to Fig. 4.

The pulse width modulator 38 transforms the half-bridge duty cycle d_Aj, dn,, dq, dq into switching signals for the half-bridges 16. The switching signals are formed, such that the semiconductor switches 20A, 20B of the half-bridges 16 are switched to generated half bridge output currents ii ._;\j, iu _j, ii .q, ii .q , which may be interleaved. In other words, the half-bridge output currents iqAj_^ ii .B_j, ii .q, ii .q of one phase branch 12A, 12B, 12C, 12N may have a substantially triangular shape and/or may sum up to the actual phase current of the phase branch 12A, 12B, 12C, 12N.

Fig. 4 shows the current balancing controller 42 in more detail. In particular, only the part of the current balancing controller 42 for one phase branch (here 12 A) is shown. It has to be understood that the current balancing controller 42 comprises the part shown in Fig. 4 for every phase branch 12A, 12B, 12C and 12N, when present.

Furthermore, in Fig. 4, an example with P=3 half-bridges 16 per phase branch 12A is shown. Thus, only half-bridge output currents ii .Ai , IL,A2, i r ..L3 are input into this part of the current balancing controller 42.

An averaged half-bridge output current IL,A* is determined with the averager 46. The averaged half-bridge output current IL,A* is the sum of the actual half-bridge output currents ir_..,_\j° of the respective phase branch 12A, 12B, 12C, 12N, the respective half-bridge 16 belongs to, divided by the number P of half-bridges 16 of the respective phase branch 12A, 12B, 12C, 12N.

Then, deviations Dίi .,_\i , Dΐ r ._;\2 from the actual half-bridge output current are determined by subtracting the respective actual half-bridge output current from the averaged half-bridge output current IL,A*· The duty cycle correction Ad_;\j for a half-bridge 16 is then determined with a proportional or proportional integral controller 48 from the respective deviation DI I .L I , Dΐ r ._;\2. The controllers 48 may be designed, such that they force the respective deviation or imbalance AI_LAI, DΪ _{I ..L}2 substantially to zero. In particular, the duty cycle correction Ad_;\j for a half-bridge 16 may be determined from the respective deviation Dίi .,_\i , Dίi . ,\2 of the actual half-bridge output current with proportional control.

Only P-l deviations need to be determined, since the duty cycle correction Ad_;\i> of one half-bridge may be determined from the other ones. The duty cycle correction Ad_;\i> of one half-bridge 16 of a phase branch 12A, 12B, 12C, 12N may be determined from the sum of the duty cycle corrections Ad_Aj of the other half-bridges 16 of the phase branch 12A, 12B, 12C, 12N. In such a way, only P-l controllers 48 may be required for the current balancing controller 42 of one phase branch 12A, 12B, 12C, 12N.

Fig. 5 shows a hybrid transformer 52, in which an electrical converter 10 as described above may be employed.

The hybrid transformer comprises a primary side winding arrangement 54 connected to a medium voltage grid 56. The primary side winding arrangement 54 comprises delta- connected windings 58, which are electrically coupled with windings 60 of a secondary side winding arrangement 62. The secondary side winding arrangement 62 is connected to a low voltage grid 64 and is star-connected via the electrical converter 10, in particular via its phases A, B, C.

An auxiliary winding arrangement 66 with delta-connected windings 68 that are electrically coupled with the primary side winding arrangement 54 supplies a converter 70, for example a rectifier, with power from the grid 56. The converter 70 provides a DC voltage for the DC link 14 of the electrical converter 10.

It may be that the controller 22 of the electrical converter 10 additionally provides measured and/or calculated grid currents, grid voltages and power flow of one or both of the grids 56, 64 to a data storage and/or post-processing unit via connection to a communication network, such as the Internet. Fig. 6 and 7 show experimental results for the generated currents either without (Fig. 6) or with (Fig. 7) current balancing control as described above. In both figures, the paralleled and/or half-bridge output currents i i ._{A i} , IL,A2, IL,A3 for a phase branch 12A with P=3 half- bridges 16 are shown. As can be seen, with current balancing control, the half-bridge output currents IL,A P .L2, IL,A3 stay within predefined bounds.

Both Fig. show that a voltage ripple 72 produced either without or with the current balancing control stays the same.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art and practising the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word“comprising” does not exclude other elements or steps, and the indefinite article“a” or“an” does not exclude a plurality. A single processor or controller or other unit may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

LIST OF REFERENCE SYMBOLS 10 electrical converter

12A phase branch

12B phase branch

12C phase branch

12N phase branch

14 DC link

CDC DC link capacity

16 half-bridge

A phase output

B phase output

C phase output

D phase output

18 midpoint

20A upper semiconductor switch

20B lower semiconductor switch

22 controller

24 electrical filter

C_A filter capacitor

C_B filter capacitor

Cc filter capacitor

C_N filter capacitor

L filter inductance

VA phase voltage

VB phase voltage

Vc phase voltage

VN phase voltage

iL,Aj half-bridge output current i_L,Bj half-bridge output current iL,cj half-bridge output current i_L,Nj half-bridge output current

26 switchable semiconductor device

28 first control part

30 second control part 32 outer voltage controller, outer control loop

34 inner current controller, inner control loop

36 duty cycle generator

38 pulse width modulator

40A ABC-dqO transformer

40B ABC-dqO transformer

40C ABC-dqO transformer

40D dqO-ABC transformer

42 current balancing controller

44 adder

V_ABC phase voltage vector

V_ABC ⁰ actual phase voltage vector

V _dqo° transformed phase voltage vector

Vdqo* reference phase voltage vector

Vi, _ABC ^* setpoint phase signal vector

io,ABC filtered phase current vector

io,ABC° actual filtered phase current vector io,dq0° transformed filtered phase current vector iL,d_qo* setpoint phase current vector

i_L,ABC° actual phase current vector

i _dqo⁰ transformed phase current vector

V i,_dqo^* transformed setpoint phase signal vector d_A phase duty cycle

dis phase duty cycle

dc phase duty cycle

d_N phase duty cycle

d_Aj half-bridge duty cycle

dis_j half-bridge duty cycle

dq half-bridge duty cycle

d_Nj half-bridge duty cycle

Ad_Aj duty cycle correction

Adii_j duty cycle correction

Adq duty cycle correction

Ad_Nj duty cycle correction iL,Aj° actual half-bridge output current i_L,Bj° actual half-bridge output current i c_j ⁰ actual half-bridge output current iL,Nj° actual half-bridge output current

46 averager

48 proportional/proportional integral controller

50 difference part

i i _{. L} ° averaged half-bridge output current

DI_I .L I deviation of half-bridge output current

D i r _;\2 deviation of half-bridge output current

52 hybrid transformer

54 primary side winding arrangement

56 medium voltage grid

58 winding

60 winding

62 secondary side winding arrangement

64 low voltage grid

66 auxiliary winding arrangement

68 windings

70 converter

72 voltage ripple

Claims

1. A method for controlling an electrical converter (10),

wherein the electrical converter (10) comprises at least two phase branches (12A, 12B, 12C, 12N), each phase branch comprising at least two half-bridges (16), which are connected in parallel to a DC link (14) and which are connected via midpoints (18) for providing a phase output (A, B, C, N) for the phase branch;

the method comprising:

determining setpoint phase signals (V_I.AISC ) for the phase branches from actual phase voltages (VABC⁰) and actual phase currents (IL,ABC⁰), which are determined from measurements, and from reference phase voltages (V_dqo^*) for the phase branches (12A, 12B, 12C, 12N);

determining a phase duty cycle (d_A, dn, dc, d_N) for each phase branch (12A, 12B, 12C, 12N) from the setpoint phase signals (V_I.AISC );

determining a half-bridge duty cycle (d_Aj, du_j, dq, d_Nj) for each half-bridge (16) by adding a duty cycle correction (Ad_Aj, Adis,, Adq, Ad_Nj) for the half-bridge (16) to the phase duty cycle (d_A, de, dc, d_N) for the phase branch (12A, 12B, 12C, 12N) to which the half bridge (16) belongs, wherein the duty cycle correction is determined from actual half-bridge output currents (ii..Aj°, ii .is_j ⁰, ii..q°, ii .\j°) of the half-bridges (16) of the phase branch, which actual half-bridge output currents fir_.. _Aj ⁰ , ii .is_j ⁰, ii_..q°, ii ._\j°) are determined from measurements;

switching semiconductor switches (20A, 20B) of the half-bridges (16) based on the respective half-bridge duty cycle (d_Aj, du_j, dq, dq), wherein the half-bridges (16) of a phase branch (12A, 12B, 12C, 12N) are switched to generated half-bridge output currents (iq_Aj^ iq_Bj, ii .q, iqq) summing up to the actual phase current of the phase branch (12A, 12B, 12C, 12N).

2. The method of claim 1,

wherein the duty cycle correction (AdA_j) for a half-bridge (16) is determined from a deviation (Ai i .,,_\j ) of an actual half-bridge output current (iqA_j ⁰) from an averaged half bridge output current (I _I ._A ), which averaged half-bridge output current is the sum of the actual half-bridge output currents (iqAj⁰) of the respective phase branch (12A, 12B, 12C, 12N), the half-bridge (16) belongs to, divided by the number of half-bridges (16) of the respective phase branch (12A, 12B, 12C, 12N); wherein the duty cycle correction (Ad_;\j) is determined from the deviation (Dίi ._L, ) of the actual half-bridge output current (iL,Aj°) with ^at least one of proportional and proportional integral control (48).

3. The method of claim 1 and 2,

wherein the half-bridges (16) of a phase branch (12A, 12B, 12C, 12N) are switched to generate interleaved half-bridge output currents (U .AJ, iL,Bj,

4. The method of one of the previous claims,

wherein the duty cycle correction (Ad_;\i>) of one half-bridge (16) of a phase branch (12A, 12B, 12C, 12N) is determined from the sum of the duty cycle corrections (AdAj) of the other half-bridges (16) of the phase branch (12A, 12B, 12C, 12N).

5. The method of one of the previous claims,

wherein the actual phase current (IL,ABC⁰) for a phase branch (12A, 12B, 12C, 12N) is determined by adding (44) the determined actual half-bridge output currents (U .AJ⁰, iL,B_j°, i_L,C_j ⁰) of the half-bridges (16) of the respective phase branch (12A, 12B, 12C, 12N).

6. The method of one of the previous claims,

wherein the setpoint phase signals (V_I.ABC ) are determined with an outer voltage control loop (32) and an inner current control loop (34);

wherein the reference phase voltages (V_dqo^*) and the actual phase voltages (VABC⁰) are input into the voltage control loop (32) for determining setpoint phase currents (i i .dqo*); wherein the setpoint phase currents (i i .dqo*) and the actual phase currents (IL,ABC⁰) are input into the current control loop (34) for determining the setpoint phase signals (V_I.ABC ).

7. The method of claim 6,

wherein actual filtered phase currents (io,ABC°) determined from current measurements after an electrical filter (24) connected to the phase outputs (A, B, C) are additionally input to the voltage control loop (32) for determining the setpoint phase currents

(lL,dq0^*).

8. The method of one of the previous claims,

wherein the actual phase voltages (V_dqo°) and the actual phase currents (i_L,_dqo°) are transformed into a dq-system;

wherein the setpoint phase signals (VLABC ^*) are transformed into an ABC-system before the phase duty cycles (dA, du, dc, dN) are determined.

9. A controller (22) for an electrical converter (10) adapted for performing the method of one of the previous claims.

10. An electrical converter (10), comprising:

at least two phase branches (12A, 12B, 12C, 12N), each phase branch (12A, 12B, 12C, 12N) comprising at least two half-bridges (16), which are connected in parallel to a DC link (14) and which are connected via midpoints (18) for providing a phase output (A, B, C, N);

a controller (22) according to claim 9.

11. The electrical converter (10) of claim 10, further comprising:

four phase branches (12A, 12B, 12C, 12N) including a phase branch (12N) for providing a neutral point voltage (VN).

12. The electrical converter (10) of claim 10 or 11,

wherein the midpoints (18) of the half-bridges (16) of one phase branch (12A, 12B, 12C, 12N) are connected via inductances (L) with the phase output (A, B, C, N) of the phase branch (12A, 12B, 12C, 12N);

wherein a passive electrical filter (24) interconnects the phase outputs (A, B, C, N) of the phase branches (12A, 12B, 12C, 12N).

13. The electrical converter (10) of one of the previous claims,

wherein a semiconductor switch (20A, 20B) of a half-bridge (16) is composed of at least two semiconductor devices (26) connected in parallel with electrically interconnected gates;

wherein the semiconductor devices (26) are GaN transistors.

14. A hybrid transformer (52), comprising:

a primary side winding arrangement (54) connectable to a first electrical grid (56); a secondary side winding arrangement (62) connectable to a second electrical grid (64) ;

an electrical converter (10) according to one of the claims 10 to 13;

wherein phase outputs (A, B, C) of the electrical converter (10) are series-connected with windings (60) of the secondary winding arrangement (62).

15. The hybrid transformer (52) of claim 14,

wherein the first electrical grid (56) is a medium voltage grid and the second electrical grid (64) is a low voltage grid.