EP3718215A1 - An interleaved sigma delta modulator based sdr transmitter - Google Patents
An interleaved sigma delta modulator based sdr transmitterInfo
- Publication number
- EP3718215A1 EP3718215A1 EP18883155.6A EP18883155A EP3718215A1 EP 3718215 A1 EP3718215 A1 EP 3718215A1 EP 18883155 A EP18883155 A EP 18883155A EP 3718215 A1 EP3718215 A1 EP 3718215A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- dem
- bits
- dacs
- encoders
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
- H03M3/502—Details of the final digital/analogue conversion following the digital delta-sigma modulation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
- H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
- H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
- H03M3/466—Multiplexed conversion systems
- H03M3/468—Interleaved, i.e. using multiple converters or converter parts for one channel, e.g. using Hadamard codes, pi-delta-sigma converters
- H03M3/47—Interleaved, i.e. using multiple converters or converter parts for one channel, e.g. using Hadamard codes, pi-delta-sigma converters using time-division multiplexing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/662—Multiplexed conversion systems
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/14—Conversion to or from non-weighted codes
- H03M7/16—Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code
- H03M7/165—Conversion to or from thermometric code
Definitions
- Transmitters are an indispensable component for radios, which have been used in cellular phones, indoor wireless local area networks (LAN) and wireless controllers. Due to emerging multi-mode and multi-band applications, a transmitter with wide-band coverage becomes necessary. Many applications require transmitters to switch rapidly between frequency bands, which impose a significant challenge to the transmitter solution.
- a variety of wide-band transmitters are known. However, some of these include local oscillator (LO) based transmitters.
- LO local oscillator
- the switching time of the LO based transmitter is often determined by the LO channel switching time under the governance of the loop bandwidth of the frequency synthesizer, which is typically around 1 MHz.
- the achievable channel switching time is several micro seconds which is too long of a time to be used in an agile radio application.
- PWM Pulse-W idth-Modulation
- DDS Direct Digital Synthesizers
- PLL Phase-locked loop
- FIG. la illustrates such a bandpass delta-sigma-modulator (BDSM) 10 receiving an RF input 12 as part of an RF transmitter 1 logic.
- a common clock 14 drives the BDSM 10 and the modulated output of the BDSM 10 is amplified through a Power Amplifier (PA) 16 and passed through a bandpass filter 18 before being transmitted.
- PA Power Amplifier
- the BDSM 10 in Figure la cannot provide a very high dynamic range and / or wide-band operation due to a moderate clock frequency driving the BDSM 10.
- the clock frequency is constrained by technology and becomes a limiting factor in providing a high dynamic range or a wide-band operation in these transmitters.
- the limited dynamic range of such systems due to the limiting sampling clock rate does not meet even today’s needs for narrow-band applications.
- DAC Digital-to-Analog Convertor
- This IF signal 108 is taken through a Band Pass Filter (BPF) 110 and up-converted by a 60 GHz carrier frequency before being amplified by a PA 112 and transmitted via antenna 117.
- BPF Band Pass Filter
- the architecture of Figure lb requires up conversion to generate the RF carrier. Latencies in LO switching times and fixed RF filter components are still bottlenecks to achieving fast band switching and further limit the reconfigurability of and usefulness in software-defined radio applications.
- thermometer coded digital signal encodes and/or permutes two bits of a thermometer coded digital signal at its output.
- the two thermometer coded bits can comprise one of the elements in ⁇ 00, 01, 11 ⁇ and DEM encoding can be accomplished by either randomly 1) swapping or 2) leaving in place the elements at the output, i.e, mapping the elements to the set ⁇ 00, 01, 10, 11 ⁇ at the output, as can be seen in Figure lc.
- a 2-bit digital signal 120 is received by a DEM Encoder 121, which encodes and separates the two bits into two digital signal paths 122 and 123, each carrying one bit that was swapped or left in place.
- the two digital signal paths are each received in parallel by two nominally identical 1-bit DACs 124 and 125, which can each comprise a single current switch (not shown).
- the two digital signals are each converted to analog signals and combined with a summing circuit 126 to produce a single outputted analog signal 127. Because the signals are summed, swapping the bits at the input of the DACs does not produce a different combined analog signal if the components within the two pathways are identical.
- a typical 2 -bit DEM would, when one of the bits of a 2- bit data signal is 1 and the other 0, either swap the bits or not swap the bits in a random, decision-making manner. Swapping them would change the sign of the mismatch error in the resulting analog signal when the digital signals are converted to analog and summed by the summing circuit.
- This sign in the mismatch error which is here called s[n], can be generalized to be either +1, -1 or 0,
- the mismatch error can then be defined as:
- the equation above for a mismatch error contains the variable e DAC [n], which is either positive definite, or negative definite in this definition, and the variable’s magnitude is equal to the magnitude of the mismatch error.
- the number [n] in this context is the sample number.
- the purpose of a DEM encoder is to alter the variable s[n] such that it is uncorrelated with the input of the 2 bits at the DACs, which will be described in more detail in the following paragraph.
- the sign s[n] - 0 could be interpreted as the bits either 1) not being switched and/or 2) not being considered by the DEM encoder, and possibly re-routed around its components.
- s[2] 0, which corresponds to input [2] - 00.
- the two bits in input [2] are identical and they can either be not considered by the DEM encoder and re-routed around or within its components or they can be considered and not switched.
- the determination as to whether switching occurs or not for a given input[n] can be determined by the design of the DEM encoder. The determination can be described by one or a combination of the sequences of 1) switching at a first instance of an input 01 or 10 and not switching at the second instance thereof, 2) not switching at a first instance of an input 01 or 10 and switching at the second instance thereof, 3) a combination or sequence of these sequences, or 4) no apparent sequence, with a random selection of switching or not switching.
- the DEM encoder system can comprise multiplexers flip-flops, random or pseudorandom bit generators, transistors, switches, and logic gates such as XOR gates, OR gates, NOR gates, XNOR gates, AND gates, NAND gates, NOT gates, etc.
- the DEM encoder system can comprise a programmable circuit such as a Field-Programmable Gate Array (FPGA).
- FPGA Field-Programmable Gate Array
- the generalization of the above-simplified algorithm can be applied to higher order bits and can be realized by someone skilled in the art. This can be exemplified by using several 2-bit DEM encoders for an N-bit length data signal or by using an N-bit DEM encoder, which would swap or not swap bits or portions of the inputted N-bit data according to the design of the N-bit encoder.
- the field of multi-band, multi-mode RE transmitters is in need of modulating techniques that provide for wide-band operation with fast switching without requiring a very high sampling clock.
- an interleaved delta-sigma modulator comprising a set of interleaved filter banks, an interleaved DEM network, interleaved array(s) of DACs and a summing unit, wherein digital input data streaming from one or more processors is mapped to feed interleaved filter banks that drive the DEM network, then converted to analog signals by the interleaved arrays or banks of DACs and merged by the summing unit.
- a method of modulating a transmit signal comprising generating amplitude, frequency, and phases of digital data for one or more transmit signals with a processing unit, creating parallel interleaved pathways for the digital data, filtering the digital data through interleaved filter banks, routing the digital data through a DEM network, converting the data to analog signals through an interleaved bank of DACs and summing the analog signals from the various interleaved DAC banks.
- Certain embodiments may provide various technical capabilities depending on the implementation of the embodiment. For example, a technical capability of some embodiments may include the ability to provide additional tunable band pass filtering to reject out-of-band emissions. Other implementations may use binary-to-thermometer encoding and / or DEM algorithms to improve the effective signal-to-noise ratio of a modulator.
- Figure la illustrates a bandpass delta-sigma modulator based RF Transmitter according to prior art (Scheytt);
- Figure lb illustrates a time-interleaved DAC based RF Transceiver, according to prior art (Pham);
- Figures lc and Id illustrate an embodiment of a 2 ⁇ bit DEM DAC system and an associated graph of the output of the system, according to a prior art (Galton, Ibid).
- Figure 2 illustrates an interleaved delta-sigma modulator based RF transmitter architecture, according to an embodiment of the present writing
- Figure 3 illustrates a detailed block diagram of Figure 2, according to an embodiment of the present writing
- Figure 4 illustrates a binary-to-thermometer encoding table representative of the outputs of one of the binary-to-thermometer encoders of Figure 3;
- Figure 5 illustrates an implementation of the code mapping of Figure 4.
- Figure 6 illustrates an interleaved, dynamic, element-matching network after mapping in Figure 3, according to an embodiment of the present writing
- Figure 7 illustrates an implementation of a crossbar switch grid and a linear feedback shift register for interleaving received data according to an embodiment of the present writing
- Figure 8a illustrates an implementation of an interleaver or a dynamic routing network with a collection of switches and a DEM encoder at a first time, according to an embodiment of the present writing.
- Figure 8b illustrates an implementation of an interleaver or a dynamic routing network with a collection of switches and a DEM encoder at another time according to an embodiment of the present writing.
- Figure 9 illustrates an implementation of a portion of the current switch bank 326 as first indicated in Figure 3, according to an embodiment of the present writing.
- this writing provides several embodiments for an interleaved, delta-sigma modulator for a rapidly switching multi-mode, wide-band transmitter architecture.
- This writing also presents a novel, software-defined, transmitter architecture based on an interleaved, delta-sigma modulator to generate RF signals.
- the proposed architecture leverages interleaving concepts to allow the relaxation of subcomponent clock rates without changing the effective oversampling ratio, thus, making it easier to reach aggressive dynamic range goals across wider bandwidths at higher frequencies.
- Some of the features of the proposed technology include: time-interleaving delta- sigma modulator DAC configurations to enable a high-dynamic-range operation at high RF carrier frequencies; a DEM algorithm to randomize mismatch errors across all interleaved paths; and a tunable bandpass filter to further reject out-of-band emissions.
- the word“permute” can take on the definition“submit to a process of a permutation”, wherein the word“permutation” takes on the definition“an arrangement or rearrangement of the elements of a set”, wherein permuting the elements can yield the originally ordered elements of the set, but can also not yield the originally ordered elements of the set.
- permuting the bits in the set ⁇ 0,1 ⁇ can yield ⁇ 1 ,0 ⁇ or ⁇ 0,1 ⁇ .
- a DEM encoder has inputs labeled inputO and input 1 , and the DEM encoder is inputted with a digital signal having bits with the order ⁇ 0,1 ⁇ at inputO and input 1 (or perhaps at a single input carrying both bits), respectively, its output is a permutation of the inputted bits. Therefore, it can be one of: ⁇ 1,0 ⁇ or ⁇ 0,1 ⁇ , at the outputs labeled outputO and output 1 , wherein its inputs have a one-to-one correspondence with its outputs.
- the bits outputted by the DEM encoder are defined as “permuted bits”.
- the identity permutation, or the permutation that leaves the order of the bits unchanged, can be accomplished in various ways known in the art of DEM encoding.
- the permuted bits are received by the DAC and the DAC converts the permuted bits according to the permutation thereof such that different permutations activate different converting elements within the DAC.
- the permuted bits are converted to a corresponding analog signal by the DAC.
- the use of the language“digital signal having bits” means a digital signal representing more than one bit.
- the digital signal should be interpreted in the broadest way possible and can be embodied as an electrical signal, optical signal, etc., virtually any type of signal or physical quantity conveying information in a form representing or having quantized values or bits.
- a single digital signal can be transmitted, transported, or conveyed in a variety of ways such as in: a single path or multiple paths. If a digital signal is transmitted or received via multiple paths, it is understood that the bits transmitted or received via multiple paths can form an ordered sequence or arrangement, which represents digital information.
- an interleaved, delta-sigma-modulator-based RF transmitter architecture system 200 is disclosed. Herein, it will be often referred to simply as a “transmitter” or“system”.
- the main blocks of the transmitter 200 are a digital signal processing unit 210 that provides low-speed digital modulation data to an interleaved bandpass delta-sigma digital-to-analog converter (DAC) 220, which generates a RF carrier signal from modulation data and shapes noise away from the carrier signal to achieve a desired dynamic range performance within the signal band.
- DAC digital-to-analog converter
- the signal proceeds from the DAC 220 to summation block or summing circuit 230 described in greater detail below.
- An optional, tunable bandpass filter 240 can be included to filter the signal to reduce out-of-band emissions.
- the RF carrier signal is amplified by a power amplifier (PA) 250 for broadcasting through an antenna 260.
- PA power amplifier
- the interleaved delta-sigma modulator based RF transmitter architecture system 200 of Figure 2 effectively increases the clock rate of the system and boosts the oversampling ratio, which in turn improves the achievable signal-to-noise ratio and the dynamic range of the system.
- unit 225 is a clock dividing unit.
- an interleaving DEM algorithm can be used, Unlike a conventional DEM algorithm that arranges the bits in cells in one DAC, the interleaving DEM algorithm must consider bits in cells routed to all of tire interleaving DACs and route the bits in cells to ensure that there is no periodic pattern of routed pathways or encoded digital bits within those cells.
- the core of the interleaved delta-sigma modulator based RF transmitter architecture system 200 is the bandpass delta-sigma DAC 220 and the interleaving that there occurs achieves remarkable dynamic range performance over wideband operation.
- a block diagram of the bandpass delta-sigma DAC 220 of Figure 2 is shown in more detail in Figure 3.
- DSP 210 from Figure 2 provides digital information to a filter block 322 which is a parallel, noise-shaping digital filter comprised of parallel infinite impulse response (HR) filters 320 followed by time- interleaved noise shaping loop filters integral therein.
- HR parallel infinite impulse response
- the parallel noise-shaping digital filter that is filter block 322 comprises a K-to-M multiplexer 321 that multiplexes K inputs into M outputs of N bits each.
- the output of the filter block 322 is multiple IF data sets of N-bit wide vectors where M is the interleave factor and N is the number of DAC bits. N can vary from vector to vector, though it is fixed in the preferred embodiment.
- the M is determined by the limitations of technology and packaging limitations. How many parallel paths can be used is determined by the hardware limitations of the technology. For example, in today’s CMOS technology, a factor of (M-) 2 to 32 is easily achievable, and M usually takes on a value of 2 1 , 2 2 , 2 3 , etc.
- an“input” is defined as a coupled path that receives a collection of bits in a certain arrangement.
- An“output” is defined as a coupled path that outputs a collection of bits in a certain arrangement.
- Each one of the M data sets is processed along the transmit chain in parallel and sampled at equal sub-phases of a clock with frequency F CLK /M as seen in Figure 3 with clock dividing circuit 225.
- the binary information in each data set is first converted to thermometer code by binary-to-thermometer encoders in block 323 and then scrambled or permuted by a DEM encoder/unit in the DEM network 324 comprising M blocks of DEM units to reduce mismatch errors.
- DEM(l) for example, receives 2 N bits outputted from HR Filter (1), and outputs a permutation of the 2 N bits.
- the 2 N bits are then dynamically routed with the interleave control unit 328 to a 2 N -bit DAC of current switch bank 326.
- the interleaving DEM algorithm must consider the cells used in all of the interleaved paths and arrange them to ensure that there is no periodic pattern. That is, the interleaving DEM algorithm must scramble (or shuffle) the digital bits present within a digital signal and interleave the digital signals with scrambled bits into a set of pathways to ensure that there is no periodic pattern of routed pathways or digital bits within those pathways.
- the binary-to-thermometer encoder block 323 converts each data set of N bits to corresponding data sets of 2 N bits. Hence, at the output of the binary-to ⁇ thermometer encoder block 323, each data set is 2 N bits in width or size.
- Each thermometer coded data set is passed through a DEM encoder of DEM network 324 to then be interleaved with interleave control 328 and routed to current switch bank 326.
- the thermometer code drives a bank of unit current switches in current switch bank 326 to generate a representative analog current value.
- the current switch bank 326 operates at a frequency of F C LK M and comprises M banks of 2 N 1 bit - DACs that convert the digital signals to the analog domain. This is shown in Figure 6 discussed in more detail in later paragraphs.
- the DEM network 324 acts to scramble the bits in this portrayal.
- the parallel noise-shaping digital filter 322 of Figure 3 can be programmed to have single or multiple passing/rejection bands to support single or multiple carrier signals for 4G LTE standards. Since the filter coefficient is programmable, this architecture is suitable to support the next generation carrier requirements with proper software upgrading.
- Figure 4 illustrates a typical binary-to-thermometer table that is representative of the outputs of the binary-to-thermometer encoder block 323 of Figures 2 and 3.
- the logic block 500 of Figure 5 illustrates a typical implementation of the code mapping of Figure 4, which maps an N-bit vector to a 2 N -bit vector.
- a binary-to-thermometer encoder can comprise any implementation of a set of logic gates or a programmable circuit to obtain the mapping of Figure 4.
- the logic block 500 decodes binary code B0:3 to Tl : 15. TO (not shown) is active when B0:3 are all zeroes.
- DACs typically comprise nominally matched components such as resistors, capacitors, current switches, transistors, and analog-to-digital converters (ADCs). Manufacturing processes often cannot generate components, which have identical electrical properties. Further, temperature differences between components (perhaps due to their positions relative to each other or other components) can also cause them to operate differently. The need to deal with such differences is present. The component value deviations, (called mismatch errors), create DAC signal conversions with mismatch errors. DEM algorithms dynamically rearrange the interconnections or couplings to the matched and mismatched components of, for example a DAC, so that any possible interconnection is available during the process of a signal conversion.
- ADCs analog-to-digital converters
- a DEM encoder works to dynamically and possibly randomly activate converting elements within a DAC. If the matched and mismatched components’ activations are appropriately varied, the harmonic distortion caused by the mismatched components can be reduced and the frequency can be shifted or eliminated. These components, often referred to as “cells”, are dynamically rearranged using different DEM algorithms.
- Interleave control 328 which provides a second level of DEM as distinguished from the DEM encoders that permute bits, can involve a crossbar switch grid 620 or 726 as seen in Figures 6 and 7 respectively, or the collection of switches 820 as seen in Figures 8a and 8b.
- the latter cooperates with DEM encoder 810, the former cooperates with Linear Feedback Shift Register (LFSR) 724.
- LFSR Linear Feedback Shift Register
- DEM encoder 810 in the interleave control 328 is used to reroute bits rather than scramble them as is done in the DEM encoders of the DEM 324 in Figure 3.
- the M DEM encoder outputs (and in one embodiment, inputs) of the DEM network 324 are routed with the interleave control unit 328.
- the interleave control unit 328 scrambles the paths at grid 620 going to or from the DEMs in DEM network 324 to reduce mismatch error.
- the interleaving DEM algorithm of 620 must consider the cells used in all of the interleaved paths and arrange them to ensure that there is no periodic pattern of interconnections.
- the M sets of 2 N digital bits are dynamically routed with the interleave control and converted to analog signals by the DACs in the current switch bank 326 which comprise unit cells of 1 -bit DACs as earlier noted.
- LFSR 724 receives a seed that generates pseudo random bits to control a crossbar switch grid 726.
- the pseudo random bits are used to control multiplexing in the signal propagation path and to provide randomness to the propagation paths.
- the scrambling of the bits helps randomize the mismatch noise so that the mismatch noise can be effectively filtered out.
- the interleaving in the DEM algorithm accounts for the cells used in all of the interleaved paths and arranges them to ensure that there is no periodic pattern of pathways or couplings to the DACs.
- M DEMs coupled to B binary-to- thermometer encoders, wherein M is not necessarily equal to B and B can be zero, equal to M or even greater than M.
- the number M is at least one.
- the B binary-to-thermometer encoders encode a plurality of digital signals substantially or fully in parallel, though the number of digital signals being thermometer encoded is not necessarily equal to B and can be at least one or any number up to B.
- One embodiment can include configuring only a portion of all of the DEMs to operate at any given time, with some digital samples or a portion of the digital samples being unchanged or not considered by any DEM encoders throughout an operation of the transmitter at a given instance.
- the portion of DEM encoders that operate at any given time can be dynamically changed from sample to sample of digital signals.
- the M DEM encoders do not operate identically and, for example, each can be configured to operate on digital data of varying length or constant length and each can uniquely scramble or shuffle the digital data in a digital signal.
- Each DEM can be designed with a unique combination of components or algorithms.
- the M DEMS are designed with nominally identical components and algorithms and all operate on M digital signals of the same length substantially or fully in parallel, though it should be restated that the number of available DEMS can be larger than the number of digital signals that are being operated on substantially or fully in parallel.
- a digital signal or digital data can be of a certain length of bits.
- the digital signals of a certain length can each be at least two bits, though they can be one bit or much larger.
- the larger the size of a digital signal the greater the complexity in the corresponding binary-to-thermometer encoder used to facilitate the mapping of that digital signal to thermometer code. This greater complexity can come in the form of a larger number of components and interconnections in the binary-to-thermometer encoder.
- the term “parallel” used herein refers to the parallel arrangement of the digital signals, digital signal pathways, DEM encoders, or potentially any other components comprised by the transmitter such that the digital signals in all pathways propagate at the same clock rate, nearly the same clock rate, a factor of a given clock rate, or nearly a factor of a given clock rate.
- two digital signals are propagating in parallel if they are being routed towards two DACs and one signal is propagating at double the clock rate the second signal is propagating. They are propagating in parallel if one signal is propagating at nearly double the clock rate the second signal is propagating.
- interleaver 328 in this writing can be referred to as an interleave system, dynamic coupler, coupler, interleave control, dynamic router or a dynamic router network and can be embodied as a number of different units.
- the interleaver can be a dynamic routing network comprised of a collection of switches 820 or a crossbar switch grid 620, 726.
- the collection of switches 820 can be controlled with the LFSR 724, as in Figure 7, that generates randomized switch selector bits to turn on and turn off certain switches for routing the digital signals in parallel.
- the collection of switches can also be controlled by DEM encoder 810, which is discussed hereunder.
- the collection of switches can comprise transistors, metal wires, relays, mechanical switches, thermal switches, optical switches, and virtually any conceivable embodiment of a collection of switches. A portion or all of the switches can be controlled in a randomized or pseudo randomized manner.
- the interleaver dynamically routes M digital signals to M signal pathways that are coupled to DACs. The total number of available signal pathways to the DACs can be greater than M. The total number of available DACs can be greater than M and they may not all be utilized at any given time.
- a collection of digital signals ⁇ /n 0 , Ih ⁇ , In 2 ) can be mapped to three of the signal pathways in ⁇ Out Q Out 1 , Out 2 , Out 3 , Out 4 ⁇ according to a randomized method or non-randomized method. Since two of the signal pathways are not utilized, their corresponding coupled DACs are not utilized and thus, do not receive digital signals.
- the signal pathways that receive the digital signals are non-dynamically coupled to corresponding DACs in one embodiment.
- the interleave control unit 328 is configured such that the digital signals are interleaved or dynamically routed before they are encoded by the DEM encoders of DEM network 324, wherein the DEM encoders receive dynamically routed digital signals and subsequently encode them.
- the interleaver unit is configured such that the digital signals are interleaved or dynamically routed after they are encoded by the DEM encoders.
- the DEM encoders receive thermometer encoded digital signals before the DEM-encoded digital signals are received by the DACs.
- a more complex algorithm could entail dynamically selecting between 1) DEM encoding the digital signals and then interleaving the DACs with the digital signals or 2) interleaving digital signal pathways with the collection of switches and then DEM encoding the digital signals.
- the only embodiment shown in the drawings is with the signals going to the Dynamic Element Matching Network 324 first before being interleaved, but this is not a limiting situation and can be changed as here noted.
- FIGS 8a and 8b illustrate an implementation of an interleaver or a dynamic routing network wherein the bits l’s and 0’s within the boxes represent on and off switches 820 that are configured to dynamically couple each input to a corresponding output.
- bits 1 :N from In 0 are all routed to Out 0 .
- This method is carried through to all inputs such that bits 1 :N from an input /n are all routed to an output Owt;.
- Figure 8b illustrates, in perhaps another point in time or sampling, a collection of switches 820 that have dynamically been selected to turn off and turn on by a control unit, and to re-route the inputs to another set of outputs.
- bits 1:N from input !n 0 are all routed to output Out .
- Bits 1:N from input ln 2 are all routed to Out 0 .
- the number of bits N could vaiy from input to input, though N bits enter an input of the interleaver and the same number of N bits output the interleaver.
- the interleaver does not scramble the bits 1 :N in a single path; it merely re-routes them in order.
- the interleaver however, can become more complex and re-route a portion of a digital signal, bits 1 :M to one path and the other bits M+1 :N to another path using two switches and recombine their signals at the DAC stage.
- Controlling of the interleaver can be implemented using a DEM encoder 810 to control the collection of switches 820 in the interleaver or the dynamic routing network, as illustrated in Figures 8a and 8b, where the interleave system includes DEM encoder 810 and the collection of switches 820.
- the collection of switches 820 is coupled to P available output paths and M available input paths, wherein the amount of available output paths is not necessarily equal to the amount of available input paths, though they are equal in a practical embodiment.
- the amount of switches in one embodiment is P X M, though this is not strictly necessary and is dependent upon the complexity and design of each switch.
- a 2-bit DEM encoder works to swap or not swap two bits in a random decision-making manner and a combination of 2-bit DEM encoders can be configured to operate on N bits.
- a higher order bit DEM encoder can be used to swap, scramble or leave unchanged, the couplings of the input-output paths in a random decision-making manner or a manner according to a sequence of a random decision-making manner. Swapping two paths can amount to swapping bits or turning on and off certain switches in the collection of switches. Any combination of 2-bit or larger DEM encoders can be used to facilitate the swapping or scrambling of input-output paths.
- Each output of N bits is coupled to either corresponding DACs or N-bit DEM encoders for further encoding of the N bits.
- the interleaver of the present application therefore, introduces a higher level of DEM encoding to the processing of the digital signals therein.
- FIG. 9 is a portion of the switch bank 326, there is seen a collection of 2 N switches 1311 o- 1311 2 N that are coupled to corresponding current sources 1312o - 1312 2 N .
- the 2 N bits from the data signal are used to turn off or turn on the switches 131 IQ - 131 1 2 N to the current sources 1312Q-1312 N -
- two switches 131 2 and 1311 3 could be turned on to generate an analog signal generated from two current sources for that data signal.
- the current sources are the symbols labeled by 1312, ⁇ and a single current switch can be defined as the combination of, for example, switch 1311; and current source 1312;.
- the outputs of the M 2 N bit DACs are received at the summing circuit 230 in Figure 3, which further processes the M analog signals generated from the M DACs.
- the summing circuit 230 can use any scheme known in the art, such as NRZ or RZ modulation techniques.
- the clock -dividing unit 225 provides the frequency F CLK /M to the current switch bank 326.
- the current switch bank 326 of Figure 3 can comprise a collection of 1-bit DACs, and can be configured to convert a digital signal of a certain length to an analog signal using a series of current switches.
- the number of 1-bit DACs is equal to the size of the digital signal being converted to analog, i.e., the number of bits carried in that digital signal, though the amount of available 1 -bit DACs can be greater than the size of the digital signal.
- a 1 ⁇ bit DAC can be embodied as a single current source switch as seen in Figure 9. Each digital bit in a digital signal turns on or turns off a switch 1311; in the current switch bank 326 and an analog signal is generated by the resulting combined current wherein the combined current is representative of or corresponds to the digital signal.
- the plurality of DACs in the switch bank 326 can also be any collection of DACs, segmented or not segmented, and can comprise binary-weighted DACs and thermometer-coded or unary DACs, or a hybrid thereof.
- These DACs comprise current sources 1312 0 -1312/ coupled to switches 1311o-T 31 l 2 N wherein the current sources are not all identical and can include a pattern of current sources.
- a binary-weighted DAC comprises a series of varying resistors used to generate a specific series of current sources of varying currents.
- unary weighted bits would be scrambled independently of the binary weighted bits.
- An ideal unary DAC comprises a collection of identical switches coupled to identical current sources.
- the proposed technology provides for an interleaved, delta-sigma modulator for a rapidly switching multi-mode, wide band transmitter architecture in the various fields of communications and this technology will benefit in the areas of ground radio, software defined radio (SDR), smart radio, cognitive radio, in-vehicle communications, in-car/in-plane infotainment systems, compact automobile sensors etc.
- This technology also provides for novel software defined transmitter architecture based on an interleaved delta-sigma modulator to generate RF signals in the field of radio transmitters among other benefits.
- tunable band pass filters at the output of the delta-sigma modulator.
- the tunable filter can be omitted.
- a general purpose processor can be used instead of the DSP to feed the delta-sigma modulator. This concept can be used with additional pre-processing or additional filtering as needed for various applications.
- a Delta-Sigma modulator architecture uses interleaving and dynamic matching algorithms to address the needs of multi-mode, multi-band high bandwidth transmitters.
- the proposed architecture also supports a novel software defined transmitter architecture based on an interleaved Delta-Sigma modulator to generate RF signals.
- the proposed architecture leverages interleaving concepts to relax subcomponent clock rates without changing the effective oversampling ratio, thus, making it easier to reach aggressive dynamic range goals across wider bandwidths at higher frequencies.
- the DEM algorithm helps to randomize mismatch errors across all interleaved paths and improves substantially the signal -to-noise ratio. Additionally, a tunable bandpass filter can be added to reject out-of-band emissions.
- a transmitter comprising:
- a dynamic element matching (DEM) system having an output, wherein the DEM system is configured to receive bits of data and output a permutation of the bits of data at its output; at least two digital-to-analog converters(DACs) each having an input and output; a coupler, wherein the coupler is configured to couple the input of at least one of the DACs of the at least two DACs to the output of the DEM system, and wherein the at least one of the DACs is configured to output an analog signal corresponding to the permutation of the bits of data.
- DEM dynamic element matching
- the transmitter of concept 1 further comprising a summing circuit having inputs coupled to the outputs of the at least two DACs, wherein:
- the DEM system comprises more than one DEM encoders and wherein the number of DACs is at least equal to the number of DEM encoders, such that each DEM encoder of the more than one DEM encoders has an output, and the more than one DEM encoders receive the bits of data and output permutations of the bits of data at corresponding outputs;
- the coupler couples the inputs of the DACs to the outputs of the DEM encoders such that the DACs are interleaved and output the analog signals corresponding to the permutations of the bits of data;
- the coupler comprises a collection of switches that is configured to couple and uncouple the inputs of the DACs to the outputs of the DEM encoders.
- the coupler further comprises at least one DEM encoder coupled to the collection of switches, and wherein the collection of switches is controlled with the at least one DEM encoder, the at least one DEM encoder being configured to pseudorandomly and dynamically turn on and turn off selected switches of the collection of switches to couple and uncouple the inputs of the DACs to the outputs of the DEM encoders.
- the coupler further comprises a linear feedback shift register (LFSR) coupled to the collection of switches, wherein the collection of switches is controlled with the LFSR configured to output pseudorandomized switch selector bits configured to turn off and turn on selected switches of the collection of switches to couple and uncouple inputs of the DACs to the outputs of the DEM encoders.
- LFSR linear feedback shift register
- binary-to-thermometer encoders having inputs and outputs, the outputs being coupled to the inputs of the more than one DEM encoders and wherein the bits of data are thermometer encoded by the binary-to-thermometer encoders;
- each DAC of the at least two DACs is a unary DAC comprising more than one 1-bit DACs.
- IIR filters having inputs, with outputs coupled to the inputs of the binary to thermometer encoders, the IIR filters comprising noise-shaping loop filters and being configured to have multiple passing and rejection bands.
- the transmitter of concept 12 further comprising a K-to ⁇ M multiplexer with M outputs coupled to the inputs of the IIR filters.
- the summing circuit is a N on-Return -to-Zero (NRZ) summing circuit.
- NRZ N on-Return -to-Zero
- RZ Retum-to-Zero
- a transmitter comprising:
- a dynamic element matching (DEM) system comprising:
- DEM encoders having inputs and outputs, wherein the DEM encoders receive bits of data at the inputs and output permutations of the bits of data at corresponding outputs;
- the coupler couples the inputs of the at least two DACs to the outputs of the at least two DEM encoders, and wherein the DACs output analog signals corresponding to the permutations of the bits of data.
- a transmitter comprising:
- a dynamic element matching (DEM) system comprising:
- DEM encoders having outputs, wherein the DEM encoders receive bits of data and output permutations of the bits of data at corresponding outputs;
- At least two DACs having inputs coupled to outputs of the DEM encoders
- a coupler having inputs and outputs; the outputs of the coupler being coupled to the inputs of the at least two DEM encoders: wherein the coupler dynamically couples the inputs of the coupler to the outputs of the coupler, and wherein the DACs output analog signals corresponding to the permutations of the bits of data.
- a method for converting digital data to analog data comprising:
- the coupler comprises a crossbar switch grid configured to couple the input of the at least one of the DACs to the output of the DEM system.
- the transmitter of concept 1 further comprising a summing circuit having inputs coupled to the outputs of the at least two DACs;
- bits of data comprises sets of bits of data
- DEM system comprises more than one DEM encoder
- the number of DACs is at least equal to the number of DEM encoders
- the output of the DEM system comprises outputs of the DEM encoders such that each DEM encoder of the more than one DEM encoder has an output, and the more than one DEM encoder are configured to receive the sets of bits of data and output permutations of the sets of bits of data at corresponding outputs;
- coupler is configured to couple the inputs of the DACs to the outputs of the DEM encoders such that the DACs are interleaved and output the analog signals corresponding to the permutations of the sets of bits of data;
- the summing circuit is configured to combine the analog signals.
- a transmitter comprising:
- a dynamic element matching (DEM) system comprising:
- DEM encoders having inputs and outputs, wherein the DEM encoders are configured to receive sets of bits of data at the inputs and output permutations of the sets of bits of data at corresponding outputs;
- the coupler is configured to couple the inputs of the at least two DACs to the outputs of the at least two DEM encoders, and wherein the DACs are configured to output analog signals corresponding to the permutations of the sets of bits of data.
- a transmitter comprising: a dynamic element matching (DEM) system comprising:
- DEM encoders having outputs, wherein the DEM encoders are configured to receive sets of bits of data and output permutations of the sets of bits of data at corresponding outputs;
- At least two DACs having inputs coupled to outputs of the DEM encoders
- a coupler having inputs and outputs; the outputs of the coupler being coupled to the inputs of the at least two DEM encoders; wherein the coupler is configured to dynamically couple the inputs of the coupler to the outputs of the coupler, and wherein the DACs are configured to output analog signals corresponding to the permutations of the sets of bits of data.
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Application Number | Priority Date | Filing Date | Title |
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US15/828,106 US10361731B2 (en) | 2017-11-30 | 2017-11-30 | Interleaved sigma delta modulator based SDR transmitter |
PCT/US2018/053645 WO2019108301A1 (en) | 2017-11-30 | 2018-09-28 | An interleaved sigma delta modulator based sdr transmitter |
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EP3718215A1 true EP3718215A1 (en) | 2020-10-07 |
EP3718215A4 EP3718215A4 (en) | 2021-08-25 |
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EP18883155.6A Pending EP3718215A4 (en) | 2017-11-30 | 2018-09-28 | An interleaved sigma delta modulator based sdr transmitter |
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US (1) | US10361731B2 (en) |
EP (1) | EP3718215A4 (en) |
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WO (1) | WO2019108301A1 (en) |
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US10958284B2 (en) * | 2019-07-17 | 2021-03-23 | Mediatek Inc. | Time-interleaved digital-to-analog converter with time-domain dynamic element matching and associated method |
US10848176B1 (en) * | 2019-10-01 | 2020-11-24 | Raytheon Company | Digital delta-sigma modulator with non-recursive computation of residues |
US11164542B1 (en) * | 2020-08-07 | 2021-11-02 | Wilbur Arthur Reckwerdt, Jr. | Image processing system for a digital display |
CN112383358B (en) * | 2020-11-11 | 2022-03-25 | 中国科学院上海微系统与信息技术研究所 | Integrated optical transceiver |
US11502717B2 (en) * | 2021-01-22 | 2022-11-15 | Qualcomm Incoporated | Multiple element mixer with digital local oscillator synthesis |
EP4312376A1 (en) * | 2022-07-28 | 2024-01-31 | Nxp B.V. | Circuit with two digital-to-analog converters and method of operating such the circuit |
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WO2002023727A2 (en) * | 2000-09-11 | 2002-03-21 | Broadcom Corporation | Method and apparatus for mismatch shaping of an oversampled converter |
US6476748B1 (en) * | 2001-04-20 | 2002-11-05 | Silicon Wave, Inc. | Method and apparatus for cyclic return to zero techniques for digital to analog convertors |
US6738003B2 (en) * | 2002-07-08 | 2004-05-18 | Cirrus Logic, Inc. | Delta-sigma modulation circuits and methods utilizing multiple noise attenuation bands and data converters using the same |
US6864819B2 (en) * | 2003-05-09 | 2005-03-08 | Broadcom Corporation | State delayed technique and system to remove tones of dynamic element matching |
US7679539B2 (en) * | 2008-03-25 | 2010-03-16 | Megawin Technology Co., Ltd. | Randomized thermometer-coding digital-to-analog converter and method therefor |
US8159381B2 (en) | 2010-05-12 | 2012-04-17 | Stmicroelectronics Pvt. Ltd. | Glitch free dynamic element matching scheme |
US9622173B2 (en) * | 2014-06-20 | 2017-04-11 | GM Global Technology Operations LLC | Power efficient, variable sampling rate delta-sigma data converters for cellular communications systems |
WO2015196175A1 (en) | 2014-06-20 | 2015-12-23 | Hrl Laboratories, Llc | Interleaved modulator |
US9608661B2 (en) * | 2014-11-06 | 2017-03-28 | GM Global Technology Operations LLC | Software programmable cellular radio architecture for wide bandwidth radio systems including telematics and infotainment systems |
US9698845B2 (en) | 2014-11-06 | 2017-07-04 | GM Global Technology Operations LLC | High oversampling ratio dynamic element matching scheme for high dynamic range digital to RF data conversion for radio communication systems |
US9685976B2 (en) | 2015-06-23 | 2017-06-20 | Microelectronics Research & Development Corp. | Methods and devices for modifying active paths in a K-delta-1-sigma modulator |
US9762258B2 (en) * | 2015-07-29 | 2017-09-12 | University Of Limerick | Mismatch and inter symbol interference (ISI) shaping using dynamic element matching |
US9543974B1 (en) * | 2015-09-18 | 2017-01-10 | Analog Devices, Inc. | Reducing switching error in data converters |
US9455737B1 (en) | 2015-09-25 | 2016-09-27 | Qualcomm Incorporated | Delta-sigma analog-to-digital converter (ADC) with time-interleaved (TI) or two-step successive approximation register (SAR) quantizer |
US9735797B2 (en) * | 2015-12-15 | 2017-08-15 | Analog Devices, Inc. | Digital measurement of DAC timing mismatch error |
US9966969B1 (en) * | 2017-04-18 | 2018-05-08 | Analog Devices, Inc. | Randomized time-interleaved digital-to-analog converters |
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US20190165820A1 (en) | 2019-05-30 |
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