EP3700618A1

EP3700618A1 - Optical sensor

Info

Publication number: EP3700618A1
Application number: EP18788782.3A
Authority: EP
Inventors: Alain CAPPY; François DANNEVILLE; Virginie HOEL; Christophe Loyez; Ilias SOURIKOPOULOS
Original assignee: Centre National de la Recherche Scientifique CNRS; Universite Lille 2 Droit et Sante; Ecole Centrale de Lille; Universite Polytechnique Hauts de France; Yncrea Hauts de France
Current assignee: Centre National de la Recherche Scientifique CNRS; Universite Lille 2 Droit et Sante; Ecole Centrale de Lille; Universite Polytechnique Hauts de France; Yncrea Hauts de France
Priority date: 2017-10-25
Filing date: 2018-10-24
Publication date: 2020-09-02
Also published as: JP7321171B2; US11478634B2; FR3072564B1; KR20200105809A; TW201929917A; IL274168B2; JP2021500215A; CN111542367B; US20200346004A1; TWI775971B; CN111542367A; WO2019081562A1; IL274168B1; IL274168A; FR3072564A1

Abstract

The invention relates to an optical sensor (1), in particular an artificial retina, with at least one photosensitive cell, each cell including: - an integration capacitor (Cm), - a reading circuit (10) of which the operation depends on the charge of the integration capacitor (Cm), - at least one MOS transistor (3; 31; 32) operating below the threshold, the drain-to-source current of which influences the charge of the integration capacitor (Cm), - at least one photodiode (2; 21; 22) operating in photovoltaic mode, connected to the gate of this transistor, so that the drain-to-source current of the MOS transistor depends on the optical power received by the photodiode.

Description

OPTICAL SENSOR

The present invention relates to a circuit with low energy consumption, which can reproduce certain behaviors of a biological retina, and used in particular in bio-inspired architectures.

It has already been proposed various systems for acquisition and processing of visual information, and implants to compensate for a visual impairment.

The application FR 2 953 394 discloses an artificial retina comprising a substrate, a first layer disposed thereon comprising portions of photovoltaic material separated by a portion of insulating material and a second layer disposed on the first and comprising portions of conductive material. separated by a portion of insulating material.

The system described in US Pat. No. 5,865,839 is small enough to be implantable in the human eye, and comprises a set of artificial retinas each of which has a detector element and an optical fiber for directing the incident light to the detector element. . The latter emits an output signal depending on the intensity of the incident light. A coupler couples this output signal to the human retina.

US Patent 5,024,223 discloses an implant having a matrix of photodiodes implanted between the inner and outer layers of a human retina. The photoactive surface of each photodiode points to the incident light. The implant produces an amplitude-modulated current to electrically stimulate the inner layer of the retina.

US Patent 6,046,444 discloses a pixel structure having a photodiode operating in photo-ampere mode where it is reverse biased, its anode being grounded and its cathode to the gate of an NMOS transistor configured in source-follower mode. The invention aims to further improve the optical sensors and retinal implants in particular, in particular to have a powerful sensor, extremely low power consumption and able to simulate to some extent the behavior of the retina.

The invention thus has, according to a first aspect, an optical sensor, in particular an artificial retina, with at least one photosensitive cell, each cell comprising:

FIRE I LLE OF REM PLACEM ENT (RULE 26) - an integration capacity,

a read circuit whose operation depends on the load of the integration capacity,

at least one MOS transistor operating below the threshold, the source drain current of which influences the load of the integration capacitor,

at least one photodiode operating in photovoltaic mode, connected to the gate of this transistor, such that the source drain current of the MOS transistor depends on the optical power received by the photodiode.

The operation of the transistor below the threshold corresponds to the existence of a drain-source current varying exponentially with the gate control voltage in the so-called weak inversion region of the transistor ('weak-inversion region' or 'subthreshold region' in English) where the gate-source voltage is below the threshold voltage for which the inversion zone appears, that is, creates a conduction channel between the drain and the source.

The open-circuit voltage of the photodiode, V _co , resulting from the photoelectric conversion, is applied to the gate of the transistor. Since the relation between the photocurrent and the photovoltaic voltage V _oc of the photodiode is logarithmic, the result is an electrical drain current substantially proportional to the photoelectric current, and therefore to the optical power. This is a remarkable result and allows the cell to present a substantially linear response depending on the illumination. The invention also allows a large scale integration of the optical sensor, thanks to the possibility of using a standard industrial CMOS technology.

The MOS transistor may be arranged within the cell, either to load the integration capacitor or to discharge it, depending on how the reading circuit behaves with the charge level of this capacitance and the desired behavior. for the cell according to the illumination received.

Thus, the aforementioned MOS transistor may be an activation transistor arranged to charge the integration capacitance when the photodiode connected to its gate is illuminated. In this case, the activation transistor is preferably of the PMOS type.

In a variant, the MOS transistor may be a deactivation transistor arranged to discharge the integration capacitance when the photodiode connected to its gate is illuminated. In this case, the deactivation transistor is preferably of the NMOS type.

FIRE I LLE OF REM PLACEM ENT (RULE 26) The cell may comprise a plurality of activation transistors connected in parallel and each controlled by a photodiode connected to a respective gate, operating in photovoltaic mode, each activation transistor being arranged to charge the integration capacitance when the photodiode is illuminated, the currents adding algebraically to the same node.

The cell may also comprise a plurality of deactivation transistors connected in parallel and each controlled by a photodiode connected to a respective gate, operating in photovoltaic mode, each deactivation transistor being arranged to discharge the integration capacitance when the photodiode is illuminated, the currents adding algebraically to the same node.

It is thus possible to make a cell having as many photodiodes as desired, and to make as many cells having as many distinct light behaviors, depending on the number of activation and deactivation transistors used and the spatial arrangement of the corresponding photodiodes.

Thus, in exemplary embodiments of the invention, the cell comprises: at least one activation MOS transistor, operating below the threshold, the source drain current of which influences the load of the integration capacitor,

at least one photodiode operating in photovoltaic mode, connected to the gate of this activation transistor, such that the source drain current depends on the optical power received by the photodiode, the activation transistor being arranged to charge the capacitance of integration when the photodiode is illuminated, at least one deactivating MOS transistor, operating below the threshold, the source drain current of which influences the load of the integration capacitor,

at least one photodiode operating in photovoltaic mode, connected to the gate of this deactivation transistor, such that the source drain current depends on the optical power received by the photodiode, the deactivation transistor being arranged to discharge the integration capacitance when the photodiode is illuminated.

In biology, the neurons of the different layers of the retina each cover a region of our visual field. This region of space where the presence of a suitable stimulus modifies the nerve activity of a neuron is called the receptor field of this neuron. Thus, the receptor fields of bipolar and ganglion cells are circular in shape. Their center and periphery, however, work in opposition: a ray of light that strikes the

FIRE I LLE OF REM PLACEM ENT (RULE 26) center of the field will have the opposite effect when it falls on the periphery. There are two types of bipolar cells according to the response of their receptor field. If a light stimulus on the center has an excitatory effect on the bipolar cell, it undergoes a depolarization. It is said that it is of type "ON". A ray of light falling only on the periphery of the field of this cell will have the opposite effect, that is, a hyperpolarization of the membrane. Other bipolar cells, of the "OFF" type, will show exactly the opposite behavior: the light on the center produces a hyperpolarization while a luminous stimulus on the periphery has an excitatory effect.

The interest of the ON and OFF cells is to detect either an optical power value at a point but a contrast between the center and the periphery of a zone.

By analogy with the biological retina, the cell may be of the "ON" type, comprising a plurality of deactivation transistors and associated photodiodes, the photodiode associated with the activation transistor being surrounded by the photodiodes associated with the deactivation transistors. The cell may be of the "OFF" type, comprising a plurality of activation transistors and associated photodiodes, the photodiode associated with the deactivation transistor being surrounded by the photodiodes associated with the activation transistors. The photodiodes associated with the deactivation transistors in the case of an "ON" cell or the photodiodes associated with the activation transistors in the case of an "OFF" cell may be arranged in a polygonal mesh, with in particular at least four photodiodes and corresponding transistors of the deactivator type, respectively activator, within the cell.

The power supply of the sensor can be done in various ways.

The optical sensor preferably comprises a source of autonomous electrical energy, preferably photovoltaic. It may thus comprise one or more photodiodes of the same type as the photosensitive cell or cells dedicated to feeding the sensor, preferably several photodiodes connected in series, so as to increase the voltage supplied.

The arrangement of the photodiodes of power supply can be various.

Preferably, the source of autonomous electrical energy comprises several photodiodes arranged around a matrix of photosensitive cells or distributed between the photosensitive cells.

FIRE I LLE OF REM PLACEM ENT (RULE 26) The reading circuit can be realized in various ways. It must be sensitive to a weak synaptic current, hence the use of transistor (s) operating below the threshold at the cell.

The read circuit itself may consist of any current measuring circuit, without specific constraint of operation in current or voltage.

Preferably, the read circuit comprises at least one artificial neuron.

For example, the artificial neuron may be spikes (impulses) of Axon-Hillock type, Morris-Lecar type, etc.

By analogy with biology, the photodiode can then correspond to a cone or rod, the transistor associated with one or more horizontal cells, bipolar and amacrine, and the artificial neuron to a ganglion cell generating pulses.

Advantageously, the artificial neuron is arranged to generate pulses at a frequency which depends on the charge level of the integration capacitor and therefore on the optical power received by at least one photodiode.

Preferably, the artificial neuron is at very low power consumption, and uses transistors operating below the threshold, so as to operate with a reduced supply voltage (V _d d <Vt).

Most preferably, at least the impulse circuit of the artificial neuron is powered by a power supply (VN, Vp) for which the negative voltage (VN) is between -200 mV and 0 mV and the positive voltage (Vp) included between 0 mV and +200 mV.

Preferably, (VP-VN) <Vth, Vth being the threshold voltage of all the MOS transistors of the artificial neuron.

For convenience, for purposes of agreement between the voltages respectively supplying the neuron and the sensor, V _p = Vdd is preferably chosen.

According to a quite preferred variant, the artificial neuron comprises:

an external synaptic input current defined by a terminal of the integration capacitor and carrying out the algebraic sum of the activation and deactivation currents,

a feedback pulse circuit comprising:

FIRE I LLE OF REM PLACEM ENT (RULE 26) a bridge with PMOS and NMOS transistors in series and connected in their drains by a midpoint to the integration capacity, this midpoint defining the output of the artificial neuron,

at least one so-called delay capacitance between the gate and the source of one of the transistors of the bridge,

only two cascaded CMOS inverters, each consisting of two transistors, the input of the first inverter being connected to the integration capacitor and its output to the input of the second inverter and to the gate of one of the transistors of the bridge the output of the second inverter being connected to the gate of the other transistor of the bridge, or

only three CMOS inverters including two inverters are in cascade, each consisting of two transistors, the input of the first inverter being connected to the integration capacitor and its output to the input of the second inverter, the output of the second inverter being connected at the gate of one of the transistors of said bridge, the input of the third CMOS inverter being connected to the integration capacitor and the output of the third CMOS inverter being connected to the gate of the other transistor of said bridge.

All the transistors of the artificial neuron preferably operate below the threshold, thus generating a low power consumption. The subject of the invention is also, independently or in combination with the foregoing, the variants as defined below:

Artificial neuron comprising:

an external synaptic current input defined by a terminal of the integration capacitor and carrying out the algebraic sum of the activation and deactivation currents,

a feedback pulse circuit powered by a negative voltage supply of between -200 mV and 0 mV and a positive voltage of between 0 mV and +200 mV, comprising:

^■ A bridge PMOS and NMOS transistors in series and connected by their drains by a middle point in the integration capacitor, this mid-point defining the output of the artificial neuron,

^■ At least one delay of said capacitance between the gate and the source of one of the bridge transistors,

FIRE I LLE OF REM PLACEM ENT (RULE 26) at least two CMOS inverters between the integration capacitance and the gates of the transistors of said bridge so as to cause the transistors of the bridge to change state as a function of the voltage of the integration capacitor and to allow the pulse circuit to generate at least one pulse when the voltage of the integration capacitance crosses a predefined threshold, with load of the integration capacitor by one of the transistors of the bridge and discharged by the other transistor.

Artificial neuron comprising:

a feedback pulse circuit comprising:

at least two CMOS inverters between the integration capacitance and the gates of the transistors of said bridge so as to cause the transistors of the bridge to change state as a function of the voltage of the integration capacitor and to allow the pulse circuit to generate at least one pulse when the voltage of the integration capacitance crosses a predefined threshold, with loading of the integration capacitor by one of the transistors of the bridge and discharge by the other transistor, said neuron being remarkable in that the delay capacitance connected to the NMOS transistor is greater than the integration capacitance.

Artificial neuron comprising:

a feedback pulse circuit comprising:

FIRE I LLE OF REM PLACEM ENT (RULE 26) ^■ At least one delay of said capacitance between the gate and the source of one of the bridge transistors,

at least two CMOS inverters between the integration capacitance and the gates of the transistors of said bridge so as to cause the transistors of the bridge to change state as a function of the voltage of the integration capacitor and to allow the pulse circuit to generate at least one pulse when the voltage of the integration capacitance crosses a predefined threshold, with loading of the integration capacitor by one of the transistors of the bridge and discharge by the other transistor, said neuron being remarkable in that it comprises two cascaded CMOS inverters, the input of the first inverter being connected to the membrane capacitance (Cm) and its output to the input of the second inverter, the output of the second inverter being connected to the gate of one of the transistors of said bridge, and a third CMOS inverter whose input is connected to the membrane capacitance (Cm) and the output to the gate of the other transistor of said bridge.

In other variants, the read circuit comprises a neural network.

Advantageously, this neuronal network comprises at least two artificial neurons called pre-neuron and post-neuron neurons, connected together by a synaptic circuit in the form of an excitatory or inhibitory synapse.

Excitatory synapses, favoring the creation of an action potential by postneuron, depolarize the post-neuron membrane (ie increase its potential) and have a role similar to that of sodium channels in biology.

Inhibitory synapses, which are detrimental to the creation of an action potential by the postneurone, hyper-polarize the post-neuron membrane (ie decrease its potential) and have a role similar to that of the potassium channels in biology.

In certain preferred subvariants, said neuron network implements transistor neurons operating below the threshold. In this case, advantageously, an excitatory synapse may be represented by two series transistors connected between the positive supply Vp and the post-neuron membrane:

• a PMOS transistor whose gate is connected to the membrane voltage of the inverted preneurone. This signal can be collected at the output of any suitable inverter (belonging to the artificial neuron or not), the source being at potential Vp.

FIRE I LLE OF REM PLACEM ENT (RULE 26) A MOS transistor (N or P) whose gate is connected to a control voltage VI which makes it possible to control the charge current of the post-neuron membrane.

Advantageously, an inhibitory synapse can be represented by two series transistors connected between the post-neuron membrane and the negative VN supply:

An NMOS transistor whose gate is connected to the output of two cascaded inverters whose input is the membrane voltage of the pre-neuron. This signal can be collected at the output of a couple of suitable cascade inverters (belonging to the artificial neuron or not), the source being at the potential VN.

A MOS transistor (N or P) whose gate is connected to a control voltage VI which makes it possible to control the discharge current of the post-neuron membrane.

According to the invention, each photosensitive cell advantageously comprises several photodiodes and associated transistors, constituting as many pixels of the sensor, and a single reading circuit per cell. The pixels can be of the same size, having the same photodiode surface. Otherwise, the pixels may be of different size, as is the case for logarithmic sensors, for example.

Finally, in order to make the sensor more sensitive to weak illumination and less sensitive to strong illumination and thus limit the frequency of pulses in a frequency band that is not very sensitive to the absolute value of illumination, by automatic gain control, it can be useful to stabilize the neuron under strong illumination and to destabilize it under low illumination.

This can be done in advanced variants of the sensor using a photodiode (or a set of photodiodes) as a control of one (or more) transistor (s) acting synapse (s) inhibitor (s).

At low illumination, this synapse plays no role and the neuron can be made very sensitive. At high illuminance, the current generated in the inhibitory synapse the membrane reduces its sensitivity.

The invention will be better understood on reading the detailed description which follows, examples of non-limiting implementation thereof, and on examining the appended drawing, in which:

FIRE I LLE OF REM PLACEM ENT (RULE 26) FIGS. 1 and 2 are diagrammatic representations of a sensor according to the invention,

FIG. 3 illustrates an example of adjustment of the synaptic weight in the case of a photodiode associated with a transistor operating under the threshold as an excitatory synapse,

FIG. 4 represents an elementary association of an activating transistor and a deactivating transistor within a sensor according to the invention,

FIGS. 5 and 6 respectively illustrate the implementation of an ON cell and an OFF cell,

FIGS. 7 and 8 are matrix representations of an ON or OFF cell from a central pixel and its neighbors, respectively according to a rectangular network and hexagonal network distribution,

FIG. 9 illustrates an example of control of the frequency of the pulses as a function of the optical power received over a certain number of pixels,

FIGS. 10 and 11 respectively represent the arrangement of an external photovoltaic power supply or integrated into the sensor,

Fig. 12 illustrates an example of an integrated photovoltaic power supply, and Figs. 13 and 14 show exemplary structures of an artificial neuron with two inverters and three inverters, respectively.

FIGS. 1 and 2 show diagrammatically an optical sensor 1 according to the invention. Such a sensor may comprise, as illustrated, a PMOS transistor 3, a photodiode 2, an integration capacitor C _m and a read circuit 10.

In FIG. 1, the photodiode 2 is connected to the gate of the transistor 3 by its cathode, its anode being connected to the supply voltage Vdd. The drain of the transistor 3 is connected to a terminal of the integration capacitor C _m also constituting an input-output of the reading circuit 10.

The photodiode 2 operates in photovoltaic open circuit mode where the voltage at its terminals is strictly positive, V _co > 0, and the current flowing through it is zero. In this mode, the photodiode is able to generate energy, contrary to the usual mode (receiver mode) in which the photodiode is reverse biased.

The transistor 3 operates below the threshold, and the drain current in it varies exponentially with the gate-source voltage, and therefore with the open circuit voltage of the

FIRE I LLE OF REM PLACEM ENT (RULE 26) photodiode 2. Transistor 3 operating below the threshold is comparable to an excitatory synapse.

By relying on the current-voltage relation of the PMOS transistor, a relation is obtained between the open-circuit voltage V _co generated by the photodiode and the current Ids from the transistor:

In equation (1), G _p is the conductance of the transistor, η the ideality coefficient of the current-voltage characteristic Ids (V _gs ) of the transistor and V _m the voltage across the capacitor as shown.

The cathode of the photodiode is connected to the gate of the PMOS transistor. This leads de facto that the total current I of the photodiode, whose expression is the following, is zero:

/ = I _s (xp (^) - l) - I _ph (2)

~ NVT

where Vt = kT / q is the thermal potential, I _s the saturation current of the PN junction constituting the photodiode and I _p h the photo-current generated by the photodiode defined by: QPppt

where q is the charge of the electron, h is the Planck constant, v is the frequency of the optical signal, Q is the quantum efficiency, and P _op t is the optical power,

As a result, the illumination produces a photovoltaic voltage in open circuit Vco which is expressed as follows:

V _co = nV _t . Ln (l + - ') m with n the ideality coefficient of the voltage-current characteristic of the photodiode.

FIRE I LLE OF REM PLACEM ENT (RULE 26) Introducing (4) into (1) gives:

and assuming that the ideality coefficients n and η are of the same order of magnitude, the expression of the drain-source current of the transistor 3 influencing the load of the integration capacitance C _m is obtained:

In the most frequent mode, the photo-current I _p h is much larger than the reverse current I _s of the unpolarized junction. From where :

A substantially linear relationship is thus obtained between the drain-source current and the photocurrent and thus between the drain-source current and the optical power received.

In FIG. 2, the photodiode 2 is connected to the gate of the transistor 3 by its anode, its cathode being connected to the supply voltage V _ss . The drain of the transistor 3 is connected to a terminal of the integration capacitor C _m also constituting an input-output of the reading circuit 10. The transistor 3 operating below the threshold is comparable to an inhibitory synapse.

If the read circuit 10 is an artificial neuron, this drain-source current can be called synaptic current. The 'weight' of the synapse can be adjusted for example:

By the sizing of the transistor, and in particular by the conductance G _p of the transistor, which is proportional to the width of the gate and inversely proportional to its length,

With the aid of an adjustment transistor (N or P) placed between the transistor 3 which operates below the threshold and the integration capacitance C _m (when the transistor 3 is similar to an excitatory synapse, said Adjustment transistor 4 is placed between the drain of transistor 3 operating below the threshold and the integrating capacitance C _m , as shown in FIG. 3).

FIRE I LLE OF REM PLACEM ENT (RULE 26) The global synaptic current can excite or inhibit the artificial neuron, among others depending on the role of transistor 3 operating under the threshold (respectively excitatory or inhibitory synapse).

The neuron can be easily connected to neighboring photovoltaic cells to create contrast-sensitive cells, such as in a biological retina.

FIG. 4 illustrates an example of elementary connection of the photodiodes in an excitation or inhibition configuration.

Without applied optical power, the neuron 10 can be stable (does not generate pulses) or unstable (low frequency pulse generation). The photodiode 21 is connected to a PMOS transistor 31 equivalent to an excitatory synapse of the artificial neuron 10. It tends to promote the generation of pulses by the neuron 10 or to increase the frequency thereof. The photodiode 22 is connected to an NMOS transistor 32 equivalent to an inhibitory synapse. It tends to reduce the aforementioned frequency. Since photodiodes operate in an open circuit, the same photodiode can be connected to different synapses without modifying its properties.

As a variant, it is possible to perform a more complex processing of the received optical signals by associating several photodiodes with the same neuron 10.

Any combination of activation and deactivation transistors is possible because all the currents will be added algebraically to the same node constituting the input-output of the neuron. For example, the equivalent of the ON and OFF cells of the biological retina can be created.

FIG. 5 represents an artificial implementation of an ON cell with a photodiode 21 associated with an activator transistor 31 acting as excitatory synapse at the center and a plurality of photodiodes 22 associated with deactivating transistors 32 connected in parallel and acting as inhibitory synapses at the periphery . The number of photodiodes 22 associated with the deactivating transistors 32 will be chosen according to the application and the targeted characteristics.

FIG. 6 represents an artificial implementation of an OFF cell with a photodiode 22 associated with a deactivating transistor 32 acting as an inhibitory synapse in the center and several photodiodes 21 associated with activating transistors 31 connected in parallel and acting as excitatory synapses at the periphery .

FIRE I LLE OF REM PLACEM ENT (RULE 26) FIG. 7 describes an elementary association by considering a "square" (square or rectangular) type matrix of pixels 40, among which we can consider sub-assemblies consisting of central pixels 50 and peripheral pixels 55. If we operate a corresponding to FIG. 5 (diagram representing an ON cell), the pixel 50 in the center of FIG. 7 corresponds to the photodiode whose cathode is connected to the gate of the activating transistor PMOS (excitatory synapse), whereas the four peripheral pixels 55 surrounding the pixel of the center 50 have their cathode connected to ground and their anode connected to the gate of an NMOS deactivator transistor (synapse inhibitor).

For uniform illumination of photodiodes, the artificial neuron will have a relatively low pulse frequency, or even zero.

If the illumination is strong at the pixel 50 of the center, the global excitation current on the neuron membrane will increase and the pulse frequency too.

If the illumination is strong at the peripheral pixels 55 of the periphery, the sum of the inhibition currents will be greater than the excitation current and the neuron will generate no more pulses (or very little, that is to say that the pulse frequency is relatively low, even zero as in case of uniform illumination).

An architecture dual to that of the circuit of FIG. 7 can also be used in order to obtain an OFF cell as shown in FIG. 6 where the center pixel 50 is associated with an inhibitory synapse (photodiode connected to a deactivating transistor) and the four peripheral pixels 55 of the periphery are associated with excitatory synapses (photodiodes connected to activating transistors).

The topology organized into a "square" type matrix can be changed to a hexagonal configuration like that presented in FIG. 8. Any polygonal topology is of course possible. In general, for a combination of N excitatory pixels and M inhibiting pixels, the total synaptic current I _to t applied to the neuron is expressed as follows:

FIRE I LLE OF REM PLACEM ENT (RULE 26)

In normal operation of the photodiode, the photo-current I _p h is much larger than the reverse current I _s of the different junctions. Then we will have: j - (\ 7 _ \ 7 \ ^G exc, i _T ph _

hot - KYdd ^v mJ Li = i,. _βχο

^L S, l

C \ 7 \ i ^M M ^{u G} iinhh, j _r pphh

I inh (9) <s, j

The conductances G _eX c, i and Ginhj of the transistors may be adjusted by the parameters of the transistors (length and gate width, for example) as a function of the application.

As the human eye does very well, it is desirable for an artificial vision system to be able to adapt to the average luminance of the scene and to be able to detect outlines and shapes in both low and high brightness. For this purpose, it is possible to use, as illustrated in FIG. 9, several deactivating transistors 32. Thus, for the high luminosities, the neuron will be hyperpolarized by a strong current in the deactivating transistors 32, which creates a leak which discharges the capacitance integration, and in case of low light, the neuron will be depolarized by reduction or cancellation of this leakage current.

FIGS. 10 and 11 show two ways of producing the energy required to operate an optical sensor 1. In FIG. 10, photovoltaic supply cells 100 are placed around the pixels, and in FIG. arranged in rows alternating with those of the pixels. In the case where the power supply is integrated with the sensors, to generate a sufficient voltage of a few hundred mV, two or more diodes 25 may be put in series, as illustrated in FIG.

FIG. 13 schematically illustrates an exemplary embodiment of the artificial neuron 10. In this example, the artificial neuron 10 comprises two inverters 5 and 6 connected in cascade, the output of the first being connected to the input of the second. The output of the first inverter 5 is connected to the gate of a PMOS transistor 8. The output of the second inverter is connected to the gate of an NMOS transistor 7.

FIRE I LLE OF REM PLACEM ENT (RULE 26) Transistors 7 and 8 are electrically connected in series and form a bridge between supply voltage Vdd and ground. The mid-point 9, defining the connection of the drains of the transistors of the bridge, is connected to a terminal of the integration capacitor C _m . The other terminal of the integration capacitance C _m is connected to ground. A capacitance Ck is connected between the ground and the gate of the NMOS transistor 7. A capacitance C _na is connected between Vdd and the gate of the PMOS transistor 8.

Iex denotes the external excitation current, which charges or discharges the integration capacitance C _m and which originates from the activation or deactivation transistor or transistors.

When the potential at the terminals of the integration capacitance C _m reaches the threshold voltage of the first inverter 5, a corresponding potential is then transmitted after a first inversion by the inverter 5 to the gate of the PMOS transistor 8, activating the latter after a delay defined by the capacity C _na . Thus, the integration capacitance C _m is charged by the open conduction channel of the PMOS transistor 8. This charge corresponds to the rising edge of the output action potential. When the threshold voltage of the second inverter 6 is reached, a corresponding potential is transmitted to the gate of the NMOS transistor 7, activating the latter after a delay defined by the delay capacitance Ck, which is in the example considered longer than the PMOS activation time, due to the choice of Ck> C _na . Thus, after having had time to load, the integration capacitance C _m begins to discharge at the opening of the conduction channel of the NMOS transistor 7. This discharge corresponds to the falling edge of the output action potential.

FIG. 14 schematically shows an artificial neuron 10 according to another embodiment, which differs from that of FIG. 13 by the addition of a third inverter 12, the first inverter 13 transmitting the output potential after inversion to the gate of the PMOS transistor 8 of the bridge and the two other inverters 11 and 12, connected in cascade, transmitting the output potential to the gate of the NMOS transistor 7.

The inputs of the inverters 13 and 11 are connected to the midpoint 9 of the bridge and the integration capacitor, and the input of the inverter 12 is connected to the output of the inverter 11.

The addition of the third inverter makes it possible to independently optimize the controls of the transistors of the bridge, by independently adjusting the threshold voltages of the inverters.

FIRE I LLE OF REM PLACEM ENT (RULE 26) The adjustment of the voltage gain and threshold voltages of the inverters influences the operation of the artificial neuron 10.

Preferably, the threshold voltage of the neuron that produces the action potential is the threshold voltage of the inverter supplying the PMOS transistor of the bridge. The number of inverters used can be defined according to objectives of speed or energy consumption.

Among the variants in which the reading circuit no longer comprises a single transistor neuron operating below the threshold but a network of transistor neurons operating below the threshold, preference will be given to the sub-variants in which the synaptic circuit has two inputs and comprises two transistors. connected in series by their drains, at least one of said transistors being of NMOS type controlled by a gate potential corresponding to the first input of the synaptic circuit, the gate of the second transistor corresponding to the second input of the synaptic circuit, the output of the synaptic circuit corresponding to the source of the NMOS transistor being connected to the output potential of the post-neuron.

By way of example, said synaptic circuit may correspond to:

An excitatory synapse where the second input of the synaptic circuit is connected to the output of an inverter (preferably the first inverter of the preneurone) having as input the membrane potential of the pre-neuron, in particular at the gate of the PMOS transistor of the bridge of the pre-neuron, or

An inhibitory synapse where the second input of the synaptic circuit is connected to the output of two inverters in series (preferentially the two cascaded inverters of the pre-neuron) whose input of the first is subjected to the membrane potential of the pre-neuron, or

An inhibitory synapse where the second input of the synaptic circuit is connected to the gate of the NMOS transistor of the pre-neuron bridge.

Of course, the invention is not limited to the embodiments which have just been described.

The invention is particularly applicable to retinal implants, but nevertheless covers a broad application spectrum. It can for example be used in robotics, home automation, image and video processing, etc. The architecture of the artificial neuron associated with a cell of the optical sensor according to the invention may be other than those described above.

FIRE I LLE OF REM PLACEM ENT (RULE 26)

Claims

An optical sensor (1), especially an artificial retina, with at least one photosensitive cell, each cell comprising:

an integration capacity (C _m ),

a read circuit (10) whose operation depends on the load of the integration capacitor (C _m ),

at least one MOS transistor (3; 31; 32) operating below the threshold, the source drain current of which influences the load of the integration capacitance (C _m ),

at least one photodiode (2; 21; 22) operating in photo voltaic mode, connected to the gate of this transistor, such that the source drain current of the MOS transistor depends on the optical power received by the photodiode.

2. Sensor (1) according to the preceding claim, the transistor (3; 31) being an activation transistor arranged to charge the integration capacitance (C _m ) when the photodiode (2; 21) connected to its gate is illuminated. .

3. Sensor (1) according to claim 2, the activation transistor (3; 31) being PMOS type.

4. Sensor (1) according to claim 1, the transistor (32) being a deactivation transistor arranged to discharge the integration capacitance (C _m ) when the photodiode (22) connected to its gate is illuminated.

5. Sensor (1) according to claim 4, the deactivation transistor (32) being of NMOS type.

6. Sensor (1) according to any one of the preceding claims, the cell comprising a plurality of activation transistors (3; 31) connected in parallel and each controlled by a photodiode (2; 21) connected to a respective gate, operating in accordance with FIG. photovoltaic mode, each activation transistor (3; 31) being arranged to charge the integration capacitance (C _m ) when the photodiode (2; 21) is illuminated.

7. Sensor (1) according to any one of the preceding claims, the cell comprising a plurality of deactivation transistors (32) connected in parallel and each controlled by a photodiode (22) connected to a respective gate, operating in photovoltaic mode, each transistor deactivating circuit (32) being arranged to discharge the integration capacitance (C _m ) when the photodiode (22) is illuminated.

8. Sensor (1) according to any one of the preceding claims, the cell comprising:

at least one activation MOS transistor (3; 31), operating below the threshold, whose source drain current influences the load of the integration capacitor (C _m ), at least one photodiode (2; 21) operating in photovoltaic mode, connected to the gate of this activation transistor (3; 31), so that the source drain current depends on the optical power received by the photodiode (2; 21), the activation transistor (3; 31) being arranged to charge the integration capacitance (C) when the photodiode (2; 21) is illuminated,

at least one deactivating MOS transistor (32), operating below the threshold, whose source drain current influences the load of the integration capacitor (C _m ), and at least one photodiode (22) operating in photovoltaic mode, connected to the gate of this deactivation transistor (32), so that the source drain current depends on the optical power received by the photodiode (22), the deactivation transistor (32) being arranged to discharge the integration capacitor ( C _m ) when the photodiode (22) is illuminated.

9. The sensor (1) according to claim 8, the cell being of "ON" type, comprising a plurality of deactivation transistors (32) and associated photodiodes (22), the photodiode (2; 21) associated with the activation transistor (3). 31) being surrounded by the photodiodes (22) associated with the deactivation transistors (32).

10. Sensor (1) according to claim 8, the cell being of type "OFF", comprising a plurality of activation transistors (3; 31) and associated photodiodes (2; 21), the photodiode (22) associated with the deactivation transistor. (32) being surrounded by the photodiodes (2; 21) associated with the activation transistors (3; 31).

11. The sensor (1) according to claim 9 or 10, the photodiodes (22) associated with the deactivation transistors (32) in the case of an "ON" cell or the photodiodes (2; 21) associated with the activation transistors. (3; 31) in the case of an "OFF" cell, being arranged in a polygonal mesh, with in particular at least four photodiodes and corresponding transistors of the deactivator type, respectively activator, within the cell.

12. Sensor (1) according to any one of the preceding claims, comprising a source of autonomous electrical energy (100), preferably photovoltaic, better comprising one or more photodiodes of the same type as those of the one or more photosensitive cells, dedicated to supplying the sensor (1), preferably several photodiodes (25) connected in series.

13. The sensor (1) according to claim 12, the source of autonomous electrical energy (100) comprising a plurality of photodiodes arranged around a matrix of photosensitive cells or distributed between the photosensitive cells.

14. Sensor (1) according to any one of the preceding claims, the read circuit comprising at least one artificial neuron (10).

15. The sensor (1) according to claim 14, the artificial neuron (10) generating pulses at a frequency that depends on the optical power received by at least one photodiode.

16. Sensor (1) according to any one of claims 14 and 15, the artificial neuron (10) comprising:

an external synaptic input current (I _ex ) defined by a terminal of the integration capacitance (C _m ) and performing the algebraic sum of the activation and deactivation currents,

a feedback pulse circuit comprising:

a PMOS transistors bridge (8) and NMOS (7) in series and connected in their drains by a midpoint (9) to the integration capacitance (C _m ), this midpoint (9) defining the output of the neuron artificial (10),

at least one so-called delay capacitance (Cm, Ck) between the gate and the source of one of the transistors (7, 8) of the bridge,

only two in-cascade CMOS inverters (5, 6), each consisting of two transistors, the input of the first inverter (5) being connected to the integration capacitor (Cm) and its output to the input of the second inverter ( 6) and to the gate of one of the transistors of the bridge (7; 8), the output of the second inverter (6) being connected to the gate of the other transistor of the bridge (7; 8), or

only three inverters (11, 12, 13) CMOS including two inverters (11, 12) are in cascade, each consisting of two transistors, the input of the first inverter (11) being connected to the integration capacitance (C _m ) and its output at the input of the second inverter (12), the output of the second inverter (12) being connected to the gate of one of the transistors (7; 8) of said bridge, the input of the third CMOS inverter ( 13) being connected to the integration capacitance (C _m ) and the output of the third CMOS inverter (13) being connected to the gate of the other transistor (7; 8) of said bridge.

17. Sensor (1) according to any one of the preceding claims, each photosensitive cell comprising a plurality of photodiodes and associated transistors constituting as many pixels of the sensor, and a single reading circuit (10) per cell.